RubyGems - crabstone - Versions diffs - 3.0.3 - Mend

crabstone 3.0.3

Files changed (302) hide show

checksums.yaml +7 -0
data/CHANGES.md +61 -0
data/LICENSE +25 -0
data/MANIFEST +312 -0
data/README.md +103 -0
data/Rakefile +27 -0
data/bin/genconst +66 -0
data/bin/genreg +99 -0
data/crabstone.gemspec +27 -0
data/examples/hello_world.rb +43 -0
data/lib/arch/arm.rb +128 -0
data/lib/arch/arm64.rb +167 -0
data/lib/arch/arm64_const.rb +1055 -0
data/lib/arch/arm64_registers.rb +295 -0
data/lib/arch/arm_const.rb +777 -0
data/lib/arch/arm_registers.rb +149 -0
data/lib/arch/mips.rb +78 -0
data/lib/arch/mips_const.rb +850 -0
data/lib/arch/mips_registers.rb +208 -0
data/lib/arch/ppc.rb +90 -0
data/lib/arch/ppc_const.rb +1181 -0
data/lib/arch/ppc_registers.rb +209 -0
data/lib/arch/sparc.rb +79 -0
data/lib/arch/sparc_const.rb +461 -0
data/lib/arch/sparc_registers.rb +121 -0
data/lib/arch/systemz.rb +79 -0
data/lib/arch/sysz_const.rb +779 -0
data/lib/arch/sysz_registers.rb +66 -0
data/lib/arch/x86.rb +107 -0
data/lib/arch/x86_const.rb +1698 -0
data/lib/arch/x86_registers.rb +265 -0
data/lib/arch/xcore.rb +78 -0
data/lib/arch/xcore_const.rb +185 -0
data/lib/arch/xcore_registers.rb +57 -0
data/lib/crabstone.rb +564 -0
data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
data/test/MC/AArch64/neon-2velem.s.cs +113 -0
data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
data/test/MC/AArch64/neon-across.s.cs +40 -0
data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
data/test/MC/AArch64/neon-crypto.s.cs +15 -0
data/test/MC/AArch64/neon-extract.s.cs +3 -0
data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
data/test/MC/AArch64/neon-max-min.s.cs +37 -0
data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
data/test/MC/AArch64/neon-mov.s.cs +74 -0
data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
data/test/MC/AArch64/neon-perm.s.cs +43 -0
data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
data/test/MC/AArch64/neon-shift.s.cs +22 -0
data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
data/test/MC/AArch64/neon-tbl.s.cs +21 -0
data/test/MC/AArch64/trace-regs.s.cs +383 -0
data/test/MC/ARM/arm-aliases.s.cs +7 -0
data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
data/test/MC/ARM/arm-it-block.s.cs +2 -0
data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
data/test/MC/ARM/arm-trustzone.s.cs +3 -0
data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
data/test/MC/ARM/arm_instructions.s.cs +25 -0
data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
data/test/MC/ARM/crc32-thumb.s.cs +7 -0
data/test/MC/ARM/crc32.s.cs +7 -0
data/test/MC/ARM/dot-req.s.cs +3 -0
data/test/MC/ARM/fp-armv8.s.cs +52 -0
data/test/MC/ARM/idiv-thumb.s.cs +3 -0
data/test/MC/ARM/idiv.s.cs +3 -0
data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
data/test/MC/ARM/mode-switch.s.cs +7 -0
data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
data/test/MC/ARM/neon-crypto.s.cs +16 -0
data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
data/test/MC/ARM/neon-v8.s.cs +38 -0
data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
data/test/MC/ARM/neon-vswp.s.cs +3 -0
data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
data/test/MC/ARM/thumb-hints.s.cs +12 -0
data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
data/test/MC/ARM/thumb.s.cs +19 -0
data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
data/test/MC/ARM/thumb2-branches.s.cs +85 -0
data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
data/test/MC/ARM/vfp4.s.cs +13 -0
data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
data/test/MC/ARM/vpush-vpop.s.cs +9 -0
data/test/MC/Mips/hilo-addressing.s.cs +4 -0
data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
data/test/MC/Mips/micromips-expansions.s.cs +20 -0
data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
data/test/MC/Mips/mips-expansions.s.cs +20 -0
data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
data/test/MC/Mips/mips-register-names.s.cs +33 -0
data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
data/test/MC/Mips/mips64-instructions.s.cs +3 -0
data/test/MC/Mips/mips64-register-names.s.cs +33 -0
data/test/MC/Mips/mips_directives.s.cs +12 -0
data/test/MC/Mips/nabi-regs.s.cs +12 -0
data/test/MC/Mips/set-at-directive.s.cs +6 -0
data/test/MC/Mips/test_2r.s.cs +16 -0
data/test/MC/Mips/test_2rf.s.cs +33 -0
data/test/MC/Mips/test_3r.s.cs +243 -0
data/test/MC/Mips/test_3rf.s.cs +83 -0
data/test/MC/Mips/test_bit.s.cs +49 -0
data/test/MC/Mips/test_cbranch.s.cs +11 -0
data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
data/test/MC/Mips/test_elm.s.cs +16 -0
data/test/MC/Mips/test_elm_insert.s.cs +4 -0
data/test/MC/Mips/test_elm_insve.s.cs +5 -0
data/test/MC/Mips/test_i10.s.cs +5 -0
data/test/MC/Mips/test_i5.s.cs +45 -0
data/test/MC/Mips/test_i8.s.cs +11 -0
data/test/MC/Mips/test_lsa.s.cs +5 -0
data/test/MC/Mips/test_mi10.s.cs +24 -0
data/test/MC/Mips/test_vec.s.cs +8 -0
data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
data/test/MC/README +6 -0
data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
data/test/MC/Sparc/sparc-vis.s.cs +2 -0
data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
data/test/MC/SystemZ/insn-good.s.cs +2265 -0
data/test/MC/SystemZ/regs-good.s.cs +45 -0
data/test/MC/X86/3DNow.s.cs +29 -0
data/test/MC/X86/address-size.s.cs +5 -0
data/test/MC/X86/avx512-encodings.s.cs +12 -0
data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
data/test/MC/X86/x86-32-avx.s.cs +833 -0
data/test/MC/X86/x86-32-fma3.s.cs +169 -0
data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
data/test/MC/X86/x86_64-encoding.s.cs +59 -0
data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
data/test/README +6 -0
data/test/test.rb +205 -0
data/test/test.rb.SPEC +235 -0
data/test/test_arm.rb +202 -0
data/test/test_arm.rb.SPEC +275 -0
data/test/test_arm64.rb +150 -0
data/test/test_arm64.rb.SPEC +116 -0
data/test/test_detail.rb +228 -0
data/test/test_detail.rb.SPEC +322 -0
data/test/test_exhaustive.rb +80 -0
data/test/test_mips.rb +118 -0
data/test/test_mips.rb.SPEC +91 -0
data/test/test_ppc.rb +137 -0
data/test/test_ppc.rb.SPEC +84 -0
data/test/test_sanity.rb +83 -0
data/test/test_skipdata.rb +111 -0
data/test/test_skipdata.rb.SPEC +58 -0
data/test/test_sparc.rb +113 -0
data/test/test_sparc.rb.SPEC +116 -0
data/test/test_sysz.rb +111 -0
data/test/test_sysz.rb.SPEC +61 -0
data/test/test_x86.rb +189 -0
data/test/test_x86.rb.SPEC +579 -0
data/test/test_xcore.rb +100 -0
data/test/test_xcore.rb.SPEC +75 -0
metadata +393 -0

data/test/MC/ARM/neon-sub-encoding.s.cs ADDED

@@ -0,0 +1,82 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xa0,0x08,0x41,0xf3 = vsub.i8 d16, d17, d16
+0xa0,0x08,0x51,0xf3 = vsub.i16 d16, d17, d16
+0xa0,0x08,0x61,0xf3 = vsub.i32 d16, d17, d16
+0xa0,0x08,0x71,0xf3 = vsub.i64 d16, d17, d16
+0xa1,0x0d,0x60,0xf2 = vsub.f32 d16, d16, d17
+0xe2,0x08,0x40,0xf3 = vsub.i8 q8, q8, q9
+0xe2,0x08,0x50,0xf3 = vsub.i16 q8, q8, q9
+0xe2,0x08,0x60,0xf3 = vsub.i32 q8, q8, q9
+0xe2,0x08,0x70,0xf3 = vsub.i64 q8, q8, q9
+0xe2,0x0d,0x60,0xf2 = vsub.f32 q8, q8, q9
+0x25,0xd8,0x0d,0xf3 = vsub.i8 d13, d13, d21
+0x26,0xe8,0x1e,0xf3 = vsub.i16 d14, d14, d22
+0x27,0xf8,0x2f,0xf3 = vsub.i32 d15, d15, d23
+0xa8,0x08,0x70,0xf3 = vsub.i64 d16, d16, d24
+0xa9,0x1d,0x61,0xf2 = vsub.f32 d17, d17, d25
+0x64,0x28,0x02,0xf3 = vsub.i8 q1, q1, q10
+0x62,0x48,0x14,0xf3 = vsub.i16 q2, q2, q9
+0x60,0x68,0x26,0xf3 = vsub.i32 q3, q3, q8
+0x4e,0x88,0x38,0xf3 = vsub.i64 q4, q4, q7
+0x4c,0xad,0x2a,0xf2 = vsub.f32 q5, q5, q6
+0xa0,0x02,0xc1,0xf2 = vsubl.s8 q8, d17, d16
+0xa0,0x02,0xd1,0xf2 = vsubl.s16 q8, d17, d16
+0xa0,0x02,0xe1,0xf2 = vsubl.s32 q8, d17, d16
+0xa0,0x02,0xc1,0xf3 = vsubl.u8 q8, d17, d16
+0xa0,0x02,0xd1,0xf3 = vsubl.u16 q8, d17, d16
+0xa0,0x02,0xe1,0xf3 = vsubl.u32 q8, d17, d16
+0xa2,0x03,0xc0,0xf2 = vsubw.s8 q8, q8, d18
+0xa2,0x03,0xd0,0xf2 = vsubw.s16 q8, q8, d18
+0xa2,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d18
+0xa2,0x03,0xc0,0xf3 = vsubw.u8 q8, q8, d18
+0xa2,0x03,0xd0,0xf3 = vsubw.u16 q8, q8, d18
+0xa2,0x03,0xe0,0xf3 = vsubw.u32 q8, q8, d18
+0xa1,0x02,0x40,0xf2 = vhsub.s8 d16, d16, d17
+0xa1,0x02,0x50,0xf2 = vhsub.s16 d16, d16, d17
+0xa1,0x02,0x60,0xf2 = vhsub.s32 d16, d16, d17
+0xa1,0x02,0x40,0xf3 = vhsub.u8 d16, d16, d17
+0xa1,0x02,0x50,0xf3 = vhsub.u16 d16, d16, d17
+0xa1,0x02,0x60,0xf3 = vhsub.u32 d16, d16, d17
+0xe2,0x02,0x40,0xf2 = vhsub.s8 q8, q8, q9
+0xe2,0x02,0x50,0xf2 = vhsub.s16 q8, q8, q9
+0xe2,0x02,0x60,0xf2 = vhsub.s32 q8, q8, q9
+0xb1,0x02,0x40,0xf2 = vqsub.s8 d16, d16, d17
+0xb1,0x02,0x50,0xf2 = vqsub.s16 d16, d16, d17
+0xb1,0x02,0x60,0xf2 = vqsub.s32 d16, d16, d17
+0xb1,0x02,0x70,0xf2 = vqsub.s64 d16, d16, d17
+0xb1,0x02,0x40,0xf3 = vqsub.u8 d16, d16, d17
+0xb1,0x02,0x50,0xf3 = vqsub.u16 d16, d16, d17
+0xb1,0x02,0x60,0xf3 = vqsub.u32 d16, d16, d17
+0xb1,0x02,0x70,0xf3 = vqsub.u64 d16, d16, d17
+0xf2,0x02,0x40,0xf2 = vqsub.s8 q8, q8, q9
+0xf2,0x02,0x50,0xf2 = vqsub.s16 q8, q8, q9
+0xf2,0x02,0x60,0xf2 = vqsub.s32 q8, q8, q9
+0xf2,0x02,0x70,0xf2 = vqsub.s64 q8, q8, q9
+0xf2,0x02,0x40,0xf3 = vqsub.u8 q8, q8, q9
+0xf2,0x02,0x50,0xf3 = vqsub.u16 q8, q8, q9
+0xf2,0x02,0x60,0xf3 = vqsub.u32 q8, q8, q9
+0xf2,0x02,0x70,0xf3 = vqsub.u64 q8, q8, q9
+0xa2,0x06,0xc0,0xf2 = vsubhn.i16 d16, q8, q9
+0xa2,0x06,0xd0,0xf2 = vsubhn.i32 d16, q8, q9
+0xa2,0x06,0xe0,0xf2 = vsubhn.i64 d16, q8, q9
+0xa2,0x06,0xc0,0xf3 = vrsubhn.i16 d16, q8, q9
+0xa2,0x06,0xd0,0xf3 = vrsubhn.i32 d16, q8, q9
+0xa2,0x06,0xe0,0xf3 = vrsubhn.i64 d16, q8, q9
+0x28,0xb2,0x0b,0xf2 = vhsub.s8 d11, d11, d24
+0x27,0xc2,0x1c,0xf2 = vhsub.s16 d12, d12, d23
+0x26,0xd2,0x2d,0xf2 = vhsub.s32 d13, d13, d22
+0x25,0xe2,0x0e,0xf3 = vhsub.u8 d14, d14, d21
+0x24,0xf2,0x1f,0xf3 = vhsub.u16 d15, d15, d20
+0xa3,0x02,0x60,0xf3 = vhsub.u32 d16, d16, d19
+0x68,0x22,0x02,0xf2 = vhsub.s8 q1, q1, q12
+0x66,0x42,0x14,0xf2 = vhsub.s16 q2, q2, q11
+0x64,0x62,0x26,0xf2 = vhsub.s32 q3, q3, q10
+0x62,0x82,0x08,0xf3 = vhsub.u8 q4, q4, q9
+0x60,0xa2,0x1a,0xf3 = vhsub.u16 q5, q5, q8
+0x4e,0xc2,0x2c,0xf3 = vhsub.u32 q6, q6, q7
+0x05,0xc3,0x8c,0xf2 = vsubw.s8 q6, q6, d5
+0x01,0xe3,0x9e,0xf2 = vsubw.s16 q7, q7, d1
+0x82,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d2
+0x05,0xc3,0x8c,0xf3 = vsubw.u8 q6, q6, d5
+0x01,0xe3,0x9e,0xf3 = vsubw.u16 q7, q7, d1
+0x82,0x03,0xe0,0xf3 = vsubw.u32 q8, q8, d2

data/test/MC/ARM/neon-table-encoding.s.cs ADDED

@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xa0,0x08,0xf1,0xf3 = vtbl.8 d16, {d17}, d16
+0xa2,0x09,0xf0,0xf3 = vtbl.8 d16, {d16, d17}, d18
+0xa4,0x0a,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18}, d20
+0xa4,0x0b,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18, d19}, d20
+0xe1,0x28,0xf0,0xf3 = vtbx.8 d18, {d16}, d17
+0xe2,0x39,0xf0,0xf3 = vtbx.8 d19, {d16, d17}, d18
+0xe5,0x4a,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18}, d21
+0xe5,0x4b,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18, d19}, d21

data/test/MC/ARM/neon-v8.s.cs ADDED

@@ -0,0 +1,38 @@
+# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
+0x11,0x4f,0x05,0xf3 = vmaxnm.f32 d4, d5, d1
+0x5c,0x4f,0x08,0xf3 = vmaxnm.f32 q2, q4, q6
+0x3e,0x5f,0x24,0xf3 = vminnm.f32 d5, d4, d30
+0xd4,0x0f,0x2a,0xf3 = vminnm.f32 q0, q13, q2
+0x06,0x40,0xbb,0xf3 = vcvta.s32.f32 d4, d6
+0x8a,0xc0,0xbb,0xf3 = vcvta.u32.f32 d12, d10
+0x4c,0x80,0xbb,0xf3 = vcvta.s32.f32 q4, q6
+0xe4,0x80,0xbb,0xf3 = vcvta.u32.f32 q4, q10
+0x2e,0x13,0xbb,0xf3 = vcvtm.s32.f32 d1, d30
+0x8a,0xc3,0xbb,0xf3 = vcvtm.u32.f32 d12, d10
+0x64,0x23,0xbb,0xf3 = vcvtm.s32.f32 q1, q10
+0xc2,0xa3,0xfb,0xf3 = vcvtm.u32.f32 q13, q1
+0x21,0xf1,0xbb,0xf3 = vcvtn.s32.f32 d15, d17
+0x83,0x51,0xbb,0xf3 = vcvtn.u32.f32 d5, d3
+0x60,0x61,0xbb,0xf3 = vcvtn.s32.f32 q3, q8
+0xc6,0xa1,0xbb,0xf3 = vcvtn.u32.f32 q5, q3
+0x25,0xb2,0xbb,0xf3 = vcvtp.s32.f32 d11, d21
+0xa7,0xe2,0xbb,0xf3 = vcvtp.u32.f32 d14, d23
+0x6e,0x82,0xbb,0xf3 = vcvtp.s32.f32 q4, q15
+0xe0,0x22,0xfb,0xf3 = vcvtp.u32.f32 q9, q8
+0x00,0x34,0xba,0xf3 = vrintn.f32 d3, d0
+0x48,0x24,0xba,0xf3 = vrintn.f32 q1, q4
+0x8c,0x54,0xba,0xf3 = vrintx.f32 d5, d12
+0xc6,0x04,0xba,0xf3 = vrintx.f32 q0, q3
+0x00,0x35,0xba,0xf3 = vrinta.f32 d3, d0
+0x44,0x05,0xfa,0xf3 = vrinta.f32 q8, q2
+0xa2,0xc5,0xba,0xf3 = vrintz.f32 d12, d18
+0xc8,0x25,0xfa,0xf3 = vrintz.f32 q9, q4
+0x80,0x36,0xba,0xf3 = vrintm.f32 d3, d0
+0xc8,0x26,0xba,0xf3 = vrintm.f32 q1, q4
+0x80,0x37,0xba,0xf3 = vrintp.f32 d3, d0
+0xc8,0x27,0xba,0xf3 = vrintp.f32 q1, q4
+0x00,0x34,0xba,0xf3 = vrintn.f32 d3, d0
+0xc6,0x04,0xba,0xf3 = vrintx.f32 q0, q3
+0x00,0x35,0xba,0xf3 = vrinta.f32 d3, d0
+0xc8,0x25,0xfa,0xf3 = vrintz.f32 q9, q4
+0xc8,0x27,0xba,0xf3 = vrintp.f32 q1, q4

data/test/MC/ARM/neon-vld-encoding.s.cs ADDED

@@ -0,0 +1,213 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x1f,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64]
+0x4f,0x07,0x60,0xf4 = vld1.16 {d16}, [r0]
+0x8f,0x07,0x60,0xf4 = vld1.32 {d16}, [r0]
+0xcf,0x07,0x60,0xf4 = vld1.64 {d16}, [r0]
+0x1f,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64]
+0x6f,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128]
+0x8f,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0]
+0xcf,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0]
+0x0f,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3]
+0x5f,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64]
+0x8f,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]
+0xdf,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64]
+0x0f,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3]
+0x5f,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]
+0x8f,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3]
+0xdf,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64]
+0x1d,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64]!
+0x4d,0x07,0x60,0xf4 = vld1.16 {d16}, [r0]!
+0x8d,0x07,0x60,0xf4 = vld1.32 {d16}, [r0]!
+0xcd,0x07,0x60,0xf4 = vld1.64 {d16}, [r0]!
+0x1d,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64]!
+0x6d,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128]!
+0x8d,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0]!
+0xcd,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0]!
+0x15,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64], r5
+0x45,0x07,0x60,0xf4 = vld1.16 {d16}, [r0], r5
+0x85,0x07,0x60,0xf4 = vld1.32 {d16}, [r0], r5
+0xc5,0x07,0x60,0xf4 = vld1.64 {d16}, [r0], r5
+0x15,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64], r5
+0x65,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128], r5
+0x85,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0], r5
+0xc5,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0], r5
+0x0d,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3]!
+0x5d,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64]!
+0x8d,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]!
+0xdd,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64]!
+0x06,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3], r6
+0x56,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64], r6
+0x86,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3], r6
+0xd6,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64], r6
+0x0d,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3]!
+0x5d,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]!
+0x8d,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3]!
+0xdd,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64]!
+0x08,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3], r8
+0x58,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64], r8
+0x88,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3], r8
+0xd8,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64], r8
+0x1f,0x08,0x60,0xf4 = vld2.8 {d16, d17}, [r0:64]
+0x6f,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128]
+0x8f,0x08,0x60,0xf4 = vld2.32 {d16, d17}, [r0]
+0x1f,0x03,0x60,0xf4 = vld2.8 {d16, d17, d18, d19}, [r0:64]
+0x6f,0x03,0x60,0xf4 = vld2.16 {d16, d17, d18, d19}, [r0:128]
+0xbf,0x03,0x60,0xf4 = vld2.32 {d16, d17, d18, d19}, [r0:256]
+0x1d,0x38,0x60,0xf4 = vld2.8 {d19, d20}, [r0:64]!
+0x6d,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128]!
+0x8d,0x48,0x60,0xf4 = vld2.32 {d20, d21}, [r0]!
+0x1d,0x43,0x20,0xf4 = vld2.8 {d4, d5, d6, d7}, [r0:64]!
+0x6d,0x13,0x20,0xf4 = vld2.16 {d1, d2, d3, d4}, [r0:128]!
+0xbd,0xe3,0x20,0xf4 = vld2.32 {d14, d15, d16, d17}, [r0:256]!
+0x16,0x38,0x60,0xf4 = vld2.8 {d19, d20}, [r0:64], r6
+0x66,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128], r6
+0x86,0x48,0x60,0xf4 = vld2.32 {d20, d21}, [r0], r6
+0x16,0x43,0x20,0xf4 = vld2.8 {d4, d5, d6, d7}, [r0:64], r6
+0x66,0x13,0x20,0xf4 = vld2.16 {d1, d2, d3, d4}, [r0:128], r6
+0xb6,0xe3,0x20,0xf4 = vld2.32 {d14, d15, d16, d17}, [r0:256], r6
+0x0f,0x04,0x61,0xf4 = vld3.8 {d16, d17, d18}, [r1]
+0x4f,0x64,0x22,0xf4 = vld3.16 {d6, d7, d8}, [r2]
+0x8f,0x14,0x23,0xf4 = vld3.32 {d1, d2, d3}, [r3]
+0x1f,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64]
+0x4f,0xb5,0x64,0xf4 = vld3.16 {d27, d29, d31}, [r4]
+0x8f,0x65,0x25,0xf4 = vld3.32 {d6, d8, d10}, [r5]
+0x01,0xc4,0x26,0xf4 = vld3.8 {d12, d13, d14}, [r6], r1
+0x42,0xb4,0x27,0xf4 = vld3.16 {d11, d12, d13}, [r7], r2
+0x83,0x24,0x28,0xf4 = vld3.32 {d2, d3, d4}, [r8], r3
+0x04,0x45,0x29,0xf4 = vld3.8 {d4, d6, d8}, [r9], r4
+0x44,0xe5,0x29,0xf4 = vld3.16 {d14, d16, d18}, [r9], r4
+0x85,0x05,0x6a,0xf4 = vld3.32 {d16, d18, d20}, [r10], r5
+0x0d,0x64,0x28,0xf4 = vld3.8 {d6, d7, d8}, [r8]!
+0x4d,0x94,0x27,0xf4 = vld3.16 {d9, d10, d11}, [r7]!
+0x8d,0x14,0x26,0xf4 = vld3.32 {d1, d2, d3}, [r6]!
+0x1d,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64]!
+0x4d,0x45,0x65,0xf4 = vld3.16 {d20, d22, d24}, [r5]!
+0x8d,0x55,0x24,0xf4 = vld3.32 {d5, d7, d9}, [r4]!
+0x1f,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64]
+0x6f,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2:128]
+0xbf,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:256]
+0x3f,0x11,0x65,0xf4 = vld4.8 {d17, d19, d21, d23}, [r5:256]
+0x4f,0x11,0x67,0xf4 = vld4.16 {d17, d19, d21, d23}, [r7]
+0x8f,0x01,0x68,0xf4 = vld4.32 {d16, d18, d20, d22}, [r8]
+0x1d,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64]!
+0x6d,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2:128]!
+0xbd,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:256]!
+0x3d,0x11,0x65,0xf4 = vld4.8 {d17, d19, d21, d23}, [r5:256]!
+0x4d,0x11,0x67,0xf4 = vld4.16 {d17, d19, d21, d23}, [r7]!
+0x8d,0x01,0x68,0xf4 = vld4.32 {d16, d18, d20, d22}, [r8]!
+0x18,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64], r8
+0x47,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2], r7
+0x95,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:64], r5
+0x32,0x01,0x64,0xf4 = vld4.8 {d16, d18, d20, d22}, [r4:256], r2
+0x43,0x01,0x66,0xf4 = vld4.16 {d16, d18, d20, d22}, [r6], r3
+0x84,0x11,0x69,0xf4 = vld4.32 {d17, d19, d21, d23}, [r9], r4
+0x0f,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1]
+0x0d,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1]!
+0x03,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1], r3
+0x2f,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1]
+0x2d,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1]!
+0x23,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1], r3
+0x6f,0x00,0xe0,0xf4 = vld1.8 {d16[3]}, [r0]
+0x9f,0x04,0xe0,0xf4 = vld1.16 {d16[2]}, [r0:16]
+0xbf,0x08,0xe0,0xf4 = vld1.32 {d16[1]}, [r0:32]
+0xcd,0xc0,0xa2,0xf4 = vld1.8 {d12[6]}, [r2]!
+0xc2,0xc0,0xa2,0xf4 = vld1.8 {d12[6]}, [r2], r2
+0xcd,0xc4,0xa2,0xf4 = vld1.16 {d12[3]}, [r2]!
+0x82,0xc4,0xa2,0xf4 = vld1.16 {d12[2]}, [r2], r2
+0x3f,0x01,0xe0,0xf4 = vld2.8 {d16[1], d17[1]}, [r0:16]
+0x5f,0x05,0xe0,0xf4 = vld2.16 {d16[1], d17[1]}, [r0:32]
+0x8f,0x09,0xe0,0xf4 = vld2.32 {d16[1], d17[1]}, [r0]
+0x6f,0x15,0xe0,0xf4 = vld2.16 {d17[1], d19[1]}, [r0]
+0x5f,0x19,0xe0,0xf4 = vld2.32 {d17[0], d19[0]}, [r0:64]
+0x5d,0x19,0xe0,0xf4 = vld2.32 {d17[0], d19[0]}, [r0:64]!
+0x83,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2], r3
+0x8d,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2]!
+0x8f,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2]
+0x8f,0x6d,0xe1,0xf4 = vld2.32 {d22[], d23[]}, [r1]
+0xaf,0x6d,0xe1,0xf4 = vld2.32 {d22[], d24[]}, [r1]
+0x8d,0xad,0xa3,0xf4 = vld2.32 {d10[], d11[]}, [r3]!
+0xad,0xed,0xa4,0xf4 = vld2.32 {d14[], d16[]}, [r4]!
+0x84,0x6d,0xe5,0xf4 = vld2.32 {d22[], d23[]}, [r5], r4
+0xa4,0x6d,0xe6,0xf4 = vld2.32 {d22[], d24[]}, [r6], r4
+0x2f,0x02,0xe1,0xf4 = vld3.8 {d16[1], d17[1], d18[1]}, [r1]
+0x4f,0x66,0xa2,0xf4 = vld3.16 {d6[1], d7[1], d8[1]}, [r2]
+0x8f,0x1a,0xa3,0xf4 = vld3.32 {d1[1], d2[1], d3[1]}, [r3]
+0xaf,0xb6,0xe4,0xf4 = vld3.16 {d27[2], d29[2], d31[2]}, [r4]
+0x4f,0x6a,0xa5,0xf4 = vld3.32 {d6[0], d8[0], d10[0]}, [r5]
+0x61,0xc2,0xa6,0xf4 = vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1
+0x82,0xb6,0xa7,0xf4 = vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2
+0x83,0x2a,0xa8,0xf4 = vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3
+0xa4,0xe6,0xa9,0xf4 = vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4
+0x45,0x0a,0xea,0xf4 = vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5
+0xcd,0x62,0xa8,0xf4 = vld3.8 {d6[6], d7[6], d8[6]}, [r8]!
+0x8d,0x96,0xa7,0xf4 = vld3.16 {d9[2], d10[2], d11[2]}, [r7]!
+0x8d,0x1a,0xa6,0xf4 = vld3.32 {d1[1], d2[1], d3[1]}, [r6]!
+0xad,0x46,0xe5,0xf4 = vld3.16 {d20[2], d21[2], d22[2]}, [r5]!
+0x4d,0x5a,0xa4,0xf4 = vld3.32 {d5[0], d7[0], d9[0]}, [r4]!
+0x0f,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1]
+0x4f,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2]
+0x8f,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3]
+0x2f,0x1e,0xe7,0xf4 = vld3.8 {d17[], d19[], d21[]}, [r7]
+0x6f,0x1e,0xe7,0xf4 = vld3.16 {d17[], d19[], d21[]}, [r7]
+0xaf,0x0e,0xe8,0xf4 = vld3.32 {d16[], d18[], d20[]}, [r8]
+0x0d,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1]!
+0x4d,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2]!
+0x8d,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3]!
+0x2d,0x1e,0xe7,0xf4 = vld3.8 {d17[], d18[], d19[]}, [r7]!
+0x6d,0x1e,0xe7,0xf4 = vld3.16 {d17[], d18[], d19[]}, [r7]!
+0xad,0x0e,0xe8,0xf4 = vld3.32 {d16[], d18[], d20[]}, [r8]!
+0x08,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1], r8
+0x47,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2], r7
+0x85,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3], r5
+0x23,0x0e,0xe6,0xf4 = vld3.8 {d16[], d18[], d20[]}, [r6], r3
+0x63,0x0e,0xe6,0xf4 = vld3.16 {d16[], d18[], d20[]}, [r6], r3
+0xa4,0x1e,0xe9,0xf4 = vld3.32 {d17[], d19[], d21[]}, [r9], r4
+0x2f,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]
+0x4f,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]
+0x8f,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]
+0x6f,0x17,0xe7,0xf4 = vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]
+0xcf,0x0b,0xe8,0xf4 = vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]
+0x3d,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
+0x5d,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!
+0xad,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!
+0x6d,0x17,0xe7,0xf4 = vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!
+0xcd,0x0b,0xe8,0xf4 = vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!
+0x38,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8
+0x47,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7
+0x95,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5
+0x63,0x07,0xe6,0xf4 = vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3
+0xc4,0x1b,0xe9,0xf4 = vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4
+0x0f,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1]
+0x4f,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2]
+0x8f,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3]
+0x2f,0x1f,0xe7,0xf4 = vld4.8 {d17[], d19[], d21[], d23[]}, [r7]
+0x6f,0x1f,0xe7,0xf4 = vld4.16 {d17[], d19[], d21[], d23[]}, [r7]
+0xaf,0x0f,0xe8,0xf4 = vld4.32 {d16[], d18[], d20[], d22[]}, [r8]
+0x0d,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1]!
+0x4d,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!
+0x8d,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3]!
+0x2d,0x1f,0xe7,0xf4 = vld4.8 {d17[], d18[], d19[], d20[]}, [r7]!
+0x6d,0x1f,0xe7,0xf4 = vld4.16 {d17[], d18[], d19[], d20[]}, [r7]!
+0xad,0x0f,0xe8,0xf4 = vld4.32 {d16[], d18[], d20[], d22[]}, [r8]!
+0x08,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8
+0x47,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7
+0x85,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5
+0x23,0x0f,0xe6,0xf4 = vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3
+0x63,0x0f,0xe6,0xf4 = vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3
+0xa4,0x1f,0xe9,0xf4 = vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4
+0x0f,0x6a,0x29,0xf4 = vld1.8 {d6, d7}, [r9]
+0x0f,0x62,0x29,0xf4 = vld1.8 {d6, d7, d8, d9}, [r9]
+0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2]
+0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2]
+0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2]
+0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2]
+0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2]
+0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2]
+0x8f,0x4a,0x22,0xf4 = vld1.32 {d4, d5}, [r2]
+0x0f,0x26,0x22,0xf4 = vld1.8 {d2, d3, d4}, [r2]
+0x8f,0x26,0x22,0xf4 = vld1.32 {d2, d3, d4}, [r2]
+0xcf,0x26,0x22,0xf4 = vld1.64 {d2, d3, d4}, [r2]
+0xed,0x22,0x22,0xf4 = vld1.64 {d2, d3, d4, d5}, [r2:128]!
+0xed,0x22,0x22,0xf4 = vld1.64 {d2, d3, d4, d5}, [r2:128]!
+0x1f,0x08,0x60,0xf4 = vld2.8 {d16, d17}, [r0:64]
+0x6f,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128]

data/test/MC/ARM/neon-vst-encoding.s.cs ADDED

@@ -0,0 +1,120 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x1f,0x07,0x40,0xf4 = vst1.8 {d16}, [r0:64]
+0x4f,0x07,0x40,0xf4 = vst1.16 {d16}, [r0]
+0x8f,0x07,0x40,0xf4 = vst1.32 {d16}, [r0]
+0xcf,0x07,0x40,0xf4 = vst1.64 {d16}, [r0]
+0x1f,0x0a,0x40,0xf4 = vst1.8 {d16, d17}, [r0:64]
+0x6f,0x0a,0x40,0xf4 = vst1.16 {d16, d17}, [r0:128]
+0x8f,0x0a,0x40,0xf4 = vst1.32 {d16, d17}, [r0]
+0xcf,0x0a,0x40,0xf4 = vst1.64 {d16, d17}, [r0]
+0x1f,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0:64]
+0x1d,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0:64]!
+0x03,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0], r3
+0x1f,0x02,0x40,0xf4 = vst1.8 {d16, d17, d18, d19}, [r0:64]
+0x5d,0x02,0x41,0xf4 = vst1.16 {d16, d17, d18, d19}, [r1:64]!
+0xc2,0x02,0x43,0xf4 = vst1.64 {d16, d17, d18, d19}, [r3], r2
+0x1f,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64]
+0x6f,0x08,0x40,0xf4 = vst2.16 {d16, d17}, [r0:128]
+0x8f,0x08,0x40,0xf4 = vst2.32 {d16, d17}, [r0]
+0x1f,0x03,0x40,0xf4 = vst2.8 {d16, d17, d18, d19}, [r0:64]
+0x6f,0x03,0x40,0xf4 = vst2.16 {d16, d17, d18, d19}, [r0:128]
+0xbf,0x03,0x40,0xf4 = vst2.32 {d16, d17, d18, d19}, [r0:256]
+0x1d,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64]!
+0x6d,0xe8,0x40,0xf4 = vst2.16 {d30, d31}, [r0:128]!
+0x8d,0xe8,0x00,0xf4 = vst2.32 {d14, d15}, [r0]!
+0x1d,0x03,0x40,0xf4 = vst2.8 {d16, d17, d18, d19}, [r0:64]!
+0x6d,0x23,0x40,0xf4 = vst2.16 {d18, d19, d20, d21}, [r0:128]!
+0xbd,0x83,0x00,0xf4 = vst2.32 {d8, d9, d10, d11}, [r0:256]!
+0x0f,0x04,0x41,0xf4 = vst3.8 {d16, d17, d18}, [r1]
+0x4f,0x64,0x02,0xf4 = vst3.16 {d6, d7, d8}, [r2]
+0x8f,0x14,0x03,0xf4 = vst3.32 {d1, d2, d3}, [r3]
+0x1f,0x05,0x40,0xf4 = vst3.8 {d16, d18, d20}, [r0:64]
+0x4f,0xb5,0x44,0xf4 = vst3.16 {d27, d29, d31}, [r4]
+0x8f,0x65,0x05,0xf4 = vst3.32 {d6, d8, d10}, [r5]
+0x01,0xc4,0x06,0xf4 = vst3.8 {d12, d13, d14}, [r6], r1
+0x42,0xb4,0x07,0xf4 = vst3.16 {d11, d12, d13}, [r7], r2
+0x83,0x24,0x08,0xf4 = vst3.32 {d2, d3, d4}, [r8], r3
+0x04,0x45,0x09,0xf4 = vst3.8 {d4, d6, d8}, [r9], r4
+0x44,0xe5,0x09,0xf4 = vst3.16 {d14, d16, d18}, [r9], r4
+0x85,0x05,0x4a,0xf4 = vst3.32 {d16, d18, d20}, [r10], r5
+0x0d,0x64,0x08,0xf4 = vst3.8 {d6, d7, d8}, [r8]!
+0x4d,0x94,0x07,0xf4 = vst3.16 {d9, d10, d11}, [r7]!
+0x8d,0x14,0x06,0xf4 = vst3.32 {d1, d2, d3}, [r6]!
+0x1d,0x05,0x40,0xf4 = vst3.8 {d16, d18, d20}, [r0:64]!
+0x4d,0x45,0x45,0xf4 = vst3.16 {d20, d22, d24}, [r5]!
+0x8d,0x55,0x04,0xf4 = vst3.32 {d5, d7, d9}, [r4]!
+0x1f,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64]
+0x6f,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2:128]
+0xbf,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:256]
+0x3f,0x11,0x45,0xf4 = vst4.8 {d17, d19, d21, d23}, [r5:256]
+0x4f,0x11,0x47,0xf4 = vst4.16 {d17, d19, d21, d23}, [r7]
+0x8f,0x01,0x48,0xf4 = vst4.32 {d16, d18, d20, d22}, [r8]
+0x1d,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64]!
+0x6d,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2:128]!
+0xbd,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:256]!
+0x3d,0x11,0x45,0xf4 = vst4.8 {d17, d19, d21, d23}, [r5:256]!
+0x4d,0x11,0x47,0xf4 = vst4.16 {d17, d19, d21, d23}, [r7]!
+0x8d,0x01,0x48,0xf4 = vst4.32 {d16, d18, d20, d22}, [r8]!
+0x18,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64], r8
+0x47,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2], r7
+0x95,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:64], r5
+0x32,0x01,0x44,0xf4 = vst4.8 {d16, d18, d20, d22}, [r4:256], r2
+0x43,0x01,0x46,0xf4 = vst4.16 {d16, d18, d20, d22}, [r6], r3
+0x84,0x11,0x49,0xf4 = vst4.32 {d17, d19, d21, d23}, [r9], r4
+0x3f,0x01,0xc0,0xf4 = vst2.8 {d16[1], d17[1]}, [r0:16]
+0x5f,0x05,0xc0,0xf4 = vst2.16 {d16[1], d17[1]}, [r0:32]
+0x8f,0x09,0xc0,0xf4 = vst2.32 {d16[1], d17[1]}, [r0]
+0x6f,0x15,0xc0,0xf4 = vst2.16 {d17[1], d19[1]}, [r0]
+0x5f,0x19,0xc0,0xf4 = vst2.32 {d17[0], d19[0]}, [r0:64]
+0x83,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2], r3
+0x8d,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2]!
+0x8f,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2]
+0x6f,0x15,0xc0,0xf4 = vst2.16 {d17[1], d19[1]}, [r0]
+0x5f,0x19,0xc0,0xf4 = vst2.32 {d17[0], d19[0]}, [r0:64]
+0x6d,0x75,0x81,0xf4 = vst2.16 {d7[1], d9[1]}, [r1]!
+0x5d,0x69,0x82,0xf4 = vst2.32 {d6[0], d8[0]}, [r2:64]!
+0x65,0x25,0x83,0xf4 = vst2.16 {d2[1], d4[1]}, [r3], r5
+0x57,0x59,0x84,0xf4 = vst2.32 {d5[0], d7[0]}, [r4:64], r7
+0x2f,0x02,0xc1,0xf4 = vst3.8 {d16[1], d17[1], d18[1]}, [r1]
+0x4f,0x66,0x82,0xf4 = vst3.16 {d6[1], d7[1], d8[1]}, [r2]
+0x8f,0x1a,0x83,0xf4 = vst3.32 {d1[1], d2[1], d3[1]}, [r3]
+0x6f,0xb6,0xc4,0xf4 = vst3.16 {d27[1], d29[1], d31[1]}, [r4]
+0xcf,0x6a,0x85,0xf4 = vst3.32 {d6[1], d8[1], d10[1]}, [r5]
+0x21,0xc2,0x86,0xf4 = vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1
+0x42,0xb6,0x87,0xf4 = vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2
+0x83,0x2a,0x88,0xf4 = vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3
+0x64,0xe6,0x89,0xf4 = vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4
+0xc5,0x0a,0xca,0xf4 = vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5
+0x2d,0x62,0x88,0xf4 = vst3.8 {d6[1], d7[1], d8[1]}, [r8]!
+0x4d,0x96,0x87,0xf4 = vst3.16 {d9[1], d10[1], d11[1]}, [r7]!
+0x8d,0x1a,0x86,0xf4 = vst3.32 {d1[1], d2[1], d3[1]}, [r6]!
+0x6d,0x46,0xc5,0xf4 = vst3.16 {d20[1], d21[1], d22[1]}, [r5]!
+0xcd,0x5a,0x84,0xf4 = vst3.32 {d5[1], d7[1], d9[1]}, [r4]!
+0x2f,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]
+0x4f,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]
+0x8f,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]
+0x6f,0x17,0xc7,0xf4 = vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]
+0xcf,0x0b,0xc8,0xf4 = vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]
+0x3d,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
+0x5d,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!
+0xad,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!
+0x6d,0x17,0xc7,0xf4 = vst4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!
+0xcd,0x0b,0xc8,0xf4 = vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!
+0x38,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8
+0x47,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7
+0x95,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5
+0x63,0x07,0xc6,0xf4 = vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3
+0xc4,0x1b,0xc9,0xf4 = vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4
+0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2]
+0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2]
+0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2]
+0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2]
+0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2]
+0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2]
+0x8f,0x4a,0x02,0xf4 = vst1.32 {d4, d5}, [r2]
+0x0f,0x89,0x04,0xf4 = vst2.8 {d8, d10}, [r4]
+0xbf,0x98,0x83,0xf4 = vst1.32 {d9[1]}, [r3:32]
+0xbd,0xb8,0xc9,0xf4 = vst1.32 {d27[1]}, [r9:32]!
+0xb5,0xb8,0xc3,0xf4 = vst1.32 {d27[1]}, [r3:32], r5
+0x1f,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64]
+0x6f,0x08,0x40,0xf4 = vst2.16 {d16, d17}, [r0:128]