crabstone 3.0.3
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- checksums.yaml +7 -0
- data/CHANGES.md +61 -0
- data/LICENSE +25 -0
- data/MANIFEST +312 -0
- data/README.md +103 -0
- data/Rakefile +27 -0
- data/bin/genconst +66 -0
- data/bin/genreg +99 -0
- data/crabstone.gemspec +27 -0
- data/examples/hello_world.rb +43 -0
- data/lib/arch/arm.rb +128 -0
- data/lib/arch/arm64.rb +167 -0
- data/lib/arch/arm64_const.rb +1055 -0
- data/lib/arch/arm64_registers.rb +295 -0
- data/lib/arch/arm_const.rb +777 -0
- data/lib/arch/arm_registers.rb +149 -0
- data/lib/arch/mips.rb +78 -0
- data/lib/arch/mips_const.rb +850 -0
- data/lib/arch/mips_registers.rb +208 -0
- data/lib/arch/ppc.rb +90 -0
- data/lib/arch/ppc_const.rb +1181 -0
- data/lib/arch/ppc_registers.rb +209 -0
- data/lib/arch/sparc.rb +79 -0
- data/lib/arch/sparc_const.rb +461 -0
- data/lib/arch/sparc_registers.rb +121 -0
- data/lib/arch/systemz.rb +79 -0
- data/lib/arch/sysz_const.rb +779 -0
- data/lib/arch/sysz_registers.rb +66 -0
- data/lib/arch/x86.rb +107 -0
- data/lib/arch/x86_const.rb +1698 -0
- data/lib/arch/x86_registers.rb +265 -0
- data/lib/arch/xcore.rb +78 -0
- data/lib/arch/xcore_const.rb +185 -0
- data/lib/arch/xcore_registers.rb +57 -0
- data/lib/crabstone.rb +564 -0
- data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
- data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
- data/test/MC/AArch64/neon-2velem.s.cs +113 -0
- data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
- data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
- data/test/MC/AArch64/neon-across.s.cs +40 -0
- data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
- data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
- data/test/MC/AArch64/neon-crypto.s.cs +15 -0
- data/test/MC/AArch64/neon-extract.s.cs +3 -0
- data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
- data/test/MC/AArch64/neon-max-min.s.cs +37 -0
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
- data/test/MC/AArch64/neon-mov.s.cs +74 -0
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
- data/test/MC/AArch64/neon-perm.s.cs +43 -0
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
- data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
- data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
- data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
- data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
- data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
- data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
- data/test/MC/AArch64/neon-shift.s.cs +22 -0
- data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
- data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
- data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
- data/test/MC/AArch64/neon-tbl.s.cs +21 -0
- data/test/MC/AArch64/trace-regs.s.cs +383 -0
- data/test/MC/ARM/arm-aliases.s.cs +7 -0
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
- data/test/MC/ARM/arm-it-block.s.cs +2 -0
- data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
- data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
- data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
- data/test/MC/ARM/arm_instructions.s.cs +25 -0
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
- data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
- data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
- data/test/MC/ARM/crc32-thumb.s.cs +7 -0
- data/test/MC/ARM/crc32.s.cs +7 -0
- data/test/MC/ARM/dot-req.s.cs +3 -0
- data/test/MC/ARM/fp-armv8.s.cs +52 -0
- data/test/MC/ARM/idiv-thumb.s.cs +3 -0
- data/test/MC/ARM/idiv.s.cs +3 -0
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
- data/test/MC/ARM/mode-switch.s.cs +7 -0
- data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
- data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
- data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
- data/test/MC/ARM/neon-crypto.s.cs +16 -0
- data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
- data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
- data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
- data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neon-v8.s.cs +38 -0
- data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
- data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
- data/test/MC/ARM/neon-vswp.s.cs +3 -0
- data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
- data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
- data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
- data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
- data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
- data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
- data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
- data/test/MC/ARM/thumb-hints.s.cs +12 -0
- data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
- data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
- data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
- data/test/MC/ARM/thumb.s.cs +19 -0
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
- data/test/MC/ARM/thumb2-branches.s.cs +85 -0
- data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
- data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
- data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
- data/test/MC/ARM/vfp4.s.cs +13 -0
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
- data/test/MC/ARM/vpush-vpop.s.cs +9 -0
- data/test/MC/Mips/hilo-addressing.s.cs +4 -0
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
- data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
- data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
- data/test/MC/Mips/micromips-expansions.s.cs +20 -0
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
- data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
- data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
- data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
- data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
- data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
- data/test/MC/Mips/mips-expansions.s.cs +20 -0
- data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
- data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
- data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
- data/test/MC/Mips/mips-register-names.s.cs +33 -0
- data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
- data/test/MC/Mips/mips64-instructions.s.cs +3 -0
- data/test/MC/Mips/mips64-register-names.s.cs +33 -0
- data/test/MC/Mips/mips_directives.s.cs +12 -0
- data/test/MC/Mips/nabi-regs.s.cs +12 -0
- data/test/MC/Mips/set-at-directive.s.cs +6 -0
- data/test/MC/Mips/test_2r.s.cs +16 -0
- data/test/MC/Mips/test_2rf.s.cs +33 -0
- data/test/MC/Mips/test_3r.s.cs +243 -0
- data/test/MC/Mips/test_3rf.s.cs +83 -0
- data/test/MC/Mips/test_bit.s.cs +49 -0
- data/test/MC/Mips/test_cbranch.s.cs +11 -0
- data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
- data/test/MC/Mips/test_elm.s.cs +16 -0
- data/test/MC/Mips/test_elm_insert.s.cs +4 -0
- data/test/MC/Mips/test_elm_insve.s.cs +5 -0
- data/test/MC/Mips/test_i10.s.cs +5 -0
- data/test/MC/Mips/test_i5.s.cs +45 -0
- data/test/MC/Mips/test_i8.s.cs +11 -0
- data/test/MC/Mips/test_lsa.s.cs +5 -0
- data/test/MC/Mips/test_mi10.s.cs +24 -0
- data/test/MC/Mips/test_vec.s.cs +8 -0
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
- data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
- data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
- data/test/MC/README +6 -0
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
- data/test/MC/Sparc/sparc-vis.s.cs +2 -0
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
- data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
- data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
- data/test/MC/SystemZ/insn-good.s.cs +2265 -0
- data/test/MC/SystemZ/regs-good.s.cs +45 -0
- data/test/MC/X86/3DNow.s.cs +29 -0
- data/test/MC/X86/address-size.s.cs +5 -0
- data/test/MC/X86/avx512-encodings.s.cs +12 -0
- data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
- data/test/MC/X86/x86-32-avx.s.cs +833 -0
- data/test/MC/X86/x86-32-fma3.s.cs +169 -0
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
- data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
- data/test/MC/X86/x86_64-encoding.s.cs +59 -0
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
- data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
- data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
- data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
- data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
- data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
- data/test/README +6 -0
- data/test/test.rb +205 -0
- data/test/test.rb.SPEC +235 -0
- data/test/test_arm.rb +202 -0
- data/test/test_arm.rb.SPEC +275 -0
- data/test/test_arm64.rb +150 -0
- data/test/test_arm64.rb.SPEC +116 -0
- data/test/test_detail.rb +228 -0
- data/test/test_detail.rb.SPEC +322 -0
- data/test/test_exhaustive.rb +80 -0
- data/test/test_mips.rb +118 -0
- data/test/test_mips.rb.SPEC +91 -0
- data/test/test_ppc.rb +137 -0
- data/test/test_ppc.rb.SPEC +84 -0
- data/test/test_sanity.rb +83 -0
- data/test/test_skipdata.rb +111 -0
- data/test/test_skipdata.rb.SPEC +58 -0
- data/test/test_sparc.rb +113 -0
- data/test/test_sparc.rb.SPEC +116 -0
- data/test/test_sysz.rb +111 -0
- data/test/test_sysz.rb.SPEC +61 -0
- data/test/test_x86.rb +189 -0
- data/test/test_x86.rb.SPEC +579 -0
- data/test/test_xcore.rb +100 -0
- data/test/test_xcore.rb.SPEC +75 -0
- metadata +393 -0
@@ -0,0 +1,91 @@
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****************
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Platform: MIPS-32 (Big-endian)
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Code:0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56
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Disasm:
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0x1000: jal 0x40025c
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op_count: 1
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operands[0].type: IMM = 0x40025c
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0x1004: nop
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0x1008: addiu $v0, $zero, 0xc
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op_count: 3
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operands[0].type: REG = v0
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operands[1].type: REG = zero
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operands[2].type: IMM = 0xc
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0x100c: lw $v0, ($sp)
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op_count: 2
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operands[0].type: REG = v0
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operands[1].type: MEM
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operands[1].mem.base: REG = sp
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0x1010: ori $at, $at, 0x3456
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op_count: 3
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|
+
operands[0].type: REG = at
|
26
|
+
operands[1].type: REG = at
|
27
|
+
operands[2].type: IMM = 0x3456
|
28
|
+
|
29
|
+
0x1014:
|
30
|
+
|
31
|
+
****************
|
32
|
+
Platform: MIPS-64-EL (Little-endian)
|
33
|
+
Code:0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00
|
34
|
+
Disasm:
|
35
|
+
0x1000: ori $at, $at, 0x3456
|
36
|
+
op_count: 3
|
37
|
+
operands[0].type: REG = at
|
38
|
+
operands[1].type: REG = at
|
39
|
+
operands[2].type: IMM = 0x3456
|
40
|
+
|
41
|
+
0x1004: srl $v0, $at, 0x1f
|
42
|
+
op_count: 3
|
43
|
+
operands[0].type: REG = v0
|
44
|
+
operands[1].type: REG = at
|
45
|
+
operands[2].type: IMM = 0x1f
|
46
|
+
|
47
|
+
0x1008:
|
48
|
+
|
49
|
+
****************
|
50
|
+
Platform: MIPS-32R6 | Micro (Big-endian)
|
51
|
+
Code:0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0
|
52
|
+
Disasm:
|
53
|
+
0x1000: break 7, 0
|
54
|
+
op_count: 2
|
55
|
+
operands[0].type: IMM = 0x7
|
56
|
+
operands[1].type: IMM = 0x0
|
57
|
+
|
58
|
+
0x1004: wait 0x11
|
59
|
+
op_count: 1
|
60
|
+
operands[0].type: IMM = 0x11
|
61
|
+
|
62
|
+
0x1008: syscall 0x18c
|
63
|
+
op_count: 1
|
64
|
+
operands[0].type: IMM = 0x18c
|
65
|
+
|
66
|
+
0x100c: rotrv $t1, $a2, $a3
|
67
|
+
op_count: 3
|
68
|
+
operands[0].type: REG = t1
|
69
|
+
operands[1].type: REG = a2
|
70
|
+
operands[2].type: REG = a3
|
71
|
+
|
72
|
+
0x1010:
|
73
|
+
|
74
|
+
****************
|
75
|
+
Platform: MIPS-32R6 (Big-endian)
|
76
|
+
Code:0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0
|
77
|
+
Disasm:
|
78
|
+
0x1000: addiupc $a0, 0x64
|
79
|
+
op_count: 2
|
80
|
+
operands[0].type: REG = a0
|
81
|
+
operands[1].type: IMM = 0x64
|
82
|
+
|
83
|
+
0x1004: align $a0, $v0, $v1, 2
|
84
|
+
op_count: 4
|
85
|
+
operands[0].type: REG = a0
|
86
|
+
operands[1].type: REG = v0
|
87
|
+
operands[2].type: REG = v1
|
88
|
+
operands[3].type: IMM = 0x2
|
89
|
+
|
90
|
+
0x1008:
|
91
|
+
|
data/test/test_ppc.rb
ADDED
@@ -0,0 +1,137 @@
|
|
1
|
+
#!/usr/bin/env ruby
|
2
|
+
|
3
|
+
# Library by Nguyen Anh Quynh
|
4
|
+
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
5
|
+
# Additional binding work by Ben Nagy
|
6
|
+
# (c) 2013 COSEINC. All Rights Reserved.
|
7
|
+
|
8
|
+
require 'crabstone'
|
9
|
+
require 'stringio'
|
10
|
+
|
11
|
+
module TestPPC
|
12
|
+
|
13
|
+
PPC_CODE = "\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
|
14
|
+
include Crabstone
|
15
|
+
include Crabstone::PPC
|
16
|
+
|
17
|
+
@platforms = [
|
18
|
+
Hash[
|
19
|
+
'arch' => ARCH_PPC,
|
20
|
+
'mode' => MODE_BIG_ENDIAN,
|
21
|
+
'code' => PPC_CODE,
|
22
|
+
'comment' => "PPC-64"
|
23
|
+
]
|
24
|
+
]
|
25
|
+
|
26
|
+
def self.uint32 i
|
27
|
+
Integer(i) & 0xffffffff
|
28
|
+
end
|
29
|
+
|
30
|
+
def self.bc_name bc
|
31
|
+
case bc
|
32
|
+
when BC_INVALID
|
33
|
+
"invalid"
|
34
|
+
when BC_LT
|
35
|
+
"lt"
|
36
|
+
when BC_LE
|
37
|
+
"le"
|
38
|
+
when BC_EQ
|
39
|
+
"eq"
|
40
|
+
when BC_GE
|
41
|
+
"ge"
|
42
|
+
when BC_GT
|
43
|
+
"gt"
|
44
|
+
when BC_NE
|
45
|
+
"ne"
|
46
|
+
when BC_UN
|
47
|
+
"un"
|
48
|
+
when BC_NU
|
49
|
+
"nu"
|
50
|
+
when BC_SO
|
51
|
+
"so"
|
52
|
+
when BC_NS
|
53
|
+
"ns"
|
54
|
+
end
|
55
|
+
end
|
56
|
+
|
57
|
+
def self.print_detail cs, insn, sio
|
58
|
+
if insn.op_count > 0
|
59
|
+
if insn.writes_reg? :ra
|
60
|
+
print "[w:ra] "
|
61
|
+
end
|
62
|
+
sio.puts "\top_count: #{insn.op_count}"
|
63
|
+
insn.operands.each_with_index do |op,idx|
|
64
|
+
case op[:type]
|
65
|
+
when OP_REG
|
66
|
+
sio.puts "\t\toperands[#{idx}].type: REG = #{cs.reg_name(op.value)}"
|
67
|
+
when OP_IMM
|
68
|
+
sio.puts "\t\toperands[#{idx}].type: IMM = 0x#{self.uint32(op.value).to_s(16)}"
|
69
|
+
when OP_MEM
|
70
|
+
sio.puts "\t\toperands[#{idx}].type: MEM"
|
71
|
+
if op.value[:base].nonzero?
|
72
|
+
sio.puts "\t\t\toperands[#{idx}].mem.base: REG = %s" % cs.reg_name(op.value[:base])
|
73
|
+
end
|
74
|
+
if op.value[:disp].nonzero?
|
75
|
+
sio.puts "\t\t\toperands[#{idx}].mem.disp: 0x%x" % (self.uint32(op.value[:disp]))
|
76
|
+
end
|
77
|
+
when OP_CRX
|
78
|
+
sio.puts "\t\toperands[#{idx}].type: CRX\n"
|
79
|
+
sio.puts "\t\t\toperands[#{idx}].crx.scale: #{op.value[:scale]}"
|
80
|
+
sio.puts "\t\t\toperands[#{idx}].crx.reg: %s" % (cs.reg_name(op.value[:reg]))
|
81
|
+
sio.puts "\t\t\toperands[#{idx}].crx.cond: %s" % (self.bc_name(op.value[:cond]))
|
82
|
+
end
|
83
|
+
end
|
84
|
+
end
|
85
|
+
if insn.bc.nonzero?
|
86
|
+
sio.puts("\tBranch code: %u" % insn.bc)
|
87
|
+
end
|
88
|
+
if insn.bh.nonzero?
|
89
|
+
sio.puts("\tBranch hint: %u" % insn.bh)
|
90
|
+
end
|
91
|
+
if insn.update_cr0
|
92
|
+
sio.puts("\tUpdate-CR0: True")
|
93
|
+
end
|
94
|
+
sio.puts
|
95
|
+
end
|
96
|
+
|
97
|
+
ours = StringIO.new
|
98
|
+
|
99
|
+
begin
|
100
|
+
cs = Disassembler.new(0,0)
|
101
|
+
print "PPC Test: Capstone v #{cs.version.join('.')} - "
|
102
|
+
ensure
|
103
|
+
cs.close
|
104
|
+
end
|
105
|
+
|
106
|
+
#Test through all modes and architectures
|
107
|
+
@platforms.each do |p|
|
108
|
+
ours.puts "****************"
|
109
|
+
ours.puts "Platform: #{p['comment']}"
|
110
|
+
ours.puts "Code:#{p['code'].bytes.map {|b| "0x%.2x" % b}.join(' ')} "
|
111
|
+
ours.puts "Disasm:"
|
112
|
+
|
113
|
+
cs = Disassembler.new(p['arch'], p['mode'])
|
114
|
+
cs.decomposer = true
|
115
|
+
cache = nil
|
116
|
+
|
117
|
+
cs.disasm(p['code'], 0x1000).each {|insn|
|
118
|
+
ours.puts "0x#{insn.address.to_s(16)}:\t#{insn.mnemonic}\t#{insn.op_str}"
|
119
|
+
self.print_detail(cs, insn, ours)
|
120
|
+
cache = insn.address + insn.size
|
121
|
+
}
|
122
|
+
|
123
|
+
ours.printf("0x%x:\n", cache)
|
124
|
+
ours.puts
|
125
|
+
cs.close
|
126
|
+
end
|
127
|
+
|
128
|
+
ours.rewind
|
129
|
+
theirs = File.binread(__FILE__ + ".SPEC")
|
130
|
+
if ours.read == theirs
|
131
|
+
puts "#{__FILE__}: PASS"
|
132
|
+
else
|
133
|
+
ours.rewind
|
134
|
+
puts ours.read
|
135
|
+
puts "#{__FILE__}: FAIL"
|
136
|
+
end
|
137
|
+
end
|
@@ -0,0 +1,84 @@
|
|
1
|
+
****************
|
2
|
+
Platform: PPC-64
|
3
|
+
Code:0x43 0x20 0x0c 0x07 0x41 0x56 0xff 0x17 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14
|
4
|
+
Disasm:
|
5
|
+
0x1000: bdnzla+ 0xc04
|
6
|
+
op_count: 1
|
7
|
+
operands[0].type: IMM = 0xc04
|
8
|
+
Branch hint: 1
|
9
|
+
|
10
|
+
0x1004: bdztla 4*cr5+eq, 0xffffff14
|
11
|
+
op_count: 2
|
12
|
+
operands[0].type: CRX
|
13
|
+
operands[0].crx.scale: 4
|
14
|
+
operands[0].crx.reg: cr5
|
15
|
+
operands[0].crx.cond: eq
|
16
|
+
operands[1].type: IMM = 0xffffff14
|
17
|
+
Branch hint: 1
|
18
|
+
|
19
|
+
0x1008: lwz r1, (0)
|
20
|
+
op_count: 2
|
21
|
+
operands[0].type: REG = r1
|
22
|
+
operands[1].type: MEM
|
23
|
+
operands[1].mem.base: REG = r0
|
24
|
+
|
25
|
+
0x100c: lwz r1, (r31)
|
26
|
+
op_count: 2
|
27
|
+
operands[0].type: REG = r1
|
28
|
+
operands[1].type: MEM
|
29
|
+
operands[1].mem.base: REG = r31
|
30
|
+
|
31
|
+
0x1010: vpkpx v2, v3, v4
|
32
|
+
op_count: 3
|
33
|
+
operands[0].type: REG = v2
|
34
|
+
operands[1].type: REG = v3
|
35
|
+
operands[2].type: REG = v4
|
36
|
+
|
37
|
+
0x1014: stfs f2, 0x80(r4)
|
38
|
+
op_count: 2
|
39
|
+
operands[0].type: REG = f2
|
40
|
+
operands[1].type: MEM
|
41
|
+
operands[1].mem.base: REG = r4
|
42
|
+
operands[1].mem.disp: 0x80
|
43
|
+
|
44
|
+
0x1018: crand 2, 3, 4
|
45
|
+
op_count: 3
|
46
|
+
operands[0].type: REG = r2
|
47
|
+
operands[1].type: REG = r3
|
48
|
+
operands[2].type: REG = r4
|
49
|
+
|
50
|
+
0x101c: cmpwi cr2, r3, 0x80
|
51
|
+
op_count: 3
|
52
|
+
operands[0].type: REG = cr2
|
53
|
+
operands[1].type: REG = r3
|
54
|
+
operands[2].type: IMM = 0x80
|
55
|
+
|
56
|
+
0x1020: addc r2, r3, r4
|
57
|
+
op_count: 3
|
58
|
+
operands[0].type: REG = r2
|
59
|
+
operands[1].type: REG = r3
|
60
|
+
operands[2].type: REG = r4
|
61
|
+
|
62
|
+
0x1024: mulhd. r2, r3, r4
|
63
|
+
op_count: 3
|
64
|
+
operands[0].type: REG = r2
|
65
|
+
operands[1].type: REG = r3
|
66
|
+
operands[2].type: REG = r4
|
67
|
+
Update-CR0: True
|
68
|
+
|
69
|
+
0x1028: bdnzlrl+
|
70
|
+
Branch hint: 1
|
71
|
+
|
72
|
+
0x102c: bgelrl- cr2
|
73
|
+
op_count: 1
|
74
|
+
operands[0].type: REG = cr2
|
75
|
+
Branch code: 4
|
76
|
+
Branch hint: 2
|
77
|
+
|
78
|
+
0x1030: bne 0x1044
|
79
|
+
op_count: 1
|
80
|
+
operands[0].type: IMM = 0x1044
|
81
|
+
Branch code: 68
|
82
|
+
|
83
|
+
0x1034:
|
84
|
+
|
data/test/test_sanity.rb
ADDED
@@ -0,0 +1,83 @@
|
|
1
|
+
#!/usr/bin/env ruby
|
2
|
+
|
3
|
+
# Library by Nguyen Anh Quynh
|
4
|
+
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
5
|
+
# Additional binding work by Ben Nagy
|
6
|
+
# (c) 2013 COSEINC. All Rights Reserved.
|
7
|
+
|
8
|
+
require 'crabstone'
|
9
|
+
require 'stringio'
|
10
|
+
|
11
|
+
module Test
|
12
|
+
|
13
|
+
include Crabstone
|
14
|
+
|
15
|
+
# These need to be maintained by hand, but I actually just copy them over
|
16
|
+
# from the Go binding. It's just a very quick check to catch developer
|
17
|
+
# error.
|
18
|
+
# TODO: Work out why I can't get the C constants with ffi/tools/const_generator
|
19
|
+
|
20
|
+
@checks = {
|
21
|
+
Crabstone::ARM64 => Hash[
|
22
|
+
reg_max: 260,
|
23
|
+
ins_max: 452,
|
24
|
+
grp_max: 132
|
25
|
+
],
|
26
|
+
Crabstone::ARM => Hash[
|
27
|
+
reg_max: 111,
|
28
|
+
ins_max: 435,
|
29
|
+
grp_max: 159
|
30
|
+
],
|
31
|
+
Crabstone::MIPS => Hash[
|
32
|
+
reg_max: 136,
|
33
|
+
ins_max: 586,
|
34
|
+
grp_max: 161
|
35
|
+
],
|
36
|
+
Crabstone::PPC => Hash[
|
37
|
+
reg_max: 178,
|
38
|
+
ins_max: 934,
|
39
|
+
grp_max: 138
|
40
|
+
],
|
41
|
+
Crabstone::Sparc => Hash[
|
42
|
+
reg_max: 88,
|
43
|
+
ins_max: 279,
|
44
|
+
grp_max: 135
|
45
|
+
],
|
46
|
+
Crabstone::SysZ => Hash[
|
47
|
+
reg_max: 35,
|
48
|
+
ins_max: 682,
|
49
|
+
grp_max: 133
|
50
|
+
],
|
51
|
+
Crabstone::X86 => Hash[
|
52
|
+
reg_max: 234,
|
53
|
+
ins_max: 1295,
|
54
|
+
grp_max: 169
|
55
|
+
],
|
56
|
+
Crabstone::XCore => Hash[
|
57
|
+
reg_max: 26,
|
58
|
+
ins_max: 121,
|
59
|
+
grp_max: 2
|
60
|
+
],
|
61
|
+
}
|
62
|
+
|
63
|
+
begin
|
64
|
+
cs = Disassembler.new(0,0)
|
65
|
+
print "Sanity Check: Capstone v #{cs.version.join('.')}\n"
|
66
|
+
ensure
|
67
|
+
cs.close rescue nil
|
68
|
+
end
|
69
|
+
|
70
|
+
#Test through all modes and architectures
|
71
|
+
@checks.each do |klass, checklist|
|
72
|
+
if klass::REG_ENDING != checklist[:reg_max] ||
|
73
|
+
klass::INS_ENDING != checklist[:ins_max] ||
|
74
|
+
klass::GRP_ENDING != checklist[:grp_max]
|
75
|
+
puts "\t#{__FILE__}: #{klass}: FAIL"
|
76
|
+
else
|
77
|
+
puts "\t#{__FILE__}: #{klass}: PASS"
|
78
|
+
end
|
79
|
+
|
80
|
+
end
|
81
|
+
|
82
|
+
|
83
|
+
end
|
@@ -0,0 +1,111 @@
|
|
1
|
+
#! /usr/bin/env ruby
|
2
|
+
|
3
|
+
# Library by Nguyen Anh Quynh
|
4
|
+
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
5
|
+
# Additional binding work by Ben Nagy
|
6
|
+
# (c) 2013 COSEINC. All Rights Reserved.
|
7
|
+
|
8
|
+
require 'crabstone'
|
9
|
+
require 'stringio'
|
10
|
+
|
11
|
+
module TestSkipdata
|
12
|
+
|
13
|
+
include Crabstone
|
14
|
+
|
15
|
+
X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x00\x91\x92"
|
16
|
+
RANDOM_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
|
17
|
+
|
18
|
+
@platforms = [
|
19
|
+
Hash[
|
20
|
+
'arch' => ARCH_X86,
|
21
|
+
'mode' => MODE_32,
|
22
|
+
'code' => X86_CODE32,
|
23
|
+
'comment' => "X86 32 (Intel syntax) - Skip data",
|
24
|
+
'mnemonic' => nil,
|
25
|
+
'callback' => nil
|
26
|
+
],
|
27
|
+
Hash[
|
28
|
+
'arch' => ARCH_ARM,
|
29
|
+
'mode' => MODE_ARM,
|
30
|
+
'code' => RANDOM_CODE,
|
31
|
+
'comment' => "Arm - Skip data",
|
32
|
+
'mnemonic' => nil,
|
33
|
+
'callback' => nil
|
34
|
+
],
|
35
|
+
Hash[
|
36
|
+
'arch' => ARCH_X86,
|
37
|
+
'mode' => MODE_32,
|
38
|
+
'code' => X86_CODE32,
|
39
|
+
'comment' => "X86 32 (Intel syntax) - Skip data with custom mnemonic",
|
40
|
+
'mnemonic' => 'db',
|
41
|
+
'callback' => nil
|
42
|
+
],
|
43
|
+
Hash[
|
44
|
+
'arch' => ARCH_ARM,
|
45
|
+
'mode' => MODE_ARM,
|
46
|
+
'code' => RANDOM_CODE,
|
47
|
+
'comment' => "Arm - Skip data with callback",
|
48
|
+
'mnemonic' => 'db',
|
49
|
+
'callback' => lambda {|_,_| 2}
|
50
|
+
]
|
51
|
+
]
|
52
|
+
|
53
|
+
def self.uint32 i
|
54
|
+
Integer(i) & 0xffffffff
|
55
|
+
end
|
56
|
+
|
57
|
+
def self.uint64 i
|
58
|
+
Integer(i) & ((1<<64)-1)
|
59
|
+
end
|
60
|
+
|
61
|
+
ours = StringIO.new
|
62
|
+
|
63
|
+
begin
|
64
|
+
cs = Disassembler.new(0,0)
|
65
|
+
print "Skipdata Test: Capstone v #{cs.version.join('.')} - "
|
66
|
+
ensure
|
67
|
+
cs.close
|
68
|
+
end
|
69
|
+
|
70
|
+
#Test through all modes and architectures
|
71
|
+
@platforms.each do |p|
|
72
|
+
ours.puts "****************"
|
73
|
+
ours.puts "Platform: #{p['comment']}"
|
74
|
+
ours.puts "Code: #{p['code'].bytes.map {|b| "0x%.2x" % b}.join(' ')} "
|
75
|
+
ours.puts "Disasm:"
|
76
|
+
cs = Disassembler.new(p['arch'], p['mode'])
|
77
|
+
|
78
|
+
if p['syntax']
|
79
|
+
cs.syntax = p['syntax']
|
80
|
+
end
|
81
|
+
|
82
|
+
cs.decomposer = true
|
83
|
+
cache = nil
|
84
|
+
|
85
|
+
if p['mnemonic']
|
86
|
+
cs.skipdata p['mnemonic'], &(p['callback'])
|
87
|
+
else
|
88
|
+
# Even if callback is nil this turns on skipdata mode
|
89
|
+
cs.skipdata( &(p['callback']) )
|
90
|
+
end
|
91
|
+
|
92
|
+
cs.disasm(p['code'], 0x1000).each {|insn|
|
93
|
+
ours.puts "0x#{insn.address.to_s(16)}:\t#{insn.mnemonic}\t\t#{insn.op_str}"
|
94
|
+
cache = insn.address + insn.size
|
95
|
+
}
|
96
|
+
ours.printf("0x%x:\n", cache)
|
97
|
+
ours.puts
|
98
|
+
|
99
|
+
cs.close
|
100
|
+
end
|
101
|
+
|
102
|
+
ours.rewind
|
103
|
+
theirs = File.binread(__FILE__ + ".SPEC") rescue ''
|
104
|
+
if ours.read == theirs
|
105
|
+
puts "#{__FILE__}: PASS"
|
106
|
+
else
|
107
|
+
ours.rewind
|
108
|
+
puts ours.read
|
109
|
+
puts "#{__FILE__}: FAIL"
|
110
|
+
end
|
111
|
+
end
|