crabstone 3.0.3

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (302) hide show
  1. checksums.yaml +7 -0
  2. data/CHANGES.md +61 -0
  3. data/LICENSE +25 -0
  4. data/MANIFEST +312 -0
  5. data/README.md +103 -0
  6. data/Rakefile +27 -0
  7. data/bin/genconst +66 -0
  8. data/bin/genreg +99 -0
  9. data/crabstone.gemspec +27 -0
  10. data/examples/hello_world.rb +43 -0
  11. data/lib/arch/arm.rb +128 -0
  12. data/lib/arch/arm64.rb +167 -0
  13. data/lib/arch/arm64_const.rb +1055 -0
  14. data/lib/arch/arm64_registers.rb +295 -0
  15. data/lib/arch/arm_const.rb +777 -0
  16. data/lib/arch/arm_registers.rb +149 -0
  17. data/lib/arch/mips.rb +78 -0
  18. data/lib/arch/mips_const.rb +850 -0
  19. data/lib/arch/mips_registers.rb +208 -0
  20. data/lib/arch/ppc.rb +90 -0
  21. data/lib/arch/ppc_const.rb +1181 -0
  22. data/lib/arch/ppc_registers.rb +209 -0
  23. data/lib/arch/sparc.rb +79 -0
  24. data/lib/arch/sparc_const.rb +461 -0
  25. data/lib/arch/sparc_registers.rb +121 -0
  26. data/lib/arch/systemz.rb +79 -0
  27. data/lib/arch/sysz_const.rb +779 -0
  28. data/lib/arch/sysz_registers.rb +66 -0
  29. data/lib/arch/x86.rb +107 -0
  30. data/lib/arch/x86_const.rb +1698 -0
  31. data/lib/arch/x86_registers.rb +265 -0
  32. data/lib/arch/xcore.rb +78 -0
  33. data/lib/arch/xcore_const.rb +185 -0
  34. data/lib/arch/xcore_registers.rb +57 -0
  35. data/lib/crabstone.rb +564 -0
  36. data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
  37. data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
  38. data/test/MC/AArch64/neon-2velem.s.cs +113 -0
  39. data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
  40. data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
  41. data/test/MC/AArch64/neon-across.s.cs +40 -0
  42. data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
  43. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
  44. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
  45. data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
  46. data/test/MC/AArch64/neon-crypto.s.cs +15 -0
  47. data/test/MC/AArch64/neon-extract.s.cs +3 -0
  48. data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
  49. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
  50. data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
  51. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
  52. data/test/MC/AArch64/neon-max-min.s.cs +37 -0
  53. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
  54. data/test/MC/AArch64/neon-mov.s.cs +74 -0
  55. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
  56. data/test/MC/AArch64/neon-perm.s.cs +43 -0
  57. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
  58. data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
  59. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
  60. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
  61. data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
  62. data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
  63. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
  64. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
  65. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
  66. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
  67. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
  68. data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
  69. data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
  70. data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
  71. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
  72. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
  73. data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
  74. data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
  75. data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
  76. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
  77. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
  78. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
  79. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
  80. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
  81. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
  82. data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
  83. data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
  84. data/test/MC/AArch64/neon-shift.s.cs +22 -0
  85. data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
  86. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
  87. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
  88. data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
  89. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
  90. data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
  91. data/test/MC/AArch64/neon-tbl.s.cs +21 -0
  92. data/test/MC/AArch64/trace-regs.s.cs +383 -0
  93. data/test/MC/ARM/arm-aliases.s.cs +7 -0
  94. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
  95. data/test/MC/ARM/arm-it-block.s.cs +2 -0
  96. data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
  97. data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
  98. data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
  99. data/test/MC/ARM/arm-trustzone.s.cs +3 -0
  100. data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
  101. data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
  102. data/test/MC/ARM/arm_instructions.s.cs +25 -0
  103. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
  104. data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
  105. data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
  106. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
  107. data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
  108. data/test/MC/ARM/crc32-thumb.s.cs +7 -0
  109. data/test/MC/ARM/crc32.s.cs +7 -0
  110. data/test/MC/ARM/dot-req.s.cs +3 -0
  111. data/test/MC/ARM/fp-armv8.s.cs +52 -0
  112. data/test/MC/ARM/idiv-thumb.s.cs +3 -0
  113. data/test/MC/ARM/idiv.s.cs +3 -0
  114. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
  115. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
  116. data/test/MC/ARM/mode-switch.s.cs +7 -0
  117. data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
  118. data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
  119. data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
  120. data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
  121. data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
  122. data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
  123. data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
  124. data/test/MC/ARM/neon-crypto.s.cs +16 -0
  125. data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
  126. data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
  127. data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
  128. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
  129. data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
  130. data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
  131. data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
  132. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
  133. data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
  134. data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
  135. data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
  136. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
  137. data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
  138. data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
  139. data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
  140. data/test/MC/ARM/neon-v8.s.cs +38 -0
  141. data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
  142. data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
  143. data/test/MC/ARM/neon-vswp.s.cs +3 -0
  144. data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
  145. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
  146. data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
  147. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
  148. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
  149. data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
  150. data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
  151. data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
  152. data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
  153. data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
  154. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
  155. data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
  156. data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
  157. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
  158. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
  159. data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
  160. data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
  161. data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
  162. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
  163. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
  164. data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
  165. data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
  166. data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
  167. data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
  168. data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
  169. data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
  170. data/test/MC/ARM/thumb-hints.s.cs +12 -0
  171. data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
  172. data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
  173. data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
  174. data/test/MC/ARM/thumb.s.cs +19 -0
  175. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
  176. data/test/MC/ARM/thumb2-branches.s.cs +85 -0
  177. data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
  178. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
  179. data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
  180. data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
  181. data/test/MC/ARM/vfp4.s.cs +13 -0
  182. data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
  183. data/test/MC/ARM/vpush-vpop.s.cs +9 -0
  184. data/test/MC/Mips/hilo-addressing.s.cs +4 -0
  185. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
  186. data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
  187. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
  188. data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
  189. data/test/MC/Mips/micromips-expansions.s.cs +20 -0
  190. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
  191. data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
  192. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
  193. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
  194. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
  195. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
  196. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
  197. data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
  198. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
  199. data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
  200. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
  201. data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
  202. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
  203. data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
  204. data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
  205. data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
  206. data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
  207. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
  208. data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
  209. data/test/MC/Mips/mips-expansions.s.cs +20 -0
  210. data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
  211. data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
  212. data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
  213. data/test/MC/Mips/mips-register-names.s.cs +33 -0
  214. data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
  215. data/test/MC/Mips/mips64-instructions.s.cs +3 -0
  216. data/test/MC/Mips/mips64-register-names.s.cs +33 -0
  217. data/test/MC/Mips/mips_directives.s.cs +12 -0
  218. data/test/MC/Mips/nabi-regs.s.cs +12 -0
  219. data/test/MC/Mips/set-at-directive.s.cs +6 -0
  220. data/test/MC/Mips/test_2r.s.cs +16 -0
  221. data/test/MC/Mips/test_2rf.s.cs +33 -0
  222. data/test/MC/Mips/test_3r.s.cs +243 -0
  223. data/test/MC/Mips/test_3rf.s.cs +83 -0
  224. data/test/MC/Mips/test_bit.s.cs +49 -0
  225. data/test/MC/Mips/test_cbranch.s.cs +11 -0
  226. data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
  227. data/test/MC/Mips/test_elm.s.cs +16 -0
  228. data/test/MC/Mips/test_elm_insert.s.cs +4 -0
  229. data/test/MC/Mips/test_elm_insve.s.cs +5 -0
  230. data/test/MC/Mips/test_i10.s.cs +5 -0
  231. data/test/MC/Mips/test_i5.s.cs +45 -0
  232. data/test/MC/Mips/test_i8.s.cs +11 -0
  233. data/test/MC/Mips/test_lsa.s.cs +5 -0
  234. data/test/MC/Mips/test_mi10.s.cs +24 -0
  235. data/test/MC/Mips/test_vec.s.cs +8 -0
  236. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
  237. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
  238. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
  239. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
  240. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
  241. data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
  242. data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
  243. data/test/MC/README +6 -0
  244. data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
  245. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
  246. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
  247. data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
  248. data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
  249. data/test/MC/Sparc/sparc-vis.s.cs +2 -0
  250. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
  251. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
  252. data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
  253. data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
  254. data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
  255. data/test/MC/SystemZ/insn-good.s.cs +2265 -0
  256. data/test/MC/SystemZ/regs-good.s.cs +45 -0
  257. data/test/MC/X86/3DNow.s.cs +29 -0
  258. data/test/MC/X86/address-size.s.cs +5 -0
  259. data/test/MC/X86/avx512-encodings.s.cs +12 -0
  260. data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
  261. data/test/MC/X86/x86-32-avx.s.cs +833 -0
  262. data/test/MC/X86/x86-32-fma3.s.cs +169 -0
  263. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
  264. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
  265. data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
  266. data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
  267. data/test/MC/X86/x86_64-encoding.s.cs +59 -0
  268. data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
  269. data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
  270. data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
  271. data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
  272. data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
  273. data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
  274. data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
  275. data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
  276. data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
  277. data/test/README +6 -0
  278. data/test/test.rb +205 -0
  279. data/test/test.rb.SPEC +235 -0
  280. data/test/test_arm.rb +202 -0
  281. data/test/test_arm.rb.SPEC +275 -0
  282. data/test/test_arm64.rb +150 -0
  283. data/test/test_arm64.rb.SPEC +116 -0
  284. data/test/test_detail.rb +228 -0
  285. data/test/test_detail.rb.SPEC +322 -0
  286. data/test/test_exhaustive.rb +80 -0
  287. data/test/test_mips.rb +118 -0
  288. data/test/test_mips.rb.SPEC +91 -0
  289. data/test/test_ppc.rb +137 -0
  290. data/test/test_ppc.rb.SPEC +84 -0
  291. data/test/test_sanity.rb +83 -0
  292. data/test/test_skipdata.rb +111 -0
  293. data/test/test_skipdata.rb.SPEC +58 -0
  294. data/test/test_sparc.rb +113 -0
  295. data/test/test_sparc.rb.SPEC +116 -0
  296. data/test/test_sysz.rb +111 -0
  297. data/test/test_sysz.rb.SPEC +61 -0
  298. data/test/test_x86.rb +189 -0
  299. data/test/test_x86.rb.SPEC +579 -0
  300. data/test/test_xcore.rb +100 -0
  301. data/test/test_xcore.rb.SPEC +75 -0
  302. metadata +393 -0
@@ -0,0 +1,111 @@
1
+ # CS_ARCH_ARM64, 0, None
2
+ 0x08,0xcc,0x38,0xd5 = mrs x8, icc_iar1_el1
3
+ 0x1a,0xc8,0x38,0xd5 = mrs x26, icc_iar0_el1
4
+ 0x42,0xcc,0x38,0xd5 = mrs x2, icc_hppir1_el1
5
+ 0x51,0xc8,0x38,0xd5 = mrs x17, icc_hppir0_el1
6
+ 0x7d,0xcb,0x38,0xd5 = mrs x29, icc_rpr_el1
7
+ 0x24,0xcb,0x3c,0xd5 = mrs x4, ich_vtr_el2
8
+ 0x78,0xcb,0x3c,0xd5 = mrs x24, ich_eisr_el2
9
+ 0xa9,0xcb,0x3c,0xd5 = mrs x9, ich_elsr_el2
10
+ 0x78,0xcc,0x38,0xd5 = mrs x24, icc_bpr1_el1
11
+ 0x6e,0xc8,0x38,0xd5 = mrs x14, icc_bpr0_el1
12
+ 0x13,0x46,0x38,0xd5 = mrs x19, icc_pmr_el1
13
+ 0x97,0xcc,0x38,0xd5 = mrs x23, icc_ctlr_el1
14
+ 0x94,0xcc,0x3e,0xd5 = mrs x20, icc_ctlr_el3
15
+ 0xbc,0xcc,0x38,0xd5 = mrs x28, icc_sre_el1
16
+ 0xb9,0xc9,0x3c,0xd5 = mrs x25, icc_sre_el2
17
+ 0xa8,0xcc,0x3e,0xd5 = mrs x8, icc_sre_el3
18
+ 0xd6,0xcc,0x38,0xd5 = mrs x22, icc_igrpen0_el1
19
+ 0xe5,0xcc,0x38,0xd5 = mrs x5, icc_igrpen1_el1
20
+ 0xe7,0xcc,0x3e,0xd5 = mrs x7, icc_igrpen1_el3
21
+ 0x16,0xcd,0x38,0xd5 = mrs x22, icc_seien_el1
22
+ 0x84,0xc8,0x38,0xd5 = mrs x4, icc_ap0r0_el1
23
+ 0xab,0xc8,0x38,0xd5 = mrs x11, icc_ap0r1_el1
24
+ 0xdb,0xc8,0x38,0xd5 = mrs x27, icc_ap0r2_el1
25
+ 0xf5,0xc8,0x38,0xd5 = mrs x21, icc_ap0r3_el1
26
+ 0x02,0xc9,0x38,0xd5 = mrs x2, icc_ap1r0_el1
27
+ 0x35,0xc9,0x38,0xd5 = mrs x21, icc_ap1r1_el1
28
+ 0x4a,0xc9,0x38,0xd5 = mrs x10, icc_ap1r2_el1
29
+ 0x7b,0xc9,0x38,0xd5 = mrs x27, icc_ap1r3_el1
30
+ 0x14,0xc8,0x3c,0xd5 = mrs x20, ich_ap0r0_el2
31
+ 0x35,0xc8,0x3c,0xd5 = mrs x21, ich_ap0r1_el2
32
+ 0x45,0xc8,0x3c,0xd5 = mrs x5, ich_ap0r2_el2
33
+ 0x64,0xc8,0x3c,0xd5 = mrs x4, ich_ap0r3_el2
34
+ 0x0f,0xc9,0x3c,0xd5 = mrs x15, ich_ap1r0_el2
35
+ 0x2c,0xc9,0x3c,0xd5 = mrs x12, ich_ap1r1_el2
36
+ 0x5b,0xc9,0x3c,0xd5 = mrs x27, ich_ap1r2_el2
37
+ 0x74,0xc9,0x3c,0xd5 = mrs x20, ich_ap1r3_el2
38
+ 0x0a,0xcb,0x3c,0xd5 = mrs x10, ich_hcr_el2
39
+ 0x5b,0xcb,0x3c,0xd5 = mrs x27, ich_misr_el2
40
+ 0xe6,0xcb,0x3c,0xd5 = mrs x6, ich_vmcr_el2
41
+ 0x93,0xc9,0x3c,0xd5 = mrs x19, ich_vseir_el2
42
+ 0x03,0xcc,0x3c,0xd5 = mrs x3, ich_lr0_el2
43
+ 0x21,0xcc,0x3c,0xd5 = mrs x1, ich_lr1_el2
44
+ 0x56,0xcc,0x3c,0xd5 = mrs x22, ich_lr2_el2
45
+ 0x75,0xcc,0x3c,0xd5 = mrs x21, ich_lr3_el2
46
+ 0x86,0xcc,0x3c,0xd5 = mrs x6, ich_lr4_el2
47
+ 0xaa,0xcc,0x3c,0xd5 = mrs x10, ich_lr5_el2
48
+ 0xcb,0xcc,0x3c,0xd5 = mrs x11, ich_lr6_el2
49
+ 0xec,0xcc,0x3c,0xd5 = mrs x12, ich_lr7_el2
50
+ 0x00,0xcd,0x3c,0xd5 = mrs x0, ich_lr8_el2
51
+ 0x35,0xcd,0x3c,0xd5 = mrs x21, ich_lr9_el2
52
+ 0x4d,0xcd,0x3c,0xd5 = mrs x13, ich_lr10_el2
53
+ 0x7a,0xcd,0x3c,0xd5 = mrs x26, ich_lr11_el2
54
+ 0x81,0xcd,0x3c,0xd5 = mrs x1, ich_lr12_el2
55
+ 0xa8,0xcd,0x3c,0xd5 = mrs x8, ich_lr13_el2
56
+ 0xc2,0xcd,0x3c,0xd5 = mrs x2, ich_lr14_el2
57
+ 0xe8,0xcd,0x3c,0xd5 = mrs x8, ich_lr15_el2
58
+ 0x3b,0xcc,0x18,0xd5 = msr icc_eoir1_el1, x27
59
+ 0x25,0xc8,0x18,0xd5 = msr icc_eoir0_el1, x5
60
+ 0x2d,0xcb,0x18,0xd5 = msr icc_dir_el1, x13
61
+ 0xb5,0xcb,0x18,0xd5 = msr icc_sgi1r_el1, x21
62
+ 0xd9,0xcb,0x18,0xd5 = msr icc_asgi1r_el1, x25
63
+ 0xfc,0xcb,0x18,0xd5 = msr icc_sgi0r_el1, x28
64
+ 0x67,0xcc,0x18,0xd5 = msr icc_bpr1_el1, x7
65
+ 0x69,0xc8,0x18,0xd5 = msr icc_bpr0_el1, x9
66
+ 0x1d,0x46,0x18,0xd5 = msr icc_pmr_el1, x29
67
+ 0x98,0xcc,0x18,0xd5 = msr icc_ctlr_el1, x24
68
+ 0x80,0xcc,0x1e,0xd5 = msr icc_ctlr_el3, x0
69
+ 0xa2,0xcc,0x18,0xd5 = msr icc_sre_el1, x2
70
+ 0xa5,0xc9,0x1c,0xd5 = msr icc_sre_el2, x5
71
+ 0xaa,0xcc,0x1e,0xd5 = msr icc_sre_el3, x10
72
+ 0xd6,0xcc,0x18,0xd5 = msr icc_igrpen0_el1, x22
73
+ 0xeb,0xcc,0x18,0xd5 = msr icc_igrpen1_el1, x11
74
+ 0xe8,0xcc,0x1e,0xd5 = msr icc_igrpen1_el3, x8
75
+ 0x04,0xcd,0x18,0xd5 = msr icc_seien_el1, x4
76
+ 0x9b,0xc8,0x18,0xd5 = msr icc_ap0r0_el1, x27
77
+ 0xa5,0xc8,0x18,0xd5 = msr icc_ap0r1_el1, x5
78
+ 0xd4,0xc8,0x18,0xd5 = msr icc_ap0r2_el1, x20
79
+ 0xe0,0xc8,0x18,0xd5 = msr icc_ap0r3_el1, x0
80
+ 0x02,0xc9,0x18,0xd5 = msr icc_ap1r0_el1, x2
81
+ 0x3d,0xc9,0x18,0xd5 = msr icc_ap1r1_el1, x29
82
+ 0x57,0xc9,0x18,0xd5 = msr icc_ap1r2_el1, x23
83
+ 0x6b,0xc9,0x18,0xd5 = msr icc_ap1r3_el1, x11
84
+ 0x02,0xc8,0x1c,0xd5 = msr ich_ap0r0_el2, x2
85
+ 0x3b,0xc8,0x1c,0xd5 = msr ich_ap0r1_el2, x27
86
+ 0x47,0xc8,0x1c,0xd5 = msr ich_ap0r2_el2, x7
87
+ 0x61,0xc8,0x1c,0xd5 = msr ich_ap0r3_el2, x1
88
+ 0x07,0xc9,0x1c,0xd5 = msr ich_ap1r0_el2, x7
89
+ 0x2c,0xc9,0x1c,0xd5 = msr ich_ap1r1_el2, x12
90
+ 0x4e,0xc9,0x1c,0xd5 = msr ich_ap1r2_el2, x14
91
+ 0x6d,0xc9,0x1c,0xd5 = msr ich_ap1r3_el2, x13
92
+ 0x01,0xcb,0x1c,0xd5 = msr ich_hcr_el2, x1
93
+ 0x4a,0xcb,0x1c,0xd5 = msr ich_misr_el2, x10
94
+ 0xf8,0xcb,0x1c,0xd5 = msr ich_vmcr_el2, x24
95
+ 0x9d,0xc9,0x1c,0xd5 = msr ich_vseir_el2, x29
96
+ 0x1a,0xcc,0x1c,0xd5 = msr ich_lr0_el2, x26
97
+ 0x29,0xcc,0x1c,0xd5 = msr ich_lr1_el2, x9
98
+ 0x52,0xcc,0x1c,0xd5 = msr ich_lr2_el2, x18
99
+ 0x7a,0xcc,0x1c,0xd5 = msr ich_lr3_el2, x26
100
+ 0x96,0xcc,0x1c,0xd5 = msr ich_lr4_el2, x22
101
+ 0xba,0xcc,0x1c,0xd5 = msr ich_lr5_el2, x26
102
+ 0xdb,0xcc,0x1c,0xd5 = msr ich_lr6_el2, x27
103
+ 0xe8,0xcc,0x1c,0xd5 = msr ich_lr7_el2, x8
104
+ 0x11,0xcd,0x1c,0xd5 = msr ich_lr8_el2, x17
105
+ 0x33,0xcd,0x1c,0xd5 = msr ich_lr9_el2, x19
106
+ 0x51,0xcd,0x1c,0xd5 = msr ich_lr10_el2, x17
107
+ 0x65,0xcd,0x1c,0xd5 = msr ich_lr11_el2, x5
108
+ 0x9d,0xcd,0x1c,0xd5 = msr ich_lr12_el2, x29
109
+ 0xa2,0xcd,0x1c,0xd5 = msr ich_lr13_el2, x2
110
+ 0xcd,0xcd,0x1c,0xd5 = msr ich_lr14_el2, x13
111
+ 0xfb,0xcd,0x1c,0xd5 = msr ich_lr15_el2, x27
@@ -0,0 +1,113 @@
1
+ # CS_ARCH_ARM64, 0, None
2
+ 0x20,0x08,0x82,0x2f = mla v0.2s, v1.2s, v2.s[2]
3
+ 0x20,0x08,0x96,0x2f = mla v0.2s, v1.2s, v22.s[2]
4
+ 0x03,0x01,0xa2,0x6f = mla v3.4s, v8.4s, v2.s[1]
5
+ 0x03,0x09,0xb6,0x6f = mla v3.4s, v8.4s, v22.s[3]
6
+ 0x20,0x00,0x62,0x2f = mla v0.4h, v1.4h, v2.h[2]
7
+ 0x20,0x00,0x6f,0x2f = mla v0.4h, v1.4h, v15.h[2]
8
+ 0x20,0x08,0x72,0x6f = mla v0.8h, v1.8h, v2.h[7]
9
+ 0x20,0x08,0x6e,0x6f = mla v0.8h, v1.8h, v14.h[6]
10
+ 0x20,0x48,0x82,0x2f = mls v0.2s, v1.2s, v2.s[2]
11
+ 0x20,0x48,0x96,0x2f = mls v0.2s, v1.2s, v22.s[2]
12
+ 0x03,0x41,0xa2,0x6f = mls v3.4s, v8.4s, v2.s[1]
13
+ 0x03,0x49,0xb6,0x6f = mls v3.4s, v8.4s, v22.s[3]
14
+ 0x20,0x40,0x62,0x2f = mls v0.4h, v1.4h, v2.h[2]
15
+ 0x20,0x40,0x6f,0x2f = mls v0.4h, v1.4h, v15.h[2]
16
+ 0x20,0x48,0x72,0x6f = mls v0.8h, v1.8h, v2.h[7]
17
+ 0x20,0x48,0x6e,0x6f = mls v0.8h, v1.8h, v14.h[6]
18
+ 0x20,0x18,0x82,0x0f = fmla v0.2s, v1.2s, v2.s[2]
19
+ 0x20,0x18,0x96,0x0f = fmla v0.2s, v1.2s, v22.s[2]
20
+ 0x03,0x11,0xa2,0x4f = fmla v3.4s, v8.4s, v2.s[1]
21
+ 0x03,0x19,0xb6,0x4f = fmla v3.4s, v8.4s, v22.s[3]
22
+ 0x20,0x18,0xc2,0x4f = fmla v0.2d, v1.2d, v2.d[1]
23
+ 0x20,0x18,0xd6,0x4f = fmla v0.2d, v1.2d, v22.d[1]
24
+ 0x20,0x58,0x82,0x0f = fmls v0.2s, v1.2s, v2.s[2]
25
+ 0x20,0x58,0x96,0x0f = fmls v0.2s, v1.2s, v22.s[2]
26
+ 0x03,0x51,0xa2,0x4f = fmls v3.4s, v8.4s, v2.s[1]
27
+ 0x03,0x59,0xb6,0x4f = fmls v3.4s, v8.4s, v22.s[3]
28
+ 0x20,0x58,0xc2,0x4f = fmls v0.2d, v1.2d, v2.d[1]
29
+ 0x20,0x58,0xd6,0x4f = fmls v0.2d, v1.2d, v22.d[1]
30
+ 0x20,0x20,0x62,0x0f = smlal v0.4s, v1.4h, v2.h[2]
31
+ 0x20,0x28,0x82,0x0f = smlal v0.2d, v1.2s, v2.s[2]
32
+ 0x20,0x28,0x96,0x0f = smlal v0.2d, v1.2s, v22.s[2]
33
+ 0x20,0x20,0x61,0x4f = smlal2 v0.4s, v1.8h, v1.h[2]
34
+ 0x20,0x28,0x81,0x4f = smlal2 v0.2d, v1.4s, v1.s[2]
35
+ 0x20,0x28,0x96,0x4f = smlal2 v0.2d, v1.4s, v22.s[2]
36
+ 0x20,0x60,0x62,0x0f = smlsl v0.4s, v1.4h, v2.h[2]
37
+ 0x20,0x68,0x82,0x0f = smlsl v0.2d, v1.2s, v2.s[2]
38
+ 0x20,0x68,0x96,0x0f = smlsl v0.2d, v1.2s, v22.s[2]
39
+ 0x20,0x60,0x61,0x4f = smlsl2 v0.4s, v1.8h, v1.h[2]
40
+ 0x20,0x68,0x81,0x4f = smlsl2 v0.2d, v1.4s, v1.s[2]
41
+ 0x20,0x68,0x96,0x4f = smlsl2 v0.2d, v1.4s, v22.s[2]
42
+ 0x20,0x30,0x62,0x0f = sqdmlal v0.4s, v1.4h, v2.h[2]
43
+ 0x20,0x38,0x82,0x0f = sqdmlal v0.2d, v1.2s, v2.s[2]
44
+ 0x20,0x38,0x96,0x0f = sqdmlal v0.2d, v1.2s, v22.s[2]
45
+ 0x20,0x30,0x61,0x4f = sqdmlal2 v0.4s, v1.8h, v1.h[2]
46
+ 0x20,0x38,0x81,0x4f = sqdmlal2 v0.2d, v1.4s, v1.s[2]
47
+ 0x20,0x38,0x96,0x4f = sqdmlal2 v0.2d, v1.4s, v22.s[2]
48
+ 0x20,0x20,0x62,0x2f = umlal v0.4s, v1.4h, v2.h[2]
49
+ 0x20,0x28,0x82,0x2f = umlal v0.2d, v1.2s, v2.s[2]
50
+ 0x20,0x28,0x96,0x2f = umlal v0.2d, v1.2s, v22.s[2]
51
+ 0x20,0x20,0x61,0x6f = umlal2 v0.4s, v1.8h, v1.h[2]
52
+ 0x20,0x28,0x81,0x6f = umlal2 v0.2d, v1.4s, v1.s[2]
53
+ 0x20,0x28,0x96,0x6f = umlal2 v0.2d, v1.4s, v22.s[2]
54
+ 0x20,0x60,0x62,0x2f = umlsl v0.4s, v1.4h, v2.h[2]
55
+ 0x20,0x68,0x82,0x2f = umlsl v0.2d, v1.2s, v2.s[2]
56
+ 0x20,0x68,0x96,0x2f = umlsl v0.2d, v1.2s, v22.s[2]
57
+ 0x20,0x60,0x61,0x6f = umlsl2 v0.4s, v1.8h, v1.h[2]
58
+ 0x20,0x68,0x81,0x6f = umlsl2 v0.2d, v1.4s, v1.s[2]
59
+ 0x20,0x68,0x96,0x6f = umlsl2 v0.2d, v1.4s, v22.s[2]
60
+ 0x20,0x70,0x62,0x0f = sqdmlsl v0.4s, v1.4h, v2.h[2]
61
+ 0x20,0x78,0x82,0x0f = sqdmlsl v0.2d, v1.2s, v2.s[2]
62
+ 0x20,0x78,0x96,0x0f = sqdmlsl v0.2d, v1.2s, v22.s[2]
63
+ 0x20,0x70,0x61,0x4f = sqdmlsl2 v0.4s, v1.8h, v1.h[2]
64
+ 0x20,0x78,0x81,0x4f = sqdmlsl2 v0.2d, v1.4s, v1.s[2]
65
+ 0x20,0x78,0x96,0x4f = sqdmlsl2 v0.2d, v1.4s, v22.s[2]
66
+ 0x20,0x80,0x62,0x0f = mul v0.4h, v1.4h, v2.h[2]
67
+ 0x20,0x80,0x62,0x4f = mul v0.8h, v1.8h, v2.h[2]
68
+ 0x20,0x88,0x82,0x0f = mul v0.2s, v1.2s, v2.s[2]
69
+ 0x20,0x88,0x96,0x0f = mul v0.2s, v1.2s, v22.s[2]
70
+ 0x20,0x88,0x82,0x4f = mul v0.4s, v1.4s, v2.s[2]
71
+ 0x20,0x88,0x96,0x4f = mul v0.4s, v1.4s, v22.s[2]
72
+ 0x20,0x98,0x82,0x0f = fmul v0.2s, v1.2s, v2.s[2]
73
+ 0x20,0x98,0x96,0x0f = fmul v0.2s, v1.2s, v22.s[2]
74
+ 0x20,0x98,0x82,0x4f = fmul v0.4s, v1.4s, v2.s[2]
75
+ 0x20,0x98,0x96,0x4f = fmul v0.4s, v1.4s, v22.s[2]
76
+ 0x20,0x98,0xc2,0x4f = fmul v0.2d, v1.2d, v2.d[1]
77
+ 0x20,0x98,0xd6,0x4f = fmul v0.2d, v1.2d, v22.d[1]
78
+ 0x20,0x98,0x82,0x2f = fmulx v0.2s, v1.2s, v2.s[2]
79
+ 0x20,0x98,0x96,0x2f = fmulx v0.2s, v1.2s, v22.s[2]
80
+ 0x20,0x98,0x82,0x6f = fmulx v0.4s, v1.4s, v2.s[2]
81
+ 0x20,0x98,0x96,0x6f = fmulx v0.4s, v1.4s, v22.s[2]
82
+ 0x20,0x98,0xc2,0x6f = fmulx v0.2d, v1.2d, v2.d[1]
83
+ 0x20,0x98,0xd6,0x6f = fmulx v0.2d, v1.2d, v22.d[1]
84
+ 0x20,0xa0,0x62,0x0f = smull v0.4s, v1.4h, v2.h[2]
85
+ 0x20,0xa8,0x82,0x0f = smull v0.2d, v1.2s, v2.s[2]
86
+ 0x20,0xa8,0x96,0x0f = smull v0.2d, v1.2s, v22.s[2]
87
+ 0x20,0xa0,0x62,0x4f = smull2 v0.4s, v1.8h, v2.h[2]
88
+ 0x20,0xa8,0x82,0x4f = smull2 v0.2d, v1.4s, v2.s[2]
89
+ 0x20,0xa8,0x96,0x4f = smull2 v0.2d, v1.4s, v22.s[2]
90
+ 0x20,0xa0,0x62,0x2f = umull v0.4s, v1.4h, v2.h[2]
91
+ 0x20,0xa8,0x82,0x2f = umull v0.2d, v1.2s, v2.s[2]
92
+ 0x20,0xa8,0x96,0x2f = umull v0.2d, v1.2s, v22.s[2]
93
+ 0x20,0xa0,0x62,0x6f = umull2 v0.4s, v1.8h, v2.h[2]
94
+ 0x20,0xa8,0x82,0x6f = umull2 v0.2d, v1.4s, v2.s[2]
95
+ 0x20,0xa8,0x96,0x6f = umull2 v0.2d, v1.4s, v22.s[2]
96
+ 0x20,0xb0,0x62,0x0f = sqdmull v0.4s, v1.4h, v2.h[2]
97
+ 0x20,0xb8,0x82,0x0f = sqdmull v0.2d, v1.2s, v2.s[2]
98
+ 0x20,0xb8,0x96,0x0f = sqdmull v0.2d, v1.2s, v22.s[2]
99
+ 0x20,0xb0,0x62,0x4f = sqdmull2 v0.4s, v1.8h, v2.h[2]
100
+ 0x20,0xb8,0x82,0x4f = sqdmull2 v0.2d, v1.4s, v2.s[2]
101
+ 0x20,0xb8,0x96,0x4f = sqdmull2 v0.2d, v1.4s, v22.s[2]
102
+ 0x20,0xc0,0x62,0x0f = sqdmulh v0.4h, v1.4h, v2.h[2]
103
+ 0x20,0xc0,0x62,0x4f = sqdmulh v0.8h, v1.8h, v2.h[2]
104
+ 0x20,0xc8,0x82,0x0f = sqdmulh v0.2s, v1.2s, v2.s[2]
105
+ 0x20,0xc8,0x96,0x0f = sqdmulh v0.2s, v1.2s, v22.s[2]
106
+ 0x20,0xc8,0x82,0x4f = sqdmulh v0.4s, v1.4s, v2.s[2]
107
+ 0x20,0xc8,0x96,0x4f = sqdmulh v0.4s, v1.4s, v22.s[2]
108
+ 0x20,0xd0,0x62,0x0f = sqrdmulh v0.4h, v1.4h, v2.h[2]
109
+ 0x20,0xd0,0x62,0x4f = sqrdmulh v0.8h, v1.8h, v2.h[2]
110
+ 0x20,0xd8,0x82,0x0f = sqrdmulh v0.2s, v1.2s, v2.s[2]
111
+ 0x20,0xd8,0x96,0x0f = sqrdmulh v0.2s, v1.2s, v22.s[2]
112
+ 0x20,0xd8,0x82,0x4f = sqrdmulh v0.4s, v1.4s, v2.s[2]
113
+ 0x20,0xd8,0x96,0x4f = sqrdmulh v0.4s, v1.4s, v22.s[2]
@@ -0,0 +1,143 @@
1
+ # CS_ARCH_ARM64, 0, None
2
+ 0x20,0x00,0x22,0x0e = saddl v0.8h, v1.8b, v2.8b
3
+ 0x20,0x00,0x62,0x0e = saddl v0.4s, v1.4h, v2.4h
4
+ 0x20,0x00,0xa2,0x0e = saddl v0.2d, v1.2s, v2.2s
5
+ 0x20,0x00,0x62,0x4e = saddl2 v0.4s, v1.8h, v2.8h
6
+ 0x20,0x00,0x22,0x4e = saddl2 v0.8h, v1.16b, v2.16b
7
+ 0x20,0x00,0xa2,0x4e = saddl2 v0.2d, v1.4s, v2.4s
8
+ 0x20,0x00,0x22,0x2e = uaddl v0.8h, v1.8b, v2.8b
9
+ 0x20,0x00,0x62,0x2e = uaddl v0.4s, v1.4h, v2.4h
10
+ 0x20,0x00,0xa2,0x2e = uaddl v0.2d, v1.2s, v2.2s
11
+ 0x20,0x00,0x22,0x6e = uaddl2 v0.8h, v1.16b, v2.16b
12
+ 0x20,0x00,0x62,0x6e = uaddl2 v0.4s, v1.8h, v2.8h
13
+ 0x20,0x00,0xa2,0x6e = uaddl2 v0.2d, v1.4s, v2.4s
14
+ 0x20,0x20,0x22,0x0e = ssubl v0.8h, v1.8b, v2.8b
15
+ 0x20,0x20,0x62,0x0e = ssubl v0.4s, v1.4h, v2.4h
16
+ 0x20,0x20,0xa2,0x0e = ssubl v0.2d, v1.2s, v2.2s
17
+ 0x20,0x20,0x22,0x4e = ssubl2 v0.8h, v1.16b, v2.16b
18
+ 0x20,0x20,0x62,0x4e = ssubl2 v0.4s, v1.8h, v2.8h
19
+ 0x20,0x20,0xa2,0x4e = ssubl2 v0.2d, v1.4s, v2.4s
20
+ 0x20,0x20,0x22,0x2e = usubl v0.8h, v1.8b, v2.8b
21
+ 0x20,0x20,0x62,0x2e = usubl v0.4s, v1.4h, v2.4h
22
+ 0x20,0x20,0xa2,0x2e = usubl v0.2d, v1.2s, v2.2s
23
+ 0x20,0x20,0x22,0x6e = usubl2 v0.8h, v1.16b, v2.16b
24
+ 0x20,0x20,0x62,0x6e = usubl2 v0.4s, v1.8h, v2.8h
25
+ 0x20,0x20,0xa2,0x6e = usubl2 v0.2d, v1.4s, v2.4s
26
+ 0x20,0x50,0x22,0x0e = sabal v0.8h, v1.8b, v2.8b
27
+ 0x20,0x50,0x62,0x0e = sabal v0.4s, v1.4h, v2.4h
28
+ 0x20,0x50,0xa2,0x0e = sabal v0.2d, v1.2s, v2.2s
29
+ 0x20,0x50,0x22,0x4e = sabal2 v0.8h, v1.16b, v2.16b
30
+ 0x20,0x50,0x62,0x4e = sabal2 v0.4s, v1.8h, v2.8h
31
+ 0x20,0x50,0xa2,0x4e = sabal2 v0.2d, v1.4s, v2.4s
32
+ 0x20,0x50,0x22,0x2e = uabal v0.8h, v1.8b, v2.8b
33
+ 0x20,0x50,0x62,0x2e = uabal v0.4s, v1.4h, v2.4h
34
+ 0x20,0x50,0xa2,0x2e = uabal v0.2d, v1.2s, v2.2s
35
+ 0x20,0x50,0x22,0x6e = uabal2 v0.8h, v1.16b, v2.16b
36
+ 0x20,0x50,0x62,0x6e = uabal2 v0.4s, v1.8h, v2.8h
37
+ 0x20,0x50,0xa2,0x6e = uabal2 v0.2d, v1.4s, v2.4s
38
+ 0x20,0x70,0x22,0x0e = sabdl v0.8h, v1.8b, v2.8b
39
+ 0x20,0x70,0x62,0x0e = sabdl v0.4s, v1.4h, v2.4h
40
+ 0x20,0x70,0xa2,0x0e = sabdl v0.2d, v1.2s, v2.2s
41
+ 0x20,0x70,0x22,0x4e = sabdl2 v0.8h, v1.16b, v2.16b
42
+ 0x20,0x70,0x62,0x4e = sabdl2 v0.4s, v1.8h, v2.8h
43
+ 0x20,0x70,0xa2,0x4e = sabdl2 v0.2d, v1.4s, v2.4s
44
+ 0x20,0x70,0x22,0x2e = uabdl v0.8h, v1.8b, v2.8b
45
+ 0x20,0x70,0x62,0x2e = uabdl v0.4s, v1.4h, v2.4h
46
+ 0x20,0x70,0xa2,0x2e = uabdl v0.2d, v1.2s, v2.2s
47
+ 0x20,0x70,0x22,0x6e = uabdl2 v0.8h, v1.16b, v2.16b
48
+ 0x20,0x70,0x62,0x6e = uabdl2 v0.4s, v1.8h, v2.8h
49
+ 0x20,0x70,0xa2,0x6e = uabdl2 v0.2d, v1.4s, v2.4s
50
+ 0x20,0x80,0x22,0x0e = smlal v0.8h, v1.8b, v2.8b
51
+ 0x20,0x80,0x62,0x0e = smlal v0.4s, v1.4h, v2.4h
52
+ 0x20,0x80,0xa2,0x0e = smlal v0.2d, v1.2s, v2.2s
53
+ 0x20,0x80,0x22,0x4e = smlal2 v0.8h, v1.16b, v2.16b
54
+ 0x20,0x80,0x62,0x4e = smlal2 v0.4s, v1.8h, v2.8h
55
+ 0x20,0x80,0xa2,0x4e = smlal2 v0.2d, v1.4s, v2.4s
56
+ 0x20,0x80,0x22,0x2e = umlal v0.8h, v1.8b, v2.8b
57
+ 0x20,0x80,0x62,0x2e = umlal v0.4s, v1.4h, v2.4h
58
+ 0x20,0x80,0xa2,0x2e = umlal v0.2d, v1.2s, v2.2s
59
+ 0x20,0x80,0x22,0x6e = umlal2 v0.8h, v1.16b, v2.16b
60
+ 0x20,0x80,0x62,0x6e = umlal2 v0.4s, v1.8h, v2.8h
61
+ 0x20,0x80,0xa2,0x6e = umlal2 v0.2d, v1.4s, v2.4s
62
+ 0x20,0xa0,0x22,0x0e = smlsl v0.8h, v1.8b, v2.8b
63
+ 0x20,0xa0,0x62,0x0e = smlsl v0.4s, v1.4h, v2.4h
64
+ 0x20,0xa0,0xa2,0x0e = smlsl v0.2d, v1.2s, v2.2s
65
+ 0x20,0xa0,0x22,0x4e = smlsl2 v0.8h, v1.16b, v2.16b
66
+ 0x20,0xa0,0x62,0x4e = smlsl2 v0.4s, v1.8h, v2.8h
67
+ 0x20,0xa0,0xa2,0x4e = smlsl2 v0.2d, v1.4s, v2.4s
68
+ 0x20,0xa0,0x22,0x2e = umlsl v0.8h, v1.8b, v2.8b
69
+ 0x20,0xa0,0x62,0x2e = umlsl v0.4s, v1.4h, v2.4h
70
+ 0x20,0xa0,0xa2,0x2e = umlsl v0.2d, v1.2s, v2.2s
71
+ 0x20,0xa0,0x22,0x6e = umlsl2 v0.8h, v1.16b, v2.16b
72
+ 0x20,0xa0,0x62,0x6e = umlsl2 v0.4s, v1.8h, v2.8h
73
+ 0x20,0xa0,0xa2,0x6e = umlsl2 v0.2d, v1.4s, v2.4s
74
+ 0x20,0xc0,0x22,0x0e = smull v0.8h, v1.8b, v2.8b
75
+ 0x20,0xc0,0x62,0x0e = smull v0.4s, v1.4h, v2.4h
76
+ 0x20,0xc0,0xa2,0x0e = smull v0.2d, v1.2s, v2.2s
77
+ 0x20,0xc0,0x22,0x4e = smull2 v0.8h, v1.16b, v2.16b
78
+ 0x20,0xc0,0x62,0x4e = smull2 v0.4s, v1.8h, v2.8h
79
+ 0x20,0xc0,0xa2,0x4e = smull2 v0.2d, v1.4s, v2.4s
80
+ 0x20,0xc0,0x22,0x2e = umull v0.8h, v1.8b, v2.8b
81
+ 0x20,0xc0,0x62,0x2e = umull v0.4s, v1.4h, v2.4h
82
+ 0x20,0xc0,0xa2,0x2e = umull v0.2d, v1.2s, v2.2s
83
+ 0x20,0xc0,0x22,0x6e = umull2 v0.8h, v1.16b, v2.16b
84
+ 0x20,0xc0,0x62,0x6e = umull2 v0.4s, v1.8h, v2.8h
85
+ 0x20,0xc0,0xa2,0x6e = umull2 v0.2d, v1.4s, v2.4s
86
+ 0x20,0x90,0x62,0x0e = sqdmlal v0.4s, v1.4h, v2.4h
87
+ 0x20,0x90,0xa2,0x0e = sqdmlal v0.2d, v1.2s, v2.2s
88
+ 0x20,0x90,0x62,0x4e = sqdmlal2 v0.4s, v1.8h, v2.8h
89
+ 0x20,0x90,0xa2,0x4e = sqdmlal2 v0.2d, v1.4s, v2.4s
90
+ 0x20,0xb0,0x62,0x0e = sqdmlsl v0.4s, v1.4h, v2.4h
91
+ 0x20,0xb0,0xa2,0x0e = sqdmlsl v0.2d, v1.2s, v2.2s
92
+ 0x20,0xb0,0x62,0x4e = sqdmlsl2 v0.4s, v1.8h, v2.8h
93
+ 0x20,0xb0,0xa2,0x4e = sqdmlsl2 v0.2d, v1.4s, v2.4s
94
+ 0x20,0xd0,0x62,0x0e = sqdmull v0.4s, v1.4h, v2.4h
95
+ 0x20,0xd0,0xa2,0x0e = sqdmull v0.2d, v1.2s, v2.2s
96
+ 0x20,0xd0,0x62,0x4e = sqdmull2 v0.4s, v1.8h, v2.8h
97
+ 0x20,0xd0,0xa2,0x4e = sqdmull2 v0.2d, v1.4s, v2.4s
98
+ 0x20,0xe0,0x22,0x0e = pmull v0.8h, v1.8b, v2.8b
99
+ 0x20,0xe0,0xe2,0x0e = pmull v0.1q, v1.1d, v2.1d
100
+ 0x20,0xe0,0x22,0x4e = pmull2 v0.8h, v1.16b, v2.16b
101
+ 0x20,0xe0,0xe2,0x4e = pmull2 v0.1q, v1.2d, v2.2d
102
+ 0x20,0x10,0x22,0x0e = saddw v0.8h, v1.8h, v2.8b
103
+ 0x20,0x10,0x62,0x0e = saddw v0.4s, v1.4s, v2.4h
104
+ 0x20,0x10,0xa2,0x0e = saddw v0.2d, v1.2d, v2.2s
105
+ 0x20,0x10,0x22,0x4e = saddw2 v0.8h, v1.8h, v2.16b
106
+ 0x20,0x10,0x62,0x4e = saddw2 v0.4s, v1.4s, v2.8h
107
+ 0x20,0x10,0xa2,0x4e = saddw2 v0.2d, v1.2d, v2.4s
108
+ 0x20,0x10,0x22,0x2e = uaddw v0.8h, v1.8h, v2.8b
109
+ 0x20,0x10,0x62,0x2e = uaddw v0.4s, v1.4s, v2.4h
110
+ 0x20,0x10,0xa2,0x2e = uaddw v0.2d, v1.2d, v2.2s
111
+ 0x20,0x10,0x22,0x6e = uaddw2 v0.8h, v1.8h, v2.16b
112
+ 0x20,0x10,0x62,0x6e = uaddw2 v0.4s, v1.4s, v2.8h
113
+ 0x20,0x10,0xa2,0x6e = uaddw2 v0.2d, v1.2d, v2.4s
114
+ 0x20,0x30,0x22,0x0e = ssubw v0.8h, v1.8h, v2.8b
115
+ 0x20,0x30,0x62,0x0e = ssubw v0.4s, v1.4s, v2.4h
116
+ 0x20,0x30,0xa2,0x0e = ssubw v0.2d, v1.2d, v2.2s
117
+ 0x20,0x30,0x22,0x4e = ssubw2 v0.8h, v1.8h, v2.16b
118
+ 0x20,0x30,0x62,0x4e = ssubw2 v0.4s, v1.4s, v2.8h
119
+ 0x20,0x30,0xa2,0x4e = ssubw2 v0.2d, v1.2d, v2.4s
120
+ 0x20,0x30,0x22,0x2e = usubw v0.8h, v1.8h, v2.8b
121
+ 0x20,0x30,0x62,0x2e = usubw v0.4s, v1.4s, v2.4h
122
+ 0x20,0x30,0xa2,0x2e = usubw v0.2d, v1.2d, v2.2s
123
+ 0x20,0x30,0x22,0x6e = usubw2 v0.8h, v1.8h, v2.16b
124
+ 0x20,0x30,0x62,0x6e = usubw2 v0.4s, v1.4s, v2.8h
125
+ 0x20,0x30,0xa2,0x6e = usubw2 v0.2d, v1.2d, v2.4s
126
+ 0x20,0x40,0x22,0x0e = addhn v0.8b, v1.8h, v2.8h
127
+ 0x20,0x40,0x62,0x0e = addhn v0.4h, v1.4s, v2.4s
128
+ 0x20,0x40,0xa2,0x0e = addhn v0.2s, v1.2d, v2.2d
129
+ 0x20,0x40,0x22,0x4e = addhn2 v0.16b, v1.8h, v2.8h
130
+ 0x20,0x40,0x62,0x4e = addhn2 v0.8h, v1.4s, v2.4s
131
+ 0x20,0x40,0xa2,0x4e = addhn2 v0.4s, v1.2d, v2.2d
132
+ 0x20,0x40,0x22,0x2e = raddhn v0.8b, v1.8h, v2.8h
133
+ 0x20,0x40,0x62,0x2e = raddhn v0.4h, v1.4s, v2.4s
134
+ 0x20,0x40,0xa2,0x2e = raddhn v0.2s, v1.2d, v2.2d
135
+ 0x20,0x40,0x22,0x6e = raddhn2 v0.16b, v1.8h, v2.8h
136
+ 0x20,0x40,0x62,0x6e = raddhn2 v0.8h, v1.4s, v2.4s
137
+ 0x20,0x40,0xa2,0x6e = raddhn2 v0.4s, v1.2d, v2.2d
138
+ 0x20,0x60,0x22,0x2e = rsubhn v0.8b, v1.8h, v2.8h
139
+ 0x20,0x60,0x62,0x2e = rsubhn v0.4h, v1.4s, v2.4s
140
+ 0x20,0x60,0xa2,0x2e = rsubhn v0.2s, v1.2d, v2.2d
141
+ 0x20,0x60,0x22,0x6e = rsubhn2 v0.16b, v1.8h, v2.8h
142
+ 0x20,0x60,0x62,0x6e = rsubhn2 v0.8h, v1.4s, v2.4s
143
+ 0x20,0x60,0xa2,0x6e = rsubhn2 v0.4s, v1.2d, v2.2d
@@ -0,0 +1,28 @@
1
+ # CS_ARCH_ARM64, 0, None
2
+ 0x20,0x7c,0x22,0x2e = uaba v0.8b, v1.8b, v2.8b
3
+ 0x20,0x7c,0x22,0x6e = uaba v0.16b, v1.16b, v2.16b
4
+ 0x20,0x7c,0x62,0x2e = uaba v0.4h, v1.4h, v2.4h
5
+ 0x20,0x7c,0x62,0x6e = uaba v0.8h, v1.8h, v2.8h
6
+ 0x20,0x7c,0xa2,0x2e = uaba v0.2s, v1.2s, v2.2s
7
+ 0x20,0x7c,0xa2,0x6e = uaba v0.4s, v1.4s, v2.4s
8
+ 0x20,0x7c,0x22,0x0e = saba v0.8b, v1.8b, v2.8b
9
+ 0x20,0x7c,0x22,0x4e = saba v0.16b, v1.16b, v2.16b
10
+ 0x20,0x7c,0x62,0x0e = saba v0.4h, v1.4h, v2.4h
11
+ 0x20,0x7c,0x62,0x4e = saba v0.8h, v1.8h, v2.8h
12
+ 0x20,0x7c,0xa2,0x0e = saba v0.2s, v1.2s, v2.2s
13
+ 0x20,0x7c,0xa2,0x4e = saba v0.4s, v1.4s, v2.4s
14
+ 0x20,0x74,0x22,0x2e = uabd v0.8b, v1.8b, v2.8b
15
+ 0x20,0x74,0x22,0x6e = uabd v0.16b, v1.16b, v2.16b
16
+ 0x20,0x74,0x62,0x2e = uabd v0.4h, v1.4h, v2.4h
17
+ 0x20,0x74,0x62,0x6e = uabd v0.8h, v1.8h, v2.8h
18
+ 0x20,0x74,0xa2,0x2e = uabd v0.2s, v1.2s, v2.2s
19
+ 0x20,0x74,0xa2,0x6e = uabd v0.4s, v1.4s, v2.4s
20
+ 0x20,0x74,0x22,0x0e = sabd v0.8b, v1.8b, v2.8b
21
+ 0x20,0x74,0x22,0x4e = sabd v0.16b, v1.16b, v2.16b
22
+ 0x20,0x74,0x62,0x0e = sabd v0.4h, v1.4h, v2.4h
23
+ 0x20,0x74,0x62,0x4e = sabd v0.8h, v1.8h, v2.8h
24
+ 0x20,0x74,0xa2,0x0e = sabd v0.2s, v1.2s, v2.2s
25
+ 0x20,0x74,0xa2,0x4e = sabd v0.4s, v1.4s, v2.4s
26
+ 0x20,0xd4,0xa2,0x2e = fabd v0.2s, v1.2s, v2.2s
27
+ 0xff,0xd5,0xb0,0x6e = fabd v31.4s, v15.4s, v16.4s
28
+ 0x07,0xd5,0xf9,0x6e = fabd v7.2d, v8.2d, v25.2d
@@ -0,0 +1,40 @@
1
+ # CS_ARCH_ARM64, 0, None
2
+ 0x20,0x38,0x30,0x0e = saddlv h0, v1.8b
3
+ 0x20,0x38,0x30,0x4e = saddlv h0, v1.16b
4
+ 0x20,0x38,0x70,0x0e = saddlv s0, v1.4h
5
+ 0x20,0x38,0x70,0x4e = saddlv s0, v1.8h
6
+ 0x20,0x38,0xb0,0x4e = saddlv d0, v1.4s
7
+ 0x20,0x38,0x30,0x2e = uaddlv h0, v1.8b
8
+ 0x20,0x38,0x30,0x6e = uaddlv h0, v1.16b
9
+ 0x20,0x38,0x70,0x2e = uaddlv s0, v1.4h
10
+ 0x20,0x38,0x70,0x6e = uaddlv s0, v1.8h
11
+ 0x20,0x38,0xb0,0x6e = uaddlv d0, v1.4s
12
+ 0x20,0xa8,0x30,0x0e = smaxv b0, v1.8b
13
+ 0x20,0xa8,0x30,0x4e = smaxv b0, v1.16b
14
+ 0x20,0xa8,0x70,0x0e = smaxv h0, v1.4h
15
+ 0x20,0xa8,0x70,0x4e = smaxv h0, v1.8h
16
+ 0x20,0xa8,0xb0,0x4e = smaxv s0, v1.4s
17
+ 0x20,0xa8,0x31,0x0e = sminv b0, v1.8b
18
+ 0x20,0xa8,0x31,0x4e = sminv b0, v1.16b
19
+ 0x20,0xa8,0x71,0x0e = sminv h0, v1.4h
20
+ 0x20,0xa8,0x71,0x4e = sminv h0, v1.8h
21
+ 0x20,0xa8,0xb1,0x4e = sminv s0, v1.4s
22
+ 0x20,0xa8,0x30,0x2e = umaxv b0, v1.8b
23
+ 0x20,0xa8,0x30,0x6e = umaxv b0, v1.16b
24
+ 0x20,0xa8,0x70,0x2e = umaxv h0, v1.4h
25
+ 0x20,0xa8,0x70,0x6e = umaxv h0, v1.8h
26
+ 0x20,0xa8,0xb0,0x6e = umaxv s0, v1.4s
27
+ 0x20,0xa8,0x31,0x2e = uminv b0, v1.8b
28
+ 0x20,0xa8,0x31,0x6e = uminv b0, v1.16b
29
+ 0x20,0xa8,0x71,0x2e = uminv h0, v1.4h
30
+ 0x20,0xa8,0x71,0x6e = uminv h0, v1.8h
31
+ 0x20,0xa8,0xb1,0x6e = uminv s0, v1.4s
32
+ 0x20,0xb8,0x31,0x0e = addv b0, v1.8b
33
+ 0x20,0xb8,0x31,0x4e = addv b0, v1.16b
34
+ 0x20,0xb8,0x71,0x0e = addv h0, v1.4h
35
+ 0x20,0xb8,0x71,0x4e = addv h0, v1.8h
36
+ 0x20,0xb8,0xb1,0x4e = addv s0, v1.4s
37
+ 0x20,0xc8,0x30,0x6e = fmaxnmv s0, v1.4s
38
+ 0x20,0xc8,0xb0,0x6e = fminnmv s0, v1.4s
39
+ 0x20,0xf8,0x30,0x6e = fmaxv s0, v1.4s
40
+ 0x20,0xf8,0xb0,0x6e = fminv s0, v1.4s
@@ -0,0 +1,11 @@
1
+ # CS_ARCH_ARM64, 0, None
2
+ 0x20,0xbc,0x22,0x0e = addp v0.8b, v1.8b, v2.8b
3
+ 0x20,0xbc,0x22,0x4e = addp v0.16b, v1.16b, v2.16b
4
+ 0x20,0xbc,0x62,0x0e = addp v0.4h, v1.4h, v2.4h
5
+ 0x20,0xbc,0x62,0x4e = addp v0.8h, v1.8h, v2.8h
6
+ 0x20,0xbc,0xa2,0x0e = addp v0.2s, v1.2s, v2.2s
7
+ 0x20,0xbc,0xa2,0x4e = addp v0.4s, v1.4s, v2.4s
8
+ 0x20,0xbc,0xe2,0x4e = addp v0.2d, v1.2d, v2.2d
9
+ 0x20,0xd4,0x22,0x2e = faddp v0.2s, v1.2s, v2.2s
10
+ 0x20,0xd4,0x22,0x6e = faddp v0.4s, v1.4s, v2.4s
11
+ 0x20,0xd4,0x62,0x6e = faddp v0.2d, v1.2d, v2.2d