crabstone 3.0.3

data/test/MC/ARM/thumb2-pldw.s.cs

@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, 
+0xb0,0xf8,0x01,0xf1 = pldw [r0, #257]

data/test/MC/ARM/vfp4-thumb.s.cs

@@ -0,0 +1,13 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, 
+0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17
+0xa2,0xee,0x00,0x1a = vfma.f32 s2, s4, s0
+0x42,0xef,0xb1,0x0c = vfma.f32 d16, d18, d17
+0x08,0xef,0x50,0x4c = vfma.f32 q2, q4, q0
+0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17
+0x92,0xee,0x40,0x1a = vfnma.f32 s2, s4, s0
+0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17
+0xa2,0xee,0x40,0x1a = vfms.f32 s2, s4, s0
+0x62,0xef,0xb1,0x0c = vfms.f32 d16, d18, d17
+0x28,0xef,0x50,0x4c = vfms.f32 q2, q4, q0
+0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17
+0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0

data/test/MC/ARM/vfp4.s.cs

@@ -0,0 +1,13 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17
+0x00,0x1a,0xa2,0xee = vfma.f32 s2, s4, s0
+0xb1,0x0c,0x42,0xf2 = vfma.f32 d16, d18, d17
+0x50,0x4c,0x08,0xf2 = vfma.f32 q2, q4, q0
+0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17
+0x40,0x1a,0x92,0xee = vfnma.f32 s2, s4, s0
+0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17
+0x40,0x1a,0xa2,0xee = vfms.f32 s2, s4, s0
+0xb1,0x0c,0x62,0xf2 = vfms.f32 d16, d18, d17
+0x50,0x4c,0x28,0xf2 = vfms.f32 q2, q4, q0
+0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17
+0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0

data/test/MC/ARM/vpush-vpop-thumb.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, 
+0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12}
+0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12}
+0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12}
+0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12}
+0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12}
+0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12}
+0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12}
+0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12}

data/test/MC/ARM/vpush-vpop.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12}
+0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12}
+0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12}
+0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12}
+0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12}
+0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12}
+0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12}
+0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12}

data/test/MC/Mips/hilo-addressing.s.cs

@@ -0,0 +1,4 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
+0x3c,0x04,0xde,0xae = lui $4, %hi(addr)
+0x03,0xe0,0x00,0x08 = jr $31
+0x80,0x82,0xbe,0xef = lb $2, %lo(addr)($4)

data/test/MC/Mips/micromips-alu-instructions-EB.s.cs

@@ -0,0 +1,33 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None
+0x00,0xe6,0x49,0x10 = add $9, $6, $7
+0x11,0x26,0x45,0x67 = addi $9, $6, 17767
+0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001
+0x11,0x26,0x45,0x67 = addi $9, $6, 17767
+0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001
+0x00,0xe6,0x49,0x50 = addu $9, $6, $7
+0x00,0xe6,0x49,0x90 = sub $9, $6, $7
+0x00,0xa3,0x21,0xd0 = subu $4, $3, $5
+0x00,0xe0,0x31,0x90 = neg $6, $7
+0x00,0xe0,0x31,0xd0 = negu $6, $7
+0x00,0x08,0x39,0x50 = move $7, $8
+0x00,0xa3,0x1b,0x50 = slt $3, $3, $5
+0x90,0x63,0x00,0x67 = slti $3, $3, 103
+0x90,0x63,0x00,0x67 = slti $3, $3, 103
+0xb0,0x63,0x00,0x67 = sltiu $3, $3, 103
+0x00,0xa3,0x1b,0x90 = sltu $3, $3, $5
+0x41,0xa9,0x45,0x67 = lui $9, 17767
+0x00,0xe6,0x4a,0x50 = and $9, $6, $7
+0xd1,0x26,0x45,0x67 = andi $9, $6, 17767
+0xd1,0x26,0x45,0x67 = andi $9, $6, 17767
+0x00,0xa4,0x1a,0x90 = or $3, $4, $5
+0x51,0x26,0x45,0x67 = ori $9, $6, 17767
+0x00,0xa3,0x1b,0x10 = xor $3, $3, $5
+0x71,0x26,0x45,0x67 = xori $9, $6, 17767
+0x71,0x26,0x45,0x67 = xori $9, $6, 17767
+0x00,0xe6,0x4a,0xd0 = nor $9, $6, $7
+0x00,0x08,0x3a,0xd0 = not $7, $8
+0x00,0xe6,0x4a,0x10 = mul $9, $6, $7
+0x00,0xe9,0x8b,0x3c = mult $9, $7
+0x00,0xe9,0x9b,0x3c = multu $9, $7
+0x00,0xe9,0xab,0x3c = div $zero, $9, $7
+0x00,0xe9,0xbb,0x3c = divu $zero, $9, $7

data/test/MC/Mips/micromips-alu-instructions.s.cs

@@ -0,0 +1,33 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0xe6,0x00,0x10,0x49 = add $9, $6, $7
+0x26,0x11,0x67,0x45 = addi $9, $6, 17767
+0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001
+0x26,0x11,0x67,0x45 = addi $9, $6, 17767
+0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001
+0xe6,0x00,0x50,0x49 = addu $9, $6, $7
+0xe6,0x00,0x90,0x49 = sub $9, $6, $7
+0xa3,0x00,0xd0,0x21 = subu $4, $3, $5
+0xe0,0x00,0x90,0x31 = neg $6, $7
+0xe0,0x00,0xd0,0x31 = negu $6, $7
+0x08,0x00,0x50,0x39 = move $7, $8
+0xa3,0x00,0x50,0x1b = slt $3, $3, $5
+0x63,0x90,0x67,0x00 = slti $3, $3, 103
+0x63,0x90,0x67,0x00 = slti $3, $3, 103
+0x63,0xb0,0x67,0x00 = sltiu $3, $3, 103
+0xa3,0x00,0x90,0x1b = sltu $3, $3, $5
+0xa9,0x41,0x67,0x45 = lui $9, 17767
+0xe6,0x00,0x50,0x4a = and $9, $6, $7
+0x26,0xd1,0x67,0x45 = andi $9, $6, 17767
+0x26,0xd1,0x67,0x45 = andi $9, $6, 17767
+0xa4,0x00,0x90,0x1a = or $3, $4, $5
+0x26,0x51,0x67,0x45 = ori $9, $6, 17767
+0xa3,0x00,0x10,0x1b = xor $3, $3, $5
+0x26,0x71,0x67,0x45 = xori $9, $6, 17767
+0x26,0x71,0x67,0x45 = xori $9, $6, 17767
+0xe6,0x00,0xd0,0x4a = nor $9, $6, $7
+0x08,0x00,0xd0,0x3a = not $7, $8
+0xe6,0x00,0x10,0x4a = mul $9, $6, $7
+0xe9,0x00,0x3c,0x8b = mult $9, $7
+0xe9,0x00,0x3c,0x9b = multu $9, $7
+0xe9,0x00,0x3c,0xab = div $zero, $9, $7
+0xe9,0x00,0x3c,0xbb = divu $zero, $9, $7

data/test/MC/Mips/micromips-branch-instructions-EB.s.cs

@@ -0,0 +1,11 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0x94,0x00,0x02,0x9a = b 1332
+0x94,0xc9,0x02,0x9a = beq $9, $6, 1332
+0x40,0x46,0x02,0x9a = bgez $6, 1332
+0x40,0x66,0x02,0x9a = bgezal $6, 1332
+0x40,0x26,0x02,0x9a = bltzal $6, 1332
+0x40,0xc6,0x02,0x9a = bgtz $6, 1332
+0x40,0x86,0x02,0x9a = blez $6, 1332
+0xb4,0xc9,0x02,0x9a = bne $9, $6, 1332
+0x40,0x60,0x02,0x9a = bal 1332
+0x40,0x06,0x02,0x9a = bltz $6, 1332

data/test/MC/Mips/micromips-branch-instructions.s.cs

@@ -0,0 +1,11 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0x00,0x94,0x9a,0x02 = b 1332
+0xc9,0x94,0x9a,0x02 = beq $9, $6, 1332
+0x46,0x40,0x9a,0x02 = bgez $6, 1332
+0x66,0x40,0x9a,0x02 = bgezal $6, 1332
+0x26,0x40,0x9a,0x02 = bltzal $6, 1332
+0xc6,0x40,0x9a,0x02 = bgtz $6, 1332
+0x86,0x40,0x9a,0x02 = blez $6, 1332
+0xc9,0xb4,0x9a,0x02 = bne $9, $6, 1332
+0x60,0x40,0x9a,0x02 = bal 1332
+0x06,0x40,0x9a,0x02 = bltz $6, 1332

data/test/MC/Mips/micromips-expansions.s.cs

@@ -0,0 +1,20 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0xa0,0x50,0x7b,0x00 = ori $5, $zero, 123
+0xc0,0x30,0xd7,0xf6 = addiu $6, $zero, -2345
+0xa7,0x41,0x01,0x00 = lui $7, 1
+0xe7,0x50,0x02,0x00 = ori $7, $7, 2
+0x80,0x30,0x14,0x00 = addiu $4, $zero, 20
+0xa7,0x41,0x01,0x00 = lui $7, 1
+0xe7,0x50,0x02,0x00 = ori $7, $7, 2
+0x85,0x30,0x14,0x00 = addiu $4, $5, 20
+0xa7,0x41,0x01,0x00 = lui $7, 1
+0xe7,0x50,0x02,0x00 = ori $7, $7, 2
+0x07,0x01,0x50,0x39 = addu $7, $7, $8
+0x8a,0x00,0x50,0x51 = addu $10, $10, $4
+0x21,0x01,0x50,0x09 = addu $1, $1, $9
+0xaa,0x41,0x0a,0x00 = lui $10, 10
+0x8a,0x00,0x50,0x51 = addu $10, $10, $4
+0x4a,0xfd,0x7b,0x00 = lw $10, 123($10)
+0xa1,0x41,0x02,0x00 = lui $1, 2
+0x21,0x01,0x50,0x09 = addu $1, $1, $9
+0x41,0xf9,0x40,0xe2 = sw $10, 57920($1)

data/test/MC/Mips/micromips-jump-instructions-EB.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0xd4,0x00,0x02,0x98 = j 1328
+0xf4,0x00,0x02,0x98 = jal 1328
+0x03,0xe6,0x0f,0x3c = jalr $6
+0x00,0x07,0x0f,0x3c = jr $7

data/test/MC/Mips/micromips-jump-instructions.s.cs

@@ -0,0 +1,6 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0x00,0xd4,0x98,0x02 = j 1328
+0x00,0xf4,0x98,0x02 = jal 1328
+0xe6,0x03,0x3c,0x0f = jalr $6
+0x07,0x00,0x3c,0x0f = jr $7
+0x07,0x00,0x3c,0x0f = jr $7

data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0x1c,0xa4,0x00,0x08 = lb $5, 8($4)
+0x14,0xc4,0x00,0x08 = lbu $6, 8($4)
+0x3c,0x44,0x00,0x08 = lh $2, 8($4)
+0x34,0x82,0x00,0x08 = lhu $4, 8($2)
+0xfc,0xc5,0x00,0x04 = lw $6, 4($5)
+0x18,0xa4,0x00,0x08 = sb $5, 8($4)
+0x38,0x44,0x00,0x08 = sh $2, 8($4)
+0xf8,0xa6,0x00,0x04 = sw $5, 4($6)

data/test/MC/Mips/micromips-loadstore-instructions.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0xa4,0x1c,0x08,0x00 = lb $5, 8($4)
+0xc4,0x14,0x08,0x00 = lbu $6, 8($4)
+0x44,0x3c,0x08,0x00 = lh $2, 8($4)
+0x82,0x34,0x08,0x00 = lhu $4, 8($2)
+0xc5,0xfc,0x04,0x00 = lw $6, 4($5)
+0xa4,0x18,0x08,0x00 = sb $5, 8($4)
+0x44,0x38,0x08,0x00 = sh $2, 8($4)
+0xa6,0xf8,0x04,0x00 = sw $5, 4($6)

data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0x60,0x85,0x00,0x10 = lwl $4, 16($5)
+0x60,0x85,0x10,0x10 = lwr $4, 16($5)
+0x60,0x85,0x80,0x10 = swl $4, 16($5)
+0x60,0x85,0x90,0x10 = swr $4, 16($5)

data/test/MC/Mips/micromips-loadstore-unaligned.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0x85,0x60,0x10,0x00 = lwl $4, 16($5)
+0x85,0x60,0x10,0x10 = lwr $4, 16($5)
+0x85,0x60,0x10,0x80 = swl $4, 16($5)
+0x85,0x60,0x10,0x90 = swr $4, 16($5)

data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0x00,0xe6,0x48,0x58 = movz $9, $6, $7
+0x00,0xe6,0x48,0x18 = movn $9, $6, $7
+0x55,0x26,0x09,0x7b = movt $9, $6, $fcc0
+0x55,0x26,0x01,0x7b = movf $9, $6, $fcc0

data/test/MC/Mips/micromips-movcond-instructions.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0xe6,0x00,0x58,0x48 = movz $9, $6, $7
+0xe6,0x00,0x18,0x48 = movn $9, $6, $7
+0x26,0x55,0x7b,0x09 = movt $9, $6, $fcc0
+0x26,0x55,0x7b,0x01 = movf $9, $6, $fcc0

data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0x00,0xa4,0xcb,0x3c = madd $4, $5
+0x00,0xa4,0xdb,0x3c = maddu $4, $5
+0x00,0xa4,0xeb,0x3c = msub $4, $5
+0x00,0xa4,0xfb,0x3c = msubu $4, $5

data/test/MC/Mips/micromips-multiply-instructions.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0xa4,0x00,0x3c,0xcb = madd $4, $5
+0xa4,0x00,0x3c,0xdb = maddu $4, $5
+0xa4,0x00,0x3c,0xeb = msub $4, $5
+0xa4,0x00,0x3c,0xfb = msubu $4, $5

data/test/MC/Mips/micromips-shift-instructions-EB.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0x00,0x83,0x38,0x00 = sll $4, $3, 7
+0x00,0x65,0x10,0x10 = sllv $2, $3, $5
+0x00,0x83,0x38,0x80 = sra $4, $3, 7
+0x00,0x65,0x10,0x90 = srav $2, $3, $5
+0x00,0x83,0x38,0x40 = srl $4, $3, 7
+0x00,0x65,0x10,0x50 = srlv $2, $3, $5
+0x01,0x26,0x38,0xc0 = rotr $9, $6, 7
+0x00,0xc7,0x48,0xd0 = rotrv $9, $6, $7

data/test/MC/Mips/micromips-shift-instructions.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0x83,0x00,0x00,0x38 = sll $4, $3, 7
+0x65,0x00,0x10,0x10 = sllv $2, $3, $5
+0x83,0x00,0x80,0x38 = sra $4, $3, 7
+0x65,0x00,0x90,0x10 = srav $2, $3, $5
+0x83,0x00,0x40,0x38 = srl $4, $3, 7
+0x65,0x00,0x50,0x10 = srlv $2, $3, $5
+0x26,0x01,0xc0,0x38 = rotr $9, $6, 7
+0xc7,0x00,0xd0,0x48 = rotrv $9, $6, $7

data/test/MC/Mips/micromips-trap-instructions-EB.s.cs

@@ -0,0 +1,13 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
+0x01,0x28,0x00,0x3c = teq $8, $9
+0x01,0x28,0x02,0x3c = tge $8, $9
+0x01,0x28,0x04,0x3c = tgeu $8, $9
+0x01,0x28,0x08,0x3c = tlt $8, $9
+0x01,0x28,0x0a,0x3c = tltu $8, $9
+0x01,0x28,0x0c,0x3c = tne $8, $9
+0x41,0xc9,0x45,0x67 = teqi $9, 17767
+0x41,0x29,0x45,0x67 = tgei $9, 17767
+0x41,0x69,0x45,0x67 = tgeiu $9, 17767
+0x41,0x09,0x45,0x67 = tlti $9, 17767
+0x41,0x49,0x45,0x67 = tltiu $9, 17767
+0x41,0x89,0x45,0x67 = tnei $9, 17767

data/test/MC/Mips/micromips-trap-instructions.s.cs

@@ -0,0 +1,13 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
+0x28,0x01,0x3c,0x00 = teq $8, $9
+0x28,0x01,0x3c,0x02 = tge $8, $9
+0x28,0x01,0x3c,0x04 = tgeu $8, $9
+0x28,0x01,0x3c,0x08 = tlt $8, $9
+0x28,0x01,0x3c,0x0a = tltu $8, $9
+0x28,0x01,0x3c,0x0c = tne $8, $9
+0xc9,0x41,0x67,0x45 = teqi $9, 17767
+0x29,0x41,0x67,0x45 = tgei $9, 17767
+0x69,0x41,0x67,0x45 = tgeiu $9, 17767
+0x09,0x41,0x67,0x45 = tlti $9, 17767
+0x49,0x41,0x67,0x45 = tltiu $9, 17767
+0x89,0x41,0x67,0x45 = tnei $9, 17767

data/test/MC/Mips/mips-alu-instructions.s.cs

@@ -0,0 +1,53 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32, None
+0x24,0x48,0xc7,0x00 = and $9, $6, $7
+0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
+0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
+0x67,0x45,0x29,0x31 = andi $9, $9, 17767
+0x21,0x30,0xe6,0x70 = clo $6, $7
+0x20,0x30,0xe6,0x70 = clz $6, $7
+0x84,0x61,0x33,0x7d = ins $19, $9, 6, 7
+0x27,0x48,0xc7,0x00 = nor $9, $6, $7
+0x25,0x18,0x65,0x00 = or $3, $3, $5
+0x67,0x45,0xa4,0x34 = ori $4, $5, 17767
+0x67,0x45,0xc9,0x34 = ori $9, $6, 17767
+0x80,0x00,0x6b,0x35 = ori $11, $11, 128
+0xc2,0x49,0x26,0x00 = rotr $9, $6, 7
+0x46,0x48,0xe6,0x00 = rotrv $9, $6, $7
+0xc0,0x21,0x03,0x00 = sll $4, $3, 7
+0x04,0x10,0xa3,0x00 = sllv $2, $3, $5
+0x2a,0x18,0x65,0x00 = slt $3, $3, $5
+0x67,0x00,0x63,0x28 = slti $3, $3, 103
+0x67,0x00,0x63,0x28 = slti $3, $3, 103
+0x67,0x00,0x63,0x2c = sltiu $3, $3, 103
+0x2b,0x18,0x65,0x00 = sltu $3, $3, $5
+0xc3,0x21,0x03,0x00 = sra $4, $3, 7
+0x07,0x10,0xa3,0x00 = srav $2, $3, $5
+0xc2,0x21,0x03,0x00 = srl $4, $3, 7
+0x06,0x10,0xa3,0x00 = srlv $2, $3, $5
+0x26,0x18,0x65,0x00 = xor $3, $3, $5
+0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
+0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
+0x0c,0x00,0x6b,0x39 = xori $11, $11, 12
+0xa0,0x30,0x07,0x7c = wsbh $6, $7
+0x27,0x38,0x00,0x01 = not $7, $8
+0x20,0x48,0xc7,0x00 = add $9, $6, $7
+0x67,0x45,0xc9,0x20 = addi $9, $6, 17767
+0x67,0xc5,0xc9,0x24 = addiu $9, $6, -15001
+0x67,0x45,0xc9,0x20 = addi $9, $6, 17767
+0x67,0x45,0x29,0x21 = addi $9, $9, 17767
+0x67,0xc5,0xc9,0x24 = addiu $9, $6, -15001
+0x28,0x00,0x6b,0x25 = addiu $11, $11, 40
+0x21,0x48,0xc7,0x00 = addu $9, $6, $7
+0x00,0x00,0xc7,0x70 = madd $6, $7
+0x01,0x00,0xc7,0x70 = maddu $6, $7
+0x04,0x00,0xc7,0x70 = msub $6, $7
+0x05,0x00,0xc7,0x70 = msubu $6, $7
+0x18,0x00,0x65,0x00 = mult $3, $5
+0x19,0x00,0x65,0x00 = multu $3, $5
+0x22,0x48,0xc7,0x00 = sub $9, $6, $7
+0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56
+0x23,0x20,0x65,0x00 = subu $4, $3, $5
+0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40
+0x22,0x30,0x07,0x00 = neg $6, $7
+0x23,0x30,0x07,0x00 = negu $6, $7
+0x21,0x38,0x00,0x01 = move $7, $8

data/test/MC/Mips/mips-control-instructions-64.s.cs

@@ -0,0 +1,33 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
+0x00,0x00,0x00,0x0d = break 
+0x00,0x07,0x00,0x0d = break 7, 0
+0x00,0x07,0x01,0x4d = break 7, 5
+0x00,0x00,0x00,0x0c = syscall 
+0x00,0x0d,0x15,0x0c = syscall 13396
+0x42,0x00,0x00,0x18 = eret 
+0x42,0x00,0x00,0x1f = deret 
+0x41,0x60,0x60,0x00 = di 
+0x41,0x60,0x60,0x00 = di 
+0x41,0x6a,0x60,0x00 = di $10
+0x41,0x60,0x60,0x20 = ei 
+0x41,0x60,0x60,0x20 = ei 
+0x41,0x6a,0x60,0x20 = ei $10
+0x42,0x00,0x00,0x20 = wait 
+0x00,0x03,0x00,0x34 = teq $zero, $3
+0x00,0x03,0x00,0x74 = teq $zero, $3, 1
+0x04,0x6c,0x00,0x01 = teqi $3, 1
+0x00,0x03,0x00,0x30 = tge $zero, $3
+0x00,0x03,0x00,0xf0 = tge $zero, $3, 3
+0x04,0x68,0x00,0x03 = tgei $3, 3
+0x00,0x03,0x00,0x31 = tgeu $zero, $3
+0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7
+0x04,0x69,0x00,0x07 = tgeiu $3, 7
+0x00,0x03,0x00,0x32 = tlt $zero, $3
+0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
+0x04,0x6a,0x00,0x1f = tlti $3, 31
+0x00,0x03,0x00,0x33 = tltu $zero, $3
+0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255
+0x04,0x6b,0x00,0xff = tltiu $3, 255
+0x00,0x03,0x00,0x36 = tne $zero, $3
+0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
+0x04,0x6e,0x03,0xff = tnei $3, 1023

data/test/MC/Mips/mips-control-instructions.s.cs

@@ -0,0 +1,33 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
+0x00,0x00,0x00,0x0d = break 
+0x00,0x07,0x00,0x0d = break 7, 0
+0x00,0x07,0x01,0x4d = break 7, 5
+0x00,0x00,0x00,0x0c = syscall 
+0x00,0x0d,0x15,0x0c = syscall 13396
+0x42,0x00,0x00,0x18 = eret 
+0x42,0x00,0x00,0x1f = deret 
+0x41,0x60,0x60,0x00 = di 
+0x41,0x60,0x60,0x00 = di 
+0x41,0x6a,0x60,0x00 = di $10
+0x41,0x60,0x60,0x20 = ei 
+0x41,0x60,0x60,0x20 = ei 
+0x41,0x6a,0x60,0x20 = ei $10
+0x42,0x00,0x00,0x20 = wait 
+0x00,0x03,0x00,0x34 = teq $zero, $3
+0x00,0x03,0x00,0x74 = teq $zero, $3, 1
+0x04,0x6c,0x00,0x01 = teqi $3, 1
+0x00,0x03,0x00,0x30 = tge $zero, $3
+0x00,0x03,0x00,0xf0 = tge $zero, $3, 3
+0x04,0x68,0x00,0x03 = tgei $3, 3
+0x00,0x03,0x00,0x31 = tgeu $zero, $3
+0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7
+0x04,0x69,0x00,0x07 = tgeiu $3, 7
+0x00,0x03,0x00,0x32 = tlt $zero, $3
+0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
+0x04,0x6a,0x00,0x1f = tlti $3, 31
+0x00,0x03,0x00,0x33 = tltu $zero, $3
+0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255
+0x04,0x6b,0x00,0xff = tltiu $3, 255
+0x00,0x03,0x00,0x36 = tne $zero, $3
+0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
+0x04,0x6e,0x03,0xff = tnei $3, 1023

data/test/MC/Mips/mips-coprocessor-encodings.s.cs

@@ -0,0 +1,17 @@
+# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
+0x40,0xac,0x80,0x02 = dmtc0 $12, $16, 2
+0x40,0xac,0x80,0x00 = dmtc0 $12, $16, 0
+0x40,0x8c,0x80,0x02 = mtc0 $12, $16, 2
+0x40,0x8c,0x80,0x00 = mtc0 $12, $16, 0
+0x40,0x2c,0x80,0x02 = dmfc0 $12, $16, 2
+0x40,0x2c,0x80,0x00 = dmfc0 $12, $16, 0
+0x40,0x0c,0x80,0x02 = mfc0 $12, $16, 2
+0x40,0x0c,0x80,0x00 = mfc0 $12, $16, 0
+0x48,0xac,0x80,0x02 = dmtc2 $12, $16, 2
+0x48,0xac,0x80,0x00 = dmtc2 $12, $16, 0
+0x48,0x8c,0x80,0x02 = mtc2 $12, $16, 2
+0x48,0x8c,0x80,0x00 = mtc2 $12, $16, 0
+0x48,0x2c,0x80,0x02 = dmfc2 $12, $16, 2
+0x48,0x2c,0x80,0x00 = dmfc2 $12, $16, 0
+0x48,0x0c,0x80,0x02 = mfc2 $12, $16, 2
+0x48,0x0c,0x80,0x00 = mfc2 $12, $16, 0