RubyGems - crabstone - Versions diffs - 3.0.3 - Mend

crabstone 3.0.3

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.

Files changed (302) hide show

checksums.yaml +7 -0
data/CHANGES.md +61 -0
data/LICENSE +25 -0
data/MANIFEST +312 -0
data/README.md +103 -0
data/Rakefile +27 -0
data/bin/genconst +66 -0
data/bin/genreg +99 -0
data/crabstone.gemspec +27 -0
data/examples/hello_world.rb +43 -0
data/lib/arch/arm.rb +128 -0
data/lib/arch/arm64.rb +167 -0
data/lib/arch/arm64_const.rb +1055 -0
data/lib/arch/arm64_registers.rb +295 -0
data/lib/arch/arm_const.rb +777 -0
data/lib/arch/arm_registers.rb +149 -0
data/lib/arch/mips.rb +78 -0
data/lib/arch/mips_const.rb +850 -0
data/lib/arch/mips_registers.rb +208 -0
data/lib/arch/ppc.rb +90 -0
data/lib/arch/ppc_const.rb +1181 -0
data/lib/arch/ppc_registers.rb +209 -0
data/lib/arch/sparc.rb +79 -0
data/lib/arch/sparc_const.rb +461 -0
data/lib/arch/sparc_registers.rb +121 -0
data/lib/arch/systemz.rb +79 -0
data/lib/arch/sysz_const.rb +779 -0
data/lib/arch/sysz_registers.rb +66 -0
data/lib/arch/x86.rb +107 -0
data/lib/arch/x86_const.rb +1698 -0
data/lib/arch/x86_registers.rb +265 -0
data/lib/arch/xcore.rb +78 -0
data/lib/arch/xcore_const.rb +185 -0
data/lib/arch/xcore_registers.rb +57 -0
data/lib/crabstone.rb +564 -0
data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
data/test/MC/AArch64/neon-2velem.s.cs +113 -0
data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
data/test/MC/AArch64/neon-across.s.cs +40 -0
data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
data/test/MC/AArch64/neon-crypto.s.cs +15 -0
data/test/MC/AArch64/neon-extract.s.cs +3 -0
data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
data/test/MC/AArch64/neon-max-min.s.cs +37 -0
data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
data/test/MC/AArch64/neon-mov.s.cs +74 -0
data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
data/test/MC/AArch64/neon-perm.s.cs +43 -0
data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
data/test/MC/AArch64/neon-shift.s.cs +22 -0
data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
data/test/MC/AArch64/neon-tbl.s.cs +21 -0
data/test/MC/AArch64/trace-regs.s.cs +383 -0
data/test/MC/ARM/arm-aliases.s.cs +7 -0
data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
data/test/MC/ARM/arm-it-block.s.cs +2 -0
data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
data/test/MC/ARM/arm-trustzone.s.cs +3 -0
data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
data/test/MC/ARM/arm_instructions.s.cs +25 -0
data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
data/test/MC/ARM/crc32-thumb.s.cs +7 -0
data/test/MC/ARM/crc32.s.cs +7 -0
data/test/MC/ARM/dot-req.s.cs +3 -0
data/test/MC/ARM/fp-armv8.s.cs +52 -0
data/test/MC/ARM/idiv-thumb.s.cs +3 -0
data/test/MC/ARM/idiv.s.cs +3 -0
data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
data/test/MC/ARM/mode-switch.s.cs +7 -0
data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
data/test/MC/ARM/neon-crypto.s.cs +16 -0
data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
data/test/MC/ARM/neon-v8.s.cs +38 -0
data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
data/test/MC/ARM/neon-vswp.s.cs +3 -0
data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
data/test/MC/ARM/thumb-hints.s.cs +12 -0
data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
data/test/MC/ARM/thumb.s.cs +19 -0
data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
data/test/MC/ARM/thumb2-branches.s.cs +85 -0
data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
data/test/MC/ARM/vfp4.s.cs +13 -0
data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
data/test/MC/ARM/vpush-vpop.s.cs +9 -0
data/test/MC/Mips/hilo-addressing.s.cs +4 -0
data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
data/test/MC/Mips/micromips-expansions.s.cs +20 -0
data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
data/test/MC/Mips/mips-expansions.s.cs +20 -0
data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
data/test/MC/Mips/mips-register-names.s.cs +33 -0
data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
data/test/MC/Mips/mips64-instructions.s.cs +3 -0
data/test/MC/Mips/mips64-register-names.s.cs +33 -0
data/test/MC/Mips/mips_directives.s.cs +12 -0
data/test/MC/Mips/nabi-regs.s.cs +12 -0
data/test/MC/Mips/set-at-directive.s.cs +6 -0
data/test/MC/Mips/test_2r.s.cs +16 -0
data/test/MC/Mips/test_2rf.s.cs +33 -0
data/test/MC/Mips/test_3r.s.cs +243 -0
data/test/MC/Mips/test_3rf.s.cs +83 -0
data/test/MC/Mips/test_bit.s.cs +49 -0
data/test/MC/Mips/test_cbranch.s.cs +11 -0
data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
data/test/MC/Mips/test_elm.s.cs +16 -0
data/test/MC/Mips/test_elm_insert.s.cs +4 -0
data/test/MC/Mips/test_elm_insve.s.cs +5 -0
data/test/MC/Mips/test_i10.s.cs +5 -0
data/test/MC/Mips/test_i5.s.cs +45 -0
data/test/MC/Mips/test_i8.s.cs +11 -0
data/test/MC/Mips/test_lsa.s.cs +5 -0
data/test/MC/Mips/test_mi10.s.cs +24 -0
data/test/MC/Mips/test_vec.s.cs +8 -0
data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
data/test/MC/README +6 -0
data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
data/test/MC/Sparc/sparc-vis.s.cs +2 -0
data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
data/test/MC/SystemZ/insn-good.s.cs +2265 -0
data/test/MC/SystemZ/regs-good.s.cs +45 -0
data/test/MC/X86/3DNow.s.cs +29 -0
data/test/MC/X86/address-size.s.cs +5 -0
data/test/MC/X86/avx512-encodings.s.cs +12 -0
data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
data/test/MC/X86/x86-32-avx.s.cs +833 -0
data/test/MC/X86/x86-32-fma3.s.cs +169 -0
data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
data/test/MC/X86/x86_64-encoding.s.cs +59 -0
data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
data/test/README +6 -0
data/test/test.rb +205 -0
data/test/test.rb.SPEC +235 -0
data/test/test_arm.rb +202 -0
data/test/test_arm.rb.SPEC +275 -0
data/test/test_arm64.rb +150 -0
data/test/test_arm64.rb.SPEC +116 -0
data/test/test_detail.rb +228 -0
data/test/test_detail.rb.SPEC +322 -0
data/test/test_exhaustive.rb +80 -0
data/test/test_mips.rb +118 -0
data/test/test_mips.rb.SPEC +91 -0
data/test/test_ppc.rb +137 -0
data/test/test_ppc.rb.SPEC +84 -0
data/test/test_sanity.rb +83 -0
data/test/test_skipdata.rb +111 -0
data/test/test_skipdata.rb.SPEC +58 -0
data/test/test_sparc.rb +113 -0
data/test/test_sparc.rb.SPEC +116 -0
data/test/test_sysz.rb +111 -0
data/test/test_sysz.rb.SPEC +61 -0
data/test/test_x86.rb +189 -0
data/test/test_x86.rb.SPEC +579 -0
data/test/test_xcore.rb +100 -0
data/test/test_xcore.rb.SPEC +75 -0
metadata +393 -0

data/test/MC/ARM/neon-cmp-encoding.s.cs ADDED

@@ -0,0 +1,88 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17
+0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17
+0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17
+0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17
+0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9
+0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9
+0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9
+0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9
+0xb1,0x03,0x40,0xf2 = vcge.s8 d16, d16, d17
+0xb1,0x03,0x50,0xf2 = vcge.s16 d16, d16, d17
+0xb1,0x03,0x60,0xf2 = vcge.s32 d16, d16, d17
+0xb1,0x03,0x40,0xf3 = vcge.u8 d16, d16, d17
+0xb1,0x03,0x50,0xf3 = vcge.u16 d16, d16, d17
+0xb1,0x03,0x60,0xf3 = vcge.u32 d16, d16, d17
+0xa1,0x0e,0x40,0xf3 = vcge.f32 d16, d16, d17
+0xf2,0x03,0x40,0xf2 = vcge.s8 q8, q8, q9
+0xf2,0x03,0x50,0xf2 = vcge.s16 q8, q8, q9
+0xf2,0x03,0x60,0xf2 = vcge.s32 q8, q8, q9
+0xf2,0x03,0x40,0xf3 = vcge.u8 q8, q8, q9
+0xf2,0x03,0x50,0xf3 = vcge.u16 q8, q8, q9
+0xf2,0x03,0x60,0xf3 = vcge.u32 q8, q8, q9
+0xe2,0x0e,0x40,0xf3 = vcge.f32 q8, q8, q9
+0xb1,0x0e,0x40,0xf3 = vacge.f32 d16, d16, d17
+0xf2,0x0e,0x40,0xf3 = vacge.f32 q8, q8, q9
+0xa1,0x03,0x40,0xf2 = vcgt.s8 d16, d16, d17
+0xa1,0x03,0x50,0xf2 = vcgt.s16 d16, d16, d17
+0xa1,0x03,0x60,0xf2 = vcgt.s32 d16, d16, d17
+0xa1,0x03,0x40,0xf3 = vcgt.u8 d16, d16, d17
+0xa1,0x03,0x50,0xf3 = vcgt.u16 d16, d16, d17
+0xa1,0x03,0x60,0xf3 = vcgt.u32 d16, d16, d17
+0xa1,0x0e,0x60,0xf3 = vcgt.f32 d16, d16, d17
+0xe2,0x03,0x40,0xf2 = vcgt.s8 q8, q8, q9
+0xe2,0x03,0x50,0xf2 = vcgt.s16 q8, q8, q9
+0xe2,0x03,0x60,0xf2 = vcgt.s32 q8, q8, q9
+0xe2,0x03,0x40,0xf3 = vcgt.u8 q8, q8, q9
+0xe2,0x03,0x50,0xf3 = vcgt.u16 q8, q8, q9
+0xe2,0x03,0x60,0xf3 = vcgt.u32 q8, q8, q9
+0xe2,0x0e,0x60,0xf3 = vcgt.f32 q8, q8, q9
+0xb1,0x0e,0x60,0xf3 = vacgt.f32 d16, d16, d17
+0xf2,0x0e,0x60,0xf3 = vacgt.f32 q8, q8, q9
+0xb1,0x08,0x40,0xf2 = vtst.8 d16, d16, d17
+0xb1,0x08,0x50,0xf2 = vtst.16 d16, d16, d17
+0xb1,0x08,0x60,0xf2 = vtst.32 d16, d16, d17
+0xf2,0x08,0x40,0xf2 = vtst.8 q8, q8, q9
+0xf2,0x08,0x50,0xf2 = vtst.16 q8, q8, q9
+0xf2,0x08,0x60,0xf2 = vtst.32 q8, q8, q9
+0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0
+0xa0,0x00,0xf1,0xf3 = vcge.s8 d16, d16, #0
+0xa0,0x01,0xf1,0xf3 = vcle.s8 d16, d16, #0
+0x20,0x00,0xf1,0xf3 = vcgt.s8 d16, d16, #0
+0x20,0x02,0xf1,0xf3 = vclt.s8 d16, d16, #0
+0x6a,0x83,0x46,0xf2 = vcgt.s8 q12, q3, q13
+0x6a,0x83,0x56,0xf2 = vcgt.s16 q12, q3, q13
+0x6a,0x83,0x66,0xf2 = vcgt.s32 q12, q3, q13
+0x6a,0x83,0x46,0xf3 = vcgt.u8 q12, q3, q13
+0x6a,0x83,0x56,0xf3 = vcgt.u16 q12, q3, q13
+0x6a,0x83,0x66,0xf3 = vcgt.u32 q12, q3, q13
+0x6a,0x8e,0x66,0xf3 = vcgt.f32 q12, q3, q13
+0x0d,0xc3,0x03,0xf2 = vcgt.s8 d12, d3, d13
+0x0d,0xc3,0x13,0xf2 = vcgt.s16 d12, d3, d13
+0x0d,0xc3,0x23,0xf2 = vcgt.s32 d12, d3, d13
+0x0d,0xc3,0x03,0xf3 = vcgt.u8 d12, d3, d13
+0x0d,0xc3,0x13,0xf3 = vcgt.u16 d12, d3, d13
+0x0d,0xc3,0x23,0xf3 = vcgt.u32 d12, d3, d13
+0x0d,0xce,0x23,0xf3 = vcgt.f32 d12, d3, d13
+0xb0,0x03,0x41,0xf2 = vcge.s8 d16, d17, d16
+0xb0,0x03,0x51,0xf2 = vcge.s16 d16, d17, d16
+0xb0,0x03,0x61,0xf2 = vcge.s32 d16, d17, d16
+0xb0,0x03,0x41,0xf3 = vcge.u8 d16, d17, d16
+0xb0,0x03,0x51,0xf3 = vcge.u16 d16, d17, d16
+0xb0,0x03,0x61,0xf3 = vcge.u32 d16, d17, d16
+0xa0,0x0e,0x41,0xf3 = vcge.f32 d16, d17, d16
+0xf0,0x03,0x42,0xf2 = vcge.s8 q8, q9, q8
+0xf0,0x03,0x52,0xf2 = vcge.s16 q8, q9, q8
+0xf0,0x03,0x62,0xf2 = vcge.s32 q8, q9, q8
+0xf0,0x03,0x42,0xf3 = vcge.u8 q8, q9, q8
+0xf0,0x03,0x52,0xf3 = vcge.u16 q8, q9, q8
+0xf0,0x03,0x62,0xf3 = vcge.u32 q8, q9, q8
+0xe0,0x0e,0x42,0xf3 = vcge.f32 q8, q9, q8
+0xf6,0x2e,0x68,0xf3 = vacgt.f32 q9, q12, q11
+0x1b,0x9e,0x2c,0xf3 = vacgt.f32 d9, d12, d11
+0xf6,0x6e,0x68,0xf3 = vacgt.f32 q11, q12, q11
+0x1b,0xbe,0x2c,0xf3 = vacgt.f32 d11, d12, d11
+0xf6,0x2e,0x48,0xf3 = vacge.f32 q9, q12, q11
+0x1b,0x9e,0x0c,0xf3 = vacge.f32 d9, d12, d11
+0xf6,0x6e,0x48,0xf3 = vacge.f32 q11, q12, q11
+0x1b,0xbe,0x0c,0xf3 = vacge.f32 d11, d12, d11

data/test/MC/ARM/neon-convert-encoding.s.cs ADDED

@@ -0,0 +1,27 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16
+0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16
+0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16
+0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16
+0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8
+0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8
+0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8
+0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8
+0x30,0x0f,0xff,0xf2 = vcvt.s32.f32 d16, d16, #1
+0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16
+0x30,0x0f,0xff,0xf3 = vcvt.u32.f32 d16, d16, #1
+0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16
+0x30,0x0e,0xff,0xf2 = vcvt.f32.s32 d16, d16, #1
+0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16
+0x30,0x0e,0xff,0xf3 = vcvt.f32.u32 d16, d16, #1
+0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16
+0x70,0x0f,0xff,0xf2 = vcvt.s32.f32 q8, q8, #1
+0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8
+0x70,0x0f,0xff,0xf3 = vcvt.u32.f32 q8, q8, #1
+0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8
+0x70,0x0e,0xff,0xf2 = vcvt.f32.s32 q8, q8, #1
+0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8
+0x70,0x0e,0xff,0xf3 = vcvt.f32.u32 q8, q8, #1
+0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8
+0x20,0x07,0xf6,0xf3 = vcvt.f32.f16 q8, d16
+0x20,0x06,0xf6,0xf3 = vcvt.f16.f32 d16, q8

data/test/MC/ARM/neon-crypto.s.cs ADDED

@@ -0,0 +1,16 @@
+# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
+0x42,0x03,0xb0,0xf3 = aesd.8 q0, q1
+0x02,0x03,0xb0,0xf3 = aese.8 q0, q1
+0xc2,0x03,0xb0,0xf3 = aesimc.8 q0, q1
+0x82,0x03,0xb0,0xf3 = aesmc.8 q0, q1
+0xc2,0x02,0xb9,0xf3 = sha1h.32 q0, q1
+0x82,0x03,0xba,0xf3 = sha1su1.32 q0, q1
+0xc2,0x03,0xba,0xf3 = sha256su0.32 q0, q1
+0x44,0x0c,0x02,0xf2 = sha1c.32 q0, q1, q2
+0x44,0x0c,0x22,0xf2 = sha1m.32 q0, q1, q2
+0x44,0x0c,0x12,0xf2 = sha1p.32 q0, q1, q2
+0x44,0x0c,0x32,0xf2 = sha1su0.32 q0, q1, q2
+0x44,0x0c,0x02,0xf3 = sha256h.32 q0, q1, q2
+0x44,0x0c,0x12,0xf3 = sha256h2.32 q0, q1, q2
+0x44,0x0c,0x22,0xf3 = sha256su1.32 q0, q1, q2
+0xa1,0x0e,0xe0,0xf2 = vmull.p64 q8, d16, d17

data/test/MC/ARM/neon-dup-encoding.s.cs ADDED

@@ -0,0 +1,13 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x90,0x0b,0xc0,0xee = vdup.8 d16, r0
+0xb0,0x0b,0x80,0xee = vdup.16 d16, r0
+0x90,0x0b,0x80,0xee = vdup.32 d16, r0
+0x90,0x0b,0xe0,0xee = vdup.8 q8, r0
+0xb0,0x0b,0xa0,0xee = vdup.16 q8, r0
+0x90,0x0b,0xa0,0xee = vdup.32 q8, r0
+0x20,0x0c,0xf3,0xf3 = vdup.8 d16, d16[1]
+0x20,0x0c,0xf6,0xf3 = vdup.16 d16, d16[1]
+0x20,0x0c,0xfc,0xf3 = vdup.32 d16, d16[1]
+0x60,0x0c,0xf3,0xf3 = vdup.8 q8, d16[1]
+0x60,0x0c,0xf6,0xf3 = vdup.16 q8, d16[1]
+0x60,0x0c,0xfc,0xf3 = vdup.32 q8, d16[1]

data/test/MC/ARM/neon-minmax-encoding.s.cs ADDED

@@ -0,0 +1,57 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x03,0x16,0x02,0xf2 = vmax.s8 d1, d2, d3
+0x06,0x46,0x15,0xf2 = vmax.s16 d4, d5, d6
+0x09,0x76,0x28,0xf2 = vmax.s32 d7, d8, d9
+0x0c,0xa6,0x0b,0xf3 = vmax.u8 d10, d11, d12
+0x0f,0xd6,0x1e,0xf3 = vmax.u16 d13, d14, d15
+0xa2,0x06,0x61,0xf3 = vmax.u32 d16, d17, d18
+0xa5,0x3f,0x44,0xf2 = vmax.f32 d19, d20, d21
+0x03,0x26,0x02,0xf2 = vmax.s8 d2, d2, d3
+0x06,0x56,0x15,0xf2 = vmax.s16 d5, d5, d6
+0x09,0x86,0x28,0xf2 = vmax.s32 d8, d8, d9
+0x0c,0xb6,0x0b,0xf3 = vmax.u8 d11, d11, d12
+0x0f,0xe6,0x1e,0xf3 = vmax.u16 d14, d14, d15
+0xa2,0x16,0x61,0xf3 = vmax.u32 d17, d17, d18
+0xa5,0x4f,0x44,0xf2 = vmax.f32 d20, d20, d21
+0x46,0x26,0x04,0xf2 = vmax.s8 q1, q2, q3
+0x4c,0x86,0x1a,0xf2 = vmax.s16 q4, q5, q6
+0xe2,0xe6,0x20,0xf2 = vmax.s32 q7, q8, q9
+0xe8,0x46,0x46,0xf3 = vmax.u8 q10, q11, q12
+0xee,0xa6,0x5c,0xf3 = vmax.u16 q13, q14, q15
+0x60,0xc6,0x2e,0xf3 = vmax.u32 q6, q7, q8
+0x42,0x2f,0x4a,0xf2 = vmax.f32 q9, q5, q1
+0x46,0x46,0x04,0xf2 = vmax.s8 q2, q2, q3
+0x4c,0xa6,0x1a,0xf2 = vmax.s16 q5, q5, q6
+0xe2,0x06,0x60,0xf2 = vmax.s32 q8, q8, q9
+0xc4,0x66,0x46,0xf3 = vmax.u8 q11, q11, q2
+0x4a,0x86,0x18,0xf3 = vmax.u16 q4, q4, q5
+0x60,0xe6,0x2e,0xf3 = vmax.u32 q7, q7, q8
+0x42,0x4f,0x04,0xf2 = vmax.f32 q2, q2, q1
+0x13,0x16,0x02,0xf2 = vmin.s8 d1, d2, d3
+0x16,0x46,0x15,0xf2 = vmin.s16 d4, d5, d6
+0x19,0x76,0x28,0xf2 = vmin.s32 d7, d8, d9
+0x1c,0xa6,0x0b,0xf3 = vmin.u8 d10, d11, d12
+0x1f,0xd6,0x1e,0xf3 = vmin.u16 d13, d14, d15
+0xb2,0x06,0x61,0xf3 = vmin.u32 d16, d17, d18
+0xa5,0x3f,0x64,0xf2 = vmin.f32 d19, d20, d21
+0x13,0x26,0x02,0xf2 = vmin.s8 d2, d2, d3
+0x16,0x56,0x15,0xf2 = vmin.s16 d5, d5, d6
+0x19,0x86,0x28,0xf2 = vmin.s32 d8, d8, d9
+0x1c,0xb6,0x0b,0xf3 = vmin.u8 d11, d11, d12
+0x1f,0xe6,0x1e,0xf3 = vmin.u16 d14, d14, d15
+0xb2,0x16,0x61,0xf3 = vmin.u32 d17, d17, d18
+0xa5,0x4f,0x64,0xf2 = vmin.f32 d20, d20, d21
+0x56,0x26,0x04,0xf2 = vmin.s8 q1, q2, q3
+0x5c,0x86,0x1a,0xf2 = vmin.s16 q4, q5, q6
+0xf2,0xe6,0x20,0xf2 = vmin.s32 q7, q8, q9
+0xf8,0x46,0x46,0xf3 = vmin.u8 q10, q11, q12
+0xfe,0xa6,0x5c,0xf3 = vmin.u16 q13, q14, q15
+0x70,0xc6,0x2e,0xf3 = vmin.u32 q6, q7, q8
+0x42,0x2f,0x6a,0xf2 = vmin.f32 q9, q5, q1
+0x56,0x46,0x04,0xf2 = vmin.s8 q2, q2, q3
+0x5c,0xa6,0x1a,0xf2 = vmin.s16 q5, q5, q6
+0xf2,0x06,0x60,0xf2 = vmin.s32 q8, q8, q9
+0xd4,0x66,0x46,0xf3 = vmin.u8 q11, q11, q2
+0x5a,0x86,0x18,0xf3 = vmin.u16 q4, q4, q5
+0x70,0xe6,0x2e,0xf3 = vmin.u32 q7, q7, q8
+0x42,0x4f,0x24,0xf2 = vmin.f32 q2, q2, q1

data/test/MC/ARM/neon-mov-encoding.s.cs ADDED

@@ -0,0 +1,76 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x18,0x0e,0xc0,0xf2 = vmov.i8 d16, #0x8
+0x10,0x08,0xc1,0xf2 = vmov.i16 d16, #0x10
+0x10,0x0a,0xc1,0xf2 = vmov.i16 d16, #0x1000
+0x10,0x00,0xc2,0xf2 = vmov.i32 d16, #0x20
+0x10,0x02,0xc2,0xf2 = vmov.i32 d16, #0x2000
+0x10,0x04,0xc2,0xf2 = vmov.i32 d16, #0x200000
+0x10,0x06,0xc2,0xf2 = vmov.i32 d16, #0x20000000
+0x10,0x0c,0xc2,0xf2 = vmov.i32 d16, #0x20ff
+0x10,0x0d,0xc2,0xf2 = vmov.i32 d16, #0x20ffff
+0x33,0x0e,0xc1,0xf3 = vmov.i64 d16, #0xff0000ff0000ffff
+0x58,0x0e,0xc0,0xf2 = vmov.i8 q8, #0x8
+0x50,0x08,0xc1,0xf2 = vmov.i16 q8, #0x10
+0x50,0x0a,0xc1,0xf2 = vmov.i16 q8, #0x1000
+0x50,0x00,0xc2,0xf2 = vmov.i32 q8, #0x20
+0x50,0x02,0xc2,0xf2 = vmov.i32 q8, #0x2000
+0x50,0x04,0xc2,0xf2 = vmov.i32 q8, #0x200000
+0x50,0x06,0xc2,0xf2 = vmov.i32 q8, #0x20000000
+0x50,0x0c,0xc2,0xf2 = vmov.i32 q8, #0x20ff
+0x50,0x0d,0xc2,0xf2 = vmov.i32 q8, #0x20ffff
+0x73,0x0e,0xc1,0xf3 = vmov.i64 q8, #0xff0000ff0000ffff
+0x30,0x08,0xc1,0xf2 = vmvn.i16 d16, #0x10
+0x30,0x0a,0xc1,0xf2 = vmvn.i16 d16, #0x1000
+0x30,0x00,0xc2,0xf2 = vmvn.i32 d16, #0x20
+0x30,0x02,0xc2,0xf2 = vmvn.i32 d16, #0x2000
+0x30,0x04,0xc2,0xf2 = vmvn.i32 d16, #0x200000
+0x30,0x06,0xc2,0xf2 = vmvn.i32 d16, #0x20000000
+0x30,0x0c,0xc2,0xf2 = vmvn.i32 d16, #0x20ff
+0x30,0x0d,0xc2,0xf2 = vmvn.i32 d16, #0x20ffff
+0x30,0x0a,0xc8,0xf2 = vmovl.s8 q8, d16
+0x30,0x0a,0xd0,0xf2 = vmovl.s16 q8, d16
+0x30,0x0a,0xe0,0xf2 = vmovl.s32 q8, d16
+0x30,0x0a,0xc8,0xf3 = vmovl.u8 q8, d16
+0x30,0x0a,0xd0,0xf3 = vmovl.u16 q8, d16
+0x30,0x0a,0xe0,0xf3 = vmovl.u32 q8, d16
+0x20,0x02,0xf2,0xf3 = vmovn.i16 d16, q8
+0x20,0x02,0xf6,0xf3 = vmovn.i32 d16, q8
+0x20,0x02,0xfa,0xf3 = vmovn.i64 d16, q8
+0xa0,0x02,0xf2,0xf3 = vqmovn.s16 d16, q8
+0xa0,0x02,0xf6,0xf3 = vqmovn.s32 d16, q8
+0xa0,0x02,0xfa,0xf3 = vqmovn.s64 d16, q8
+0xe0,0x02,0xf2,0xf3 = vqmovn.u16 d16, q8
+0xe0,0x02,0xf6,0xf3 = vqmovn.u32 d16, q8
+0xe0,0x02,0xfa,0xf3 = vqmovn.u64 d16, q8
+0x60,0x02,0xf2,0xf3 = vqmovun.s16 d16, q8
+0x60,0x02,0xf6,0xf3 = vqmovun.s32 d16, q8
+0x60,0x02,0xfa,0xf3 = vqmovun.s64 d16, q8
+0xb0,0x0b,0x50,0xee = vmov.s8 r0, d16[1]
+0xf0,0x0b,0x10,0xee = vmov.s16 r0, d16[1]
+0xb0,0x0b,0xd0,0xee = vmov.u8 r0, d16[1]
+0xf0,0x0b,0x90,0xee = vmov.u16 r0, d16[1]
+0x90,0x0b,0x30,0xee = vmov.32 r0, d16[1]
+0xb0,0x1b,0x40,0xee = vmov.8 d16[1], r1
+0xf0,0x1b,0x00,0xee = vmov.16 d16[1], r1
+0x90,0x1b,0x20,0xee = vmov.32 d16[1], r1
+0xb0,0x1b,0x42,0xee = vmov.8 d18[1], r1
+0xf0,0x1b,0x02,0xee = vmov.16 d18[1], r1
+0x90,0x1b,0x22,0xee = vmov.32 d18[1], r1
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2
+0x82,0x15,0xb0,0xf3 = vmvn d1, d2

data/test/MC/ARM/neon-mul-accum-encoding.s.cs ADDED

@@ -0,0 +1,39 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xa1,0x09,0x42,0xf2 = vmla.i8 d16, d18, d17
+0xa1,0x09,0x52,0xf2 = vmla.i16 d16, d18, d17
+0xa1,0x09,0x62,0xf2 = vmla.i32 d16, d18, d17
+0xb1,0x0d,0x42,0xf2 = vmla.f32 d16, d18, d17
+0xe4,0x29,0x40,0xf2 = vmla.i8 q9, q8, q10
+0xe4,0x29,0x50,0xf2 = vmla.i16 q9, q8, q10
+0xe4,0x29,0x60,0xf2 = vmla.i32 q9, q8, q10
+0xf4,0x2d,0x40,0xf2 = vmla.f32 q9, q8, q10
+0xc3,0x80,0xe0,0xf3 = vmla.i32 q12, q8, d3[0]
+0xa2,0x08,0xc3,0xf2 = vmlal.s8 q8, d19, d18
+0xa2,0x08,0xd3,0xf2 = vmlal.s16 q8, d19, d18
+0xa2,0x08,0xe3,0xf2 = vmlal.s32 q8, d19, d18
+0xa2,0x08,0xc3,0xf3 = vmlal.u8 q8, d19, d18
+0xa2,0x08,0xd3,0xf3 = vmlal.u16 q8, d19, d18
+0xa2,0x08,0xe3,0xf3 = vmlal.u32 q8, d19, d18
+0xa2,0x09,0xd3,0xf2 = vqdmlal.s16 q8, d19, d18
+0xa2,0x09,0xe3,0xf2 = vqdmlal.s32 q8, d19, d18
+0x47,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[0]
+0x4f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[1]
+0x67,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[2]
+0x6f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[3]
+0xa1,0x09,0x42,0xf3 = vmls.i8 d16, d18, d17
+0xa1,0x09,0x52,0xf3 = vmls.i16 d16, d18, d17
+0xa1,0x09,0x62,0xf3 = vmls.i32 d16, d18, d17
+0xb1,0x0d,0x62,0xf2 = vmls.f32 d16, d18, d17
+0xe4,0x29,0x40,0xf3 = vmls.i8 q9, q8, q10
+0xe4,0x29,0x50,0xf3 = vmls.i16 q9, q8, q10
+0xe4,0x29,0x60,0xf3 = vmls.i32 q9, q8, q10
+0xf4,0x2d,0x60,0xf2 = vmls.f32 q9, q8, q10
+0xe6,0x84,0x98,0xf3 = vmls.i16 q4, q12, d6[2]
+0xa2,0x0a,0xc3,0xf2 = vmlsl.s8 q8, d19, d18
+0xa2,0x0a,0xd3,0xf2 = vmlsl.s16 q8, d19, d18
+0xa2,0x0a,0xe3,0xf2 = vmlsl.s32 q8, d19, d18
+0xa2,0x0a,0xc3,0xf3 = vmlsl.u8 q8, d19, d18
+0xa2,0x0a,0xd3,0xf3 = vmlsl.u16 q8, d19, d18
+0xa2,0x0a,0xe3,0xf3 = vmlsl.u32 q8, d19, d18
+0xa2,0x0b,0xd3,0xf2 = vqdmlsl.s16 q8, d19, d18
+0xa2,0x0b,0xe3,0xf2 = vqdmlsl.s32 q8, d19, d18

data/test/MC/ARM/neon-mul-encoding.s.cs ADDED

@@ -0,0 +1,72 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17
+0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17
+0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17
+0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17
+0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9
+0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9
+0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9
+0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9
+0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17
+0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9
+0x68,0x28,0xd8,0xf2 = vmul.i16 d18, d8, d0[3]
+0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17
+0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17
+0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17
+0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17
+0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9
+0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9
+0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9
+0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9
+0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17
+0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9
+0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17
+0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17
+0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9
+0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9
+0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17
+0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17
+0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9
+0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9
+0x43,0xbc,0x92,0xf2 = vqdmulh.s16 d11, d2, d3[0]
+0xa1,0x0b,0x50,0xf3 = vqrdmulh.s16 d16, d16, d17
+0xa1,0x0b,0x60,0xf3 = vqrdmulh.s32 d16, d16, d17
+0xe2,0x0b,0x50,0xf3 = vqrdmulh.s16 q8, q8, q9
+0xe2,0x0b,0x60,0xf3 = vqrdmulh.s32 q8, q8, q9
+0xa1,0x0c,0xc0,0xf2 = vmull.s8 q8, d16, d17
+0xa1,0x0c,0xd0,0xf2 = vmull.s16 q8, d16, d17
+0xa1,0x0c,0xe0,0xf2 = vmull.s32 q8, d16, d17
+0xa1,0x0c,0xc0,0xf3 = vmull.u8 q8, d16, d17
+0xa1,0x0c,0xd0,0xf3 = vmull.u16 q8, d16, d17
+0xa1,0x0c,0xe0,0xf3 = vmull.u32 q8, d16, d17
+0xa1,0x0e,0xc0,0xf2 = vmull.p8 q8, d16, d17
+0xa1,0x0d,0xd0,0xf2 = vqdmull.s16 q8, d16, d17
+0xa1,0x0d,0xe0,0xf2 = vqdmull.s32 q8, d16, d17
+0x64,0x08,0x90,0xf2 = vmul.i16 d0, d0, d4[2]
+0x6f,0x18,0x91,0xf2 = vmul.i16 d1, d1, d7[3]
+0x49,0x28,0x92,0xf2 = vmul.i16 d2, d2, d1[1]
+0x42,0x38,0xa3,0xf2 = vmul.i32 d3, d3, d2[0]
+0x63,0x48,0xa4,0xf2 = vmul.i32 d4, d4, d3[1]
+0x44,0x58,0xa5,0xf2 = vmul.i32 d5, d5, d4[0]
+0x65,0x69,0xa6,0xf2 = vmul.f32 d6, d6, d5[1]
+0x64,0x08,0x90,0xf3 = vmul.i16 q0, q0, d4[2]
+0x6f,0x28,0x92,0xf3 = vmul.i16 q1, q1, d7[3]
+0x49,0x48,0x94,0xf3 = vmul.i16 q2, q2, d1[1]
+0x42,0x68,0xa6,0xf3 = vmul.i32 q3, q3, d2[0]
+0x63,0x88,0xa8,0xf3 = vmul.i32 q4, q4, d3[1]
+0x44,0xa8,0xaa,0xf3 = vmul.i32 q5, q5, d4[0]
+0x65,0xc9,0xac,0xf3 = vmul.f32 q6, q6, d5[1]
+0x64,0x98,0x90,0xf2 = vmul.i16 d9, d0, d4[2]
+0x6f,0x88,0x91,0xf2 = vmul.i16 d8, d1, d7[3]
+0x49,0x78,0x92,0xf2 = vmul.i16 d7, d2, d1[1]
+0x42,0x68,0xa3,0xf2 = vmul.i32 d6, d3, d2[0]
+0x63,0x58,0xa4,0xf2 = vmul.i32 d5, d4, d3[1]
+0x44,0x48,0xa5,0xf2 = vmul.i32 d4, d5, d4[0]
+0x65,0x39,0xa6,0xf2 = vmul.f32 d3, d6, d5[1]
+0x64,0x28,0xd0,0xf3 = vmul.i16 q9, q0, d4[2]
+0x6f,0x08,0xd2,0xf3 = vmul.i16 q8, q1, d7[3]
+0x49,0xe8,0x94,0xf3 = vmul.i16 q7, q2, d1[1]
+0x42,0xc8,0xa6,0xf3 = vmul.i32 q6, q3, d2[0]
+0x63,0xa8,0xa8,0xf3 = vmul.i32 q5, q4, d3[1]
+0x44,0x88,0xaa,0xf3 = vmul.i32 q4, q5, d4[0]
+0x65,0x69,0xac,0xf3 = vmul.f32 q3, q6, d5[1]

data/test/MC/ARM/neon-neg-encoding.s.cs ADDED

@@ -0,0 +1,15 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xa0,0x03,0xf1,0xf3 = vneg.s8 d16, d16
+0xa0,0x03,0xf5,0xf3 = vneg.s16 d16, d16
+0xa0,0x03,0xf9,0xf3 = vneg.s32 d16, d16
+0xa0,0x07,0xf9,0xf3 = vneg.f32 d16, d16
+0xe0,0x03,0xf1,0xf3 = vneg.s8 q8, q8
+0xe0,0x03,0xf5,0xf3 = vneg.s16 q8, q8
+0xe0,0x03,0xf9,0xf3 = vneg.s32 q8, q8
+0xe0,0x07,0xf9,0xf3 = vneg.f32 q8, q8
+0xa0,0x07,0xf0,0xf3 = vqneg.s8 d16, d16
+0xa0,0x07,0xf4,0xf3 = vqneg.s16 d16, d16
+0xa0,0x07,0xf8,0xf3 = vqneg.s32 d16, d16
+0xe0,0x07,0xf0,0xf3 = vqneg.s8 q8, q8
+0xe0,0x07,0xf4,0xf3 = vqneg.s16 q8, q8
+0xe0,0x07,0xf8,0xf3 = vqneg.s32 q8, q8

data/test/MC/ARM/neon-pairwise-encoding.s.cs ADDED

@@ -0,0 +1,47 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xb0,0x0b,0x41,0xf2 = vpadd.i8 d16, d17, d16
+0xb0,0x0b,0x51,0xf2 = vpadd.i16 d16, d17, d16
+0xb0,0x0b,0x61,0xf2 = vpadd.i32 d16, d17, d16
+0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17
+0xb0,0x1b,0x41,0xf2 = vpadd.i8 d17, d17, d16
+0xb0,0x1b,0x51,0xf2 = vpadd.i16 d17, d17, d16
+0xb0,0x1b,0x61,0xf2 = vpadd.i32 d17, d17, d16
+0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17
+0x20,0x02,0xf0,0xf3 = vpaddl.s8 d16, d16
+0x20,0x02,0xf4,0xf3 = vpaddl.s16 d16, d16
+0x20,0x02,0xf8,0xf3 = vpaddl.s32 d16, d16
+0xa0,0x02,0xf0,0xf3 = vpaddl.u8 d16, d16
+0xa0,0x02,0xf4,0xf3 = vpaddl.u16 d16, d16
+0xa0,0x02,0xf8,0xf3 = vpaddl.u32 d16, d16
+0x60,0x02,0xf0,0xf3 = vpaddl.s8 q8, q8
+0x60,0x02,0xf4,0xf3 = vpaddl.s16 q8, q8
+0x60,0x02,0xf8,0xf3 = vpaddl.s32 q8, q8
+0xe0,0x02,0xf0,0xf3 = vpaddl.u8 q8, q8
+0xe0,0x02,0xf4,0xf3 = vpaddl.u16 q8, q8
+0xe0,0x02,0xf8,0xf3 = vpaddl.u32 q8, q8
+0x21,0x06,0xf0,0xf3 = vpadal.s8 d16, d17
+0x21,0x06,0xf4,0xf3 = vpadal.s16 d16, d17
+0x21,0x06,0xf8,0xf3 = vpadal.s32 d16, d17
+0xa1,0x06,0xf0,0xf3 = vpadal.u8 d16, d17
+0xa1,0x06,0xf4,0xf3 = vpadal.u16 d16, d17
+0xa1,0x06,0xf8,0xf3 = vpadal.u32 d16, d17
+0x60,0x26,0xf0,0xf3 = vpadal.s8 q9, q8
+0x60,0x26,0xf4,0xf3 = vpadal.s16 q9, q8
+0x60,0x26,0xf8,0xf3 = vpadal.s32 q9, q8
+0xe0,0x26,0xf0,0xf3 = vpadal.u8 q9, q8
+0xe0,0x26,0xf4,0xf3 = vpadal.u16 q9, q8
+0xe0,0x26,0xf8,0xf3 = vpadal.u32 q9, q8
+0xb1,0x0a,0x40,0xf2 = vpmin.s8 d16, d16, d17
+0xb1,0x0a,0x50,0xf2 = vpmin.s16 d16, d16, d17
+0xb1,0x0a,0x60,0xf2 = vpmin.s32 d16, d16, d17
+0xb1,0x0a,0x40,0xf3 = vpmin.u8 d16, d16, d17
+0xb1,0x0a,0x50,0xf3 = vpmin.u16 d16, d16, d17
+0xb1,0x0a,0x60,0xf3 = vpmin.u32 d16, d16, d17
+0xa1,0x0f,0x60,0xf3 = vpmin.f32 d16, d16, d17
+0xa1,0x0a,0x40,0xf2 = vpmax.s8 d16, d16, d17
+0xa1,0x0a,0x50,0xf2 = vpmax.s16 d16, d16, d17
+0xa1,0x0a,0x60,0xf2 = vpmax.s32 d16, d16, d17
+0xa1,0x0a,0x40,0xf3 = vpmax.u8 d16, d16, d17
+0xa1,0x0a,0x50,0xf3 = vpmax.u16 d16, d16, d17
+0xa1,0x0a,0x60,0xf3 = vpmax.u32 d16, d16, d17
+0xa1,0x0f,0x40,0xf3 = vpmax.f32 d16, d16, d17