crabstone 3.0.3

data/test/test_skipdata.rb.SPEC

@@ -0,0 +1,58 @@
+****************
+Platform: X86 32 (Intel syntax) - Skip data
+Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x00 0x91 0x92 
+Disasm:
+0x1000:	lea		ecx, dword ptr [edx + esi + 8]
+0x1004:	add		eax, ebx
+0x1006:	add		esi, 0x1234
+0x100c:	.byte		0x00
+0x100d:	xchg		eax, ecx
+0x100e:	xchg		eax, edx
+0x100f:
+
+****************
+Platform: Arm - Skip data
+Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
+Disasm:
+0x1000:	andeq		r0, r0, sp, ror #1
+0x1004:	svceq		#0x5a1a00
+0x1008:	stmibeq		r2, {r0, r1, r2, r3, r4, r8, sb, sl, fp, ip, sp, lr, pc} ^
+0x100c:	andeq		r0, r0, r0, lsl #1
+0x1010:	bhs		#0xffafec34
+0x1014:	.byte		0xff, 0xff, 0x7f, 0x57
+0x1018:	.byte		0xe3, 0x01, 0xff, 0xff
+0x101c:	rsceq		r5, fp, pc, ror r7
+0x1020:	strhs		r0, [r0], #-0xf0
+0x1024:	stmdavc		r0, {r1, r4, r5, r7, r8, sb, sl, fp, lr}
+0x1028:
+
+****************
+Platform: X86 32 (Intel syntax) - Skip data with custom mnemonic
+Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x00 0x91 0x92 
+Disasm:
+0x1000:	lea		ecx, dword ptr [edx + esi + 8]
+0x1004:	add		eax, ebx
+0x1006:	add		esi, 0x1234
+0x100c:	db		0x00
+0x100d:	xchg		eax, ecx
+0x100e:	xchg		eax, edx
+0x100f:
+
+****************
+Platform: Arm - Skip data with callback
+Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
+Disasm:
+0x1000:	andeq		r0, r0, sp, ror #1
+0x1004:	svceq		#0x5a1a00
+0x1008:	stmibeq		r2, {r0, r1, r2, r3, r4, r8, sb, sl, fp, ip, sp, lr, pc} ^
+0x100c:	andeq		r0, r0, r0, lsl #1
+0x1010:	bhs		#0xffafec34
+0x1014:	db		0xff, 0xff
+0x1016:	db		0x7f, 0x57
+0x1018:	db		0xe3, 0x01
+0x101a:	db		0xff, 0xff
+0x101c:	rsceq		r5, fp, pc, ror r7
+0x1020:	strhs		r0, [r0], #-0xf0
+0x1024:	stmdavc		r0, {r1, r4, r5, r7, r8, sb, sl, fp, lr}
+0x1028:
+

data/test/test_sparc.rb

@@ -0,0 +1,113 @@
+#!/usr/bin/env ruby
+
+# Library by Nguyen Anh Quynh
+# Original binding by Nguyen Anh Quynh and Tan Sheng Di
+# Additional binding work by Ben Nagy
+# (c) 2013 COSEINC. All Rights Reserved.
+
+require 'crabstone'
+require 'stringio'
+
+module TestSparc
+
+  SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
+  SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
+
+  include Crabstone
+  include Crabstone::Sparc
+
+  @platforms = [
+    Hash[
+      'arch' => ARCH_SPARC,
+      'mode' => MODE_BIG_ENDIAN,
+      'code' => SPARC_CODE,
+      'comment' => "Sparc"
+    ],
+    Hash[
+      'arch' => ARCH_SPARC,
+      'mode' => MODE_BIG_ENDIAN + MODE_V9,
+      'code' => SPARCV9_CODE,
+      'comment' => "SparcV9"
+    ]
+  ]
+
+  def self.uint32 i
+    Integer(i) & 0xffffffff
+  end
+
+  def self.print_detail cs, insn, sio
+    if insn.op_count > 0
+      sio.puts "\top_count: #{insn.op_count}"
+      insn.operands.each_with_index do |op,idx|
+        case op[:type]
+        when OP_REG
+          sio.puts "\t\toperands[#{idx}].type: REG = #{cs.reg_name(op.value)}"
+        when OP_IMM
+          sio.puts "\t\toperands[#{idx}].type: IMM = 0x#{self.uint32(op.value).to_s(16)}"
+        when OP_MEM
+          sio.puts "\t\toperands[#{idx}].type: MEM"
+          if op.value[:base].nonzero?
+            sio.puts "\t\t\toperands[#{idx}].mem.base: REG = %s" % cs.reg_name(op.value[:base])
+          end
+          if op.value[:index].nonzero?
+            sio.puts "\t\t\toperands[#{idx}].mem.index: REG = %s" % cs.reg_name(op.value[:index])
+          end
+          if op.value[:disp].nonzero?
+            sio.puts "\t\t\toperands[#{idx}].mem.disp: 0x%x" % (self.uint32(op.value[:disp]))
+          end
+        end
+      end
+    end
+
+    if insn.cc.nonzero?
+      sio.puts("\tCode condition: %u" % insn.cc)
+    end
+
+    if insn.hint.nonzero?
+      sio.puts("\tHint code: %u" % insn.hint)
+    end
+
+    sio.puts
+  end
+
+  ours = StringIO.new
+
+  begin
+    cs    = Disassembler.new(0,0)
+    print "Sparc Test: Capstone v #{cs.version.join('.')} - "
+  ensure
+    cs.close
+  end
+
+  #Test through all modes and architectures
+  @platforms.each do |p|
+    ours.puts "****************"
+    ours.puts "Platform: #{p['comment']}"
+    ours.puts "Code:#{p['code'].bytes.map {|b| "0x%.2x" % b}.join(' ')} "
+    ours.puts "Disasm:"
+
+    cs    = Disassembler.new(p['arch'], p['mode'])
+    cs.decomposer = true
+    cache = nil
+
+    cs.disasm(p['code'], 0x1000).each {|insn|
+      ours.puts "0x#{insn.address.to_s(16)}:\t#{insn.mnemonic}\t#{insn.op_str}"
+      self.print_detail(cs, insn, ours)
+      cache = insn.address + insn.size
+    }
+
+    ours.printf("0x%x:\n", cache)
+    ours.puts
+    cs.close
+  end
+
+  ours.rewind
+  theirs = File.binread(__FILE__ + ".SPEC")
+  if ours.read == theirs
+    puts "#{__FILE__}: PASS"
+  else
+    ours.rewind
+    puts ours.read
+    puts "#{__FILE__}: FAIL"
+  end
+end

data/test/test_sparc.rb.SPEC

@@ -0,0 +1,116 @@
+****************
+Platform: Sparc
+Code:0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
+Disasm:
+0x1000:	cmp	%g1, %g2
+	op_count: 2
+		operands[0].type: REG = g1
+		operands[1].type: REG = g2
+
+0x1004:	jmpl	%o1+8, %g2
+	op_count: 2
+		operands[0].type: MEM
+			operands[0].mem.base: REG = o1
+			operands[0].mem.disp: 0x8
+		operands[1].type: REG = g2
+
+0x1008:	restore	%g0, 1, %g2
+	op_count: 3
+		operands[0].type: REG = g0
+		operands[1].type: IMM = 0x1
+		operands[2].type: REG = g2
+
+0x100c:	restore	
+
+0x1010:	mov	1, %o0
+	op_count: 2
+		operands[0].type: IMM = 0x1
+		operands[1].type: REG = o0
+
+0x1014:	casx	[%i0], %l6, %o2
+	op_count: 3
+		operands[0].type: MEM
+			operands[0].mem.base: REG = i0
+		operands[1].type: REG = l6
+		operands[2].type: REG = o2
+
+0x1018:	sethi	0xa, %l0
+	op_count: 2
+		operands[0].type: IMM = 0xa
+		operands[1].type: REG = l0
+
+0x101c:	add	%g1, %g2, %g3
+	op_count: 3
+		operands[0].type: REG = g1
+		operands[1].type: REG = g2
+		operands[2].type: REG = g3
+
+0x1020:	nop	
+
+0x1024:	bne	0x1020
+	op_count: 1
+		operands[0].type: IMM = 0x1020
+	Code condition: 265
+
+0x1028:	ba	0x1024
+	op_count: 1
+		operands[0].type: IMM = 0x1024
+
+0x102c:	add	%o0, %o1, %l0
+	op_count: 3
+		operands[0].type: REG = o0
+		operands[1].type: REG = o1
+		operands[2].type: REG = l0
+
+0x1030:	fbg	0x102c
+	op_count: 1
+		operands[0].type: IMM = 0x102c
+	Code condition: 278
+
+0x1034:	st	%o2, [%g1]
+	op_count: 2
+		operands[0].type: REG = o2
+		operands[1].type: MEM
+			operands[1].mem.base: REG = g1
+
+0x1038:	ldsb	[%i0+%l6], %o2
+	op_count: 2
+		operands[0].type: MEM
+			operands[0].mem.base: REG = i0
+			operands[0].mem.index: REG = l6
+		operands[1].type: REG = o2
+
+0x103c:	brnz,a,pn	%o2, 0x1048
+	op_count: 2
+		operands[0].type: REG = o2
+		operands[1].type: IMM = 0x1048
+	Hint code: 5
+
+0x1040:
+
+****************
+Platform: SparcV9
+Code:0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
+Disasm:
+0x1000:	fcmps	%f0, %f4
+	op_count: 2
+		operands[0].type: REG = f0
+		operands[1].type: REG = f4
+
+0x1004:	fstox	%f0, %f4
+	op_count: 2
+		operands[0].type: REG = f0
+		operands[1].type: REG = f4
+
+0x1008:	fqtoi	%f0, %f4
+	op_count: 2
+		operands[0].type: REG = f0
+		operands[1].type: REG = f4
+
+0x100c:	fnegq	%f0, %f4
+	op_count: 2
+		operands[0].type: REG = f0
+		operands[1].type: REG = f4
+
+0x1010:
+

data/test/test_sysz.rb

@@ -0,0 +1,111 @@
+#!/usr/bin/env ruby
+
+# Library by Nguyen Anh Quynh
+# Original binding by Nguyen Anh Quynh and Tan Sheng Di
+# Additional binding work by Ben Nagy
+# (c) 2013 COSEINC. All Rights Reserved.
+
+require 'crabstone'
+require 'stringio'
+
+module TestSysZ
+
+  SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f"
+
+  include Crabstone
+  include Crabstone::SysZ
+
+  @platforms = [
+    Hash[
+      'arch' => ARCH_SYSZ,
+      'mode' => MODE_BIG_ENDIAN,
+      'code' => SYSZ_CODE,
+      'comment' => "SystemZ"
+    ]
+  ]
+
+  def self.uint32 i
+    Integer(i) & 0xffffffff
+  end
+
+  def self.uint64 i
+    Integer(i) & 0xffffffffffffffff
+  end
+
+  def self.print_detail cs, insn, sio
+    if insn.op_count > 0
+      sio.puts "\top_count: #{insn.op_count}"
+      insn.operands.each_with_index do |op,idx|
+        case op[:type]
+        when OP_REG
+          sio.puts "\t\toperands[#{idx}].type: REG = #{cs.reg_name(op.value)}"
+        when OP_ACREG
+          sio.puts "\t\toperands[#{idx}].type: ACREG = #{op.value}"
+        when OP_IMM
+          sio.puts "\t\toperands[#{idx}].type: IMM = 0x#{self.uint64(op.value).to_s(16)}"
+        when OP_MEM
+          sio.puts "\t\toperands[#{idx}].type: MEM"
+          if op.value[:base].nonzero?
+            sio.puts "\t\t\toperands[#{idx}].mem.base: REG = %s" % cs.reg_name(op.value[:base])
+          end
+          if op.value[:index].nonzero?
+            sio.puts "\t\t\toperands[#{idx}].mem.index: REG = %s" % cs.reg_name(op.value[:index])
+          end
+          if op.value[:length].nonzero?
+            sio.puts "\t\t\toperands[#{idx}].mem.length: REG = %s" % cs.reg_name(op.value[:length])
+          end
+          if op.value[:disp].nonzero?
+            sio.puts "\t\t\toperands[#{idx}].mem.disp: 0x%x" % (self.uint32(op.value[:disp]))
+          end
+        end
+      end
+    end
+
+    if insn.cc.nonzero?
+      sio.puts("\tCode condition: %u" % insn.cc)
+    end
+
+    sio.puts
+  end
+
+  ours = StringIO.new
+
+  begin
+    cs    = Disassembler.new(0,0)
+    print "SystemZ Test: Capstone v #{cs.version.join('.')} - "
+  ensure
+    cs.close
+  end
+
+  #Test through all modes and architectures
+  @platforms.each do |p|
+    ours.puts "****************"
+    ours.puts "Platform: #{p['comment']}"
+    ours.puts "Code:#{p['code'].bytes.map {|b| "0x%.2x" % b}.join(' ')} "
+    ours.puts "Disasm:"
+
+    cs    = Disassembler.new(p['arch'], p['mode'])
+    cs.decomposer = true
+    cache = nil
+
+    cs.disasm(p['code'], 0x1000).each {|insn|
+      ours.puts "0x#{insn.address.to_s(16)}:\t#{insn.mnemonic}\t#{insn.op_str}"
+      self.print_detail(cs, insn, ours)
+      cache = insn.address + insn.size
+    }
+
+    ours.printf("0x%x:\n", cache)
+    ours.puts
+    cs.close
+  end
+
+  ours.rewind
+  theirs = File.binread(__FILE__ + ".SPEC")
+  if ours.read == theirs
+    puts "#{__FILE__}: PASS"
+  else
+    ours.rewind
+    puts ours.read
+    puts "#{__FILE__}: FAIL"
+  end
+end

data/test/test_sysz.rb.SPEC

@@ -0,0 +1,61 @@
+****************
+Platform: SystemZ
+Code:0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 0xec 0x18 0x00 0x00 0xc1 0x7f 
+Disasm:
+0x1000:	adb	%f0, 0
+	op_count: 2
+		operands[0].type: REG = f0
+		operands[1].type: IMM = 0x0
+
+0x1006:	a	%r0, 0xfff(%r15, %r1)
+	op_count: 2
+		operands[0].type: REG = 0
+		operands[1].type: MEM
+			operands[1].mem.base: REG = 1
+			operands[1].mem.index: REG = 15
+			operands[1].mem.disp: 0xfff
+
+0x100a:	afi	%r0, -0x80000000
+	op_count: 2
+		operands[0].type: REG = 0
+		operands[1].type: IMM = 0xffffffff80000000
+
+0x1010:	br	%r7
+	op_count: 1
+		operands[0].type: REG = 7
+
+0x1012:	xiy	0x7ffff(%r15), 0x2a
+	op_count: 2
+		operands[0].type: MEM
+			operands[0].mem.base: REG = 15
+			operands[0].mem.disp: 0x7ffff
+		operands[1].type: IMM = 0x2a
+
+0x1018:	xy	%r0, 0x7ffff(%r1, %r15)
+	op_count: 2
+		operands[0].type: REG = 0
+		operands[1].type: MEM
+			operands[1].mem.base: REG = 15
+			operands[1].mem.index: REG = 1
+			operands[1].mem.disp: 0x7ffff
+
+0x101e:	stmg	%r0, %r0, 0(%r15)
+	op_count: 3
+		operands[0].type: REG = 0
+		operands[1].type: REG = 0
+		operands[2].type: MEM
+			operands[2].mem.base: REG = 15
+
+0x1024:	ear	%r7, %a8
+	op_count: 2
+		operands[0].type: REG = 7
+		operands[1].type: ACREG = 8
+
+0x1028:	clije	%r1, 0xc1, 0x1028
+	op_count: 3
+		operands[0].type: REG = 1
+		operands[1].type: IMM = 0xc1
+		operands[2].type: IMM = 0x1028
+
+0x102e:
+