crabstone 3.0.3
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- checksums.yaml +7 -0
- data/CHANGES.md +61 -0
- data/LICENSE +25 -0
- data/MANIFEST +312 -0
- data/README.md +103 -0
- data/Rakefile +27 -0
- data/bin/genconst +66 -0
- data/bin/genreg +99 -0
- data/crabstone.gemspec +27 -0
- data/examples/hello_world.rb +43 -0
- data/lib/arch/arm.rb +128 -0
- data/lib/arch/arm64.rb +167 -0
- data/lib/arch/arm64_const.rb +1055 -0
- data/lib/arch/arm64_registers.rb +295 -0
- data/lib/arch/arm_const.rb +777 -0
- data/lib/arch/arm_registers.rb +149 -0
- data/lib/arch/mips.rb +78 -0
- data/lib/arch/mips_const.rb +850 -0
- data/lib/arch/mips_registers.rb +208 -0
- data/lib/arch/ppc.rb +90 -0
- data/lib/arch/ppc_const.rb +1181 -0
- data/lib/arch/ppc_registers.rb +209 -0
- data/lib/arch/sparc.rb +79 -0
- data/lib/arch/sparc_const.rb +461 -0
- data/lib/arch/sparc_registers.rb +121 -0
- data/lib/arch/systemz.rb +79 -0
- data/lib/arch/sysz_const.rb +779 -0
- data/lib/arch/sysz_registers.rb +66 -0
- data/lib/arch/x86.rb +107 -0
- data/lib/arch/x86_const.rb +1698 -0
- data/lib/arch/x86_registers.rb +265 -0
- data/lib/arch/xcore.rb +78 -0
- data/lib/arch/xcore_const.rb +185 -0
- data/lib/arch/xcore_registers.rb +57 -0
- data/lib/crabstone.rb +564 -0
- data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
- data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
- data/test/MC/AArch64/neon-2velem.s.cs +113 -0
- data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
- data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
- data/test/MC/AArch64/neon-across.s.cs +40 -0
- data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
- data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
- data/test/MC/AArch64/neon-crypto.s.cs +15 -0
- data/test/MC/AArch64/neon-extract.s.cs +3 -0
- data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
- data/test/MC/AArch64/neon-max-min.s.cs +37 -0
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
- data/test/MC/AArch64/neon-mov.s.cs +74 -0
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
- data/test/MC/AArch64/neon-perm.s.cs +43 -0
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
- data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
- data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
- data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
- data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
- data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
- data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
- data/test/MC/AArch64/neon-shift.s.cs +22 -0
- data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
- data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
- data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
- data/test/MC/AArch64/neon-tbl.s.cs +21 -0
- data/test/MC/AArch64/trace-regs.s.cs +383 -0
- data/test/MC/ARM/arm-aliases.s.cs +7 -0
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
- data/test/MC/ARM/arm-it-block.s.cs +2 -0
- data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
- data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
- data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
- data/test/MC/ARM/arm_instructions.s.cs +25 -0
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
- data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
- data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
- data/test/MC/ARM/crc32-thumb.s.cs +7 -0
- data/test/MC/ARM/crc32.s.cs +7 -0
- data/test/MC/ARM/dot-req.s.cs +3 -0
- data/test/MC/ARM/fp-armv8.s.cs +52 -0
- data/test/MC/ARM/idiv-thumb.s.cs +3 -0
- data/test/MC/ARM/idiv.s.cs +3 -0
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
- data/test/MC/ARM/mode-switch.s.cs +7 -0
- data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
- data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
- data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
- data/test/MC/ARM/neon-crypto.s.cs +16 -0
- data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
- data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
- data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
- data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neon-v8.s.cs +38 -0
- data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
- data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
- data/test/MC/ARM/neon-vswp.s.cs +3 -0
- data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
- data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
- data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
- data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
- data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
- data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
- data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
- data/test/MC/ARM/thumb-hints.s.cs +12 -0
- data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
- data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
- data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
- data/test/MC/ARM/thumb.s.cs +19 -0
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
- data/test/MC/ARM/thumb2-branches.s.cs +85 -0
- data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
- data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
- data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
- data/test/MC/ARM/vfp4.s.cs +13 -0
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
- data/test/MC/ARM/vpush-vpop.s.cs +9 -0
- data/test/MC/Mips/hilo-addressing.s.cs +4 -0
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
- data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
- data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
- data/test/MC/Mips/micromips-expansions.s.cs +20 -0
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
- data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
- data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
- data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
- data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
- data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
- data/test/MC/Mips/mips-expansions.s.cs +20 -0
- data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
- data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
- data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
- data/test/MC/Mips/mips-register-names.s.cs +33 -0
- data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
- data/test/MC/Mips/mips64-instructions.s.cs +3 -0
- data/test/MC/Mips/mips64-register-names.s.cs +33 -0
- data/test/MC/Mips/mips_directives.s.cs +12 -0
- data/test/MC/Mips/nabi-regs.s.cs +12 -0
- data/test/MC/Mips/set-at-directive.s.cs +6 -0
- data/test/MC/Mips/test_2r.s.cs +16 -0
- data/test/MC/Mips/test_2rf.s.cs +33 -0
- data/test/MC/Mips/test_3r.s.cs +243 -0
- data/test/MC/Mips/test_3rf.s.cs +83 -0
- data/test/MC/Mips/test_bit.s.cs +49 -0
- data/test/MC/Mips/test_cbranch.s.cs +11 -0
- data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
- data/test/MC/Mips/test_elm.s.cs +16 -0
- data/test/MC/Mips/test_elm_insert.s.cs +4 -0
- data/test/MC/Mips/test_elm_insve.s.cs +5 -0
- data/test/MC/Mips/test_i10.s.cs +5 -0
- data/test/MC/Mips/test_i5.s.cs +45 -0
- data/test/MC/Mips/test_i8.s.cs +11 -0
- data/test/MC/Mips/test_lsa.s.cs +5 -0
- data/test/MC/Mips/test_mi10.s.cs +24 -0
- data/test/MC/Mips/test_vec.s.cs +8 -0
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
- data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
- data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
- data/test/MC/README +6 -0
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
- data/test/MC/Sparc/sparc-vis.s.cs +2 -0
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
- data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
- data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
- data/test/MC/SystemZ/insn-good.s.cs +2265 -0
- data/test/MC/SystemZ/regs-good.s.cs +45 -0
- data/test/MC/X86/3DNow.s.cs +29 -0
- data/test/MC/X86/address-size.s.cs +5 -0
- data/test/MC/X86/avx512-encodings.s.cs +12 -0
- data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
- data/test/MC/X86/x86-32-avx.s.cs +833 -0
- data/test/MC/X86/x86-32-fma3.s.cs +169 -0
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
- data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
- data/test/MC/X86/x86_64-encoding.s.cs +59 -0
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
- data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
- data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
- data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
- data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
- data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
- data/test/README +6 -0
- data/test/test.rb +205 -0
- data/test/test.rb.SPEC +235 -0
- data/test/test_arm.rb +202 -0
- data/test/test_arm.rb.SPEC +275 -0
- data/test/test_arm64.rb +150 -0
- data/test/test_arm64.rb.SPEC +116 -0
- data/test/test_detail.rb +228 -0
- data/test/test_detail.rb.SPEC +322 -0
- data/test/test_exhaustive.rb +80 -0
- data/test/test_mips.rb +118 -0
- data/test/test_mips.rb.SPEC +91 -0
- data/test/test_ppc.rb +137 -0
- data/test/test_ppc.rb.SPEC +84 -0
- data/test/test_sanity.rb +83 -0
- data/test/test_skipdata.rb +111 -0
- data/test/test_skipdata.rb.SPEC +58 -0
- data/test/test_sparc.rb +113 -0
- data/test/test_sparc.rb.SPEC +116 -0
- data/test/test_sysz.rb +111 -0
- data/test/test_sysz.rb.SPEC +61 -0
- data/test/test_x86.rb +189 -0
- data/test/test_x86.rb.SPEC +579 -0
- data/test/test_xcore.rb +100 -0
- data/test/test_xcore.rb.SPEC +75 -0
- metadata +393 -0
@@ -0,0 +1,51 @@
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# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
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2
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0xb2,0xee,0xe0,0x3b = vcvtt.f64.f16 d3, s1
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3
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0xf3,0xee,0xcc,0x2b = vcvtt.f16.f64 s5, d12
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4
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0xb2,0xee,0x60,0x3b = vcvtb.f64.f16 d3, s1
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5
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0xb3,0xee,0x41,0x2b = vcvtb.f16.f64 s4, d1
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6
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0xb2,0xee,0xe0,0x3b = vcvttge.f64.f16 d3, s1
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7
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0xf3,0xee,0xcc,0x2b = vcvttgt.f16.f64 s5, d12
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8
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0xb2,0xee,0x60,0x3b = vcvtbeq.f64.f16 d3, s1
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9
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0xb3,0xee,0x41,0x2b = vcvtblt.f16.f64 s4, d1
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10
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0xbc,0xfe,0xe1,0x1a = vcvta.s32.f32 s2, s3
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11
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0xbc,0xfe,0xc3,0x1b = vcvta.s32.f64 s2, d3
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12
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0xbd,0xfe,0xeb,0x3a = vcvtn.s32.f32 s6, s23
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13
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+
0xbd,0xfe,0xe7,0x3b = vcvtn.s32.f64 s6, d23
|
14
|
+
0xbe,0xfe,0xc2,0x0a = vcvtp.s32.f32 s0, s4
|
15
|
+
0xbe,0xfe,0xc4,0x0b = vcvtp.s32.f64 s0, d4
|
16
|
+
0xff,0xfe,0xc4,0x8a = vcvtm.s32.f32 s17, s8
|
17
|
+
0xff,0xfe,0xc8,0x8b = vcvtm.s32.f64 s17, d8
|
18
|
+
0xbc,0xfe,0x61,0x1a = vcvta.u32.f32 s2, s3
|
19
|
+
0xbc,0xfe,0x43,0x1b = vcvta.u32.f64 s2, d3
|
20
|
+
0xbd,0xfe,0x6b,0x3a = vcvtn.u32.f32 s6, s23
|
21
|
+
0xbd,0xfe,0x67,0x3b = vcvtn.u32.f64 s6, d23
|
22
|
+
0xbe,0xfe,0x42,0x0a = vcvtp.u32.f32 s0, s4
|
23
|
+
0xbe,0xfe,0x44,0x0b = vcvtp.u32.f64 s0, d4
|
24
|
+
0xff,0xfe,0x44,0x8a = vcvtm.u32.f32 s17, s8
|
25
|
+
0xff,0xfe,0x48,0x8b = vcvtm.u32.f64 s17, d8
|
26
|
+
0x20,0xfe,0xab,0x2a = vselge.f32 s4, s1, s23
|
27
|
+
0x6f,0xfe,0xa7,0xeb = vselge.f64 d30, d31, d23
|
28
|
+
0x30,0xfe,0x80,0x0a = vselgt.f32 s0, s1, s0
|
29
|
+
0x3a,0xfe,0x24,0x5b = vselgt.f64 d5, d10, d20
|
30
|
+
0x0e,0xfe,0x2b,0xfa = vseleq.f32 s30, s28, s23
|
31
|
+
0x04,0xfe,0x08,0x2b = vseleq.f64 d2, d4, d8
|
32
|
+
0x58,0xfe,0x07,0xaa = vselvs.f32 s21, s16, s14
|
33
|
+
0x11,0xfe,0x2f,0x0b = vselvs.f64 d0, d1, d31
|
34
|
+
0xc6,0xfe,0x00,0x2a = vmaxnm.f32 s5, s12, s0
|
35
|
+
0x86,0xfe,0xae,0x5b = vmaxnm.f64 d5, d22, d30
|
36
|
+
0x80,0xfe,0x46,0x0a = vminnm.f32 s0, s0, s12
|
37
|
+
0x86,0xfe,0x49,0x4b = vminnm.f64 d4, d6, d9
|
38
|
+
0xb6,0xee,0xcc,0x3b = vrintzge.f64 d3, d12
|
39
|
+
0xf6,0xee,0xcc,0x1a = vrintz.f32 s3, s24
|
40
|
+
0xb6,0xee,0x40,0x5b = vrintrlt.f64 d5, d0
|
41
|
+
0xb6,0xee,0x64,0x0a = vrintr.f32 s0, s9
|
42
|
+
0xf7,0xee,0x6e,0xcb = vrintxeq.f64 d28, d30
|
43
|
+
0xb7,0xee,0x47,0x5a = vrintxvs.f32 s10, s14
|
44
|
+
0xb8,0xfe,0x44,0x3b = vrinta.f64 d3, d4
|
45
|
+
0xb8,0xfe,0x60,0x6a = vrinta.f32 s12, s1
|
46
|
+
0xb9,0xfe,0x44,0x3b = vrintn.f64 d3, d4
|
47
|
+
0xb9,0xfe,0x60,0x6a = vrintn.f32 s12, s1
|
48
|
+
0xba,0xfe,0x44,0x3b = vrintp.f64 d3, d4
|
49
|
+
0xba,0xfe,0x60,0x6a = vrintp.f32 s12, s1
|
50
|
+
0xbb,0xfe,0x44,0x3b = vrintm.f64 d3, d4
|
51
|
+
0xbb,0xfe,0x60,0x6a = vrintm.f32 s12, s1
|
@@ -0,0 +1,12 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB,
|
2
|
+
0x00,0xbf = nop
|
3
|
+
0x10,0xbf = yield
|
4
|
+
0x20,0xbf = wfe
|
5
|
+
0x30,0xbf = wfi
|
6
|
+
0x40,0xbf = sev
|
7
|
+
0xbf,0xf3,0x5f,0x8f = dmb sy
|
8
|
+
0xbf,0xf3,0x5f,0x8f = dmb sy
|
9
|
+
0xbf,0xf3,0x4f,0x8f = dsb sy
|
10
|
+
0xbf,0xf3,0x4f,0x8f = dsb sy
|
11
|
+
0xbf,0xf3,0x6f,0x8f = isb sy
|
12
|
+
0xbf,0xf3,0x6f,0x8f = isb sy
|
@@ -0,0 +1,16 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
|
2
|
+
0xb0,0xff,0x42,0x03 = aesd.8 q0, q1
|
3
|
+
0xb0,0xff,0x02,0x03 = aese.8 q0, q1
|
4
|
+
0xb0,0xff,0xc2,0x03 = aesimc.8 q0, q1
|
5
|
+
0xb0,0xff,0x82,0x03 = aesmc.8 q0, q1
|
6
|
+
0xb9,0xff,0xc2,0x02 = sha1h.32 q0, q1
|
7
|
+
0xba,0xff,0x82,0x03 = sha1su1.32 q0, q1
|
8
|
+
0xba,0xff,0xc2,0x03 = sha256su0.32 q0, q1
|
9
|
+
0x02,0xef,0x44,0x0c = sha1c.32 q0, q1, q2
|
10
|
+
0x22,0xef,0x44,0x0c = sha1m.32 q0, q1, q2
|
11
|
+
0x12,0xef,0x44,0x0c = sha1p.32 q0, q1, q2
|
12
|
+
0x32,0xef,0x44,0x0c = sha1su0.32 q0, q1, q2
|
13
|
+
0x02,0xff,0x44,0x0c = sha256h.32 q0, q1, q2
|
14
|
+
0x12,0xff,0x44,0x0c = sha256h2.32 q0, q1, q2
|
15
|
+
0x22,0xff,0x44,0x0c = sha256su1.32 q0, q1, q2
|
16
|
+
0xe0,0xef,0xa1,0x0e = vmull.p64 q8, d16, d17
|
@@ -0,0 +1,38 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
|
2
|
+
0x05,0xff,0x11,0x4f = vmaxnm.f32 d4, d5, d1
|
3
|
+
0x08,0xff,0x5c,0x4f = vmaxnm.f32 q2, q4, q6
|
4
|
+
0x24,0xff,0x3e,0x5f = vminnm.f32 d5, d4, d30
|
5
|
+
0x2a,0xff,0xd4,0x0f = vminnm.f32 q0, q13, q2
|
6
|
+
0xbb,0xff,0x06,0x40 = vcvta.s32.f32 d4, d6
|
7
|
+
0xbb,0xff,0x8a,0xc0 = vcvta.u32.f32 d12, d10
|
8
|
+
0xbb,0xff,0x4c,0x80 = vcvta.s32.f32 q4, q6
|
9
|
+
0xbb,0xff,0xe4,0x80 = vcvta.u32.f32 q4, q10
|
10
|
+
0xbb,0xff,0x2e,0x13 = vcvtm.s32.f32 d1, d30
|
11
|
+
0xbb,0xff,0x8a,0xc3 = vcvtm.u32.f32 d12, d10
|
12
|
+
0xbb,0xff,0x64,0x23 = vcvtm.s32.f32 q1, q10
|
13
|
+
0xfb,0xff,0xc2,0xa3 = vcvtm.u32.f32 q13, q1
|
14
|
+
0xbb,0xff,0x21,0xf1 = vcvtn.s32.f32 d15, d17
|
15
|
+
0xbb,0xff,0x83,0x51 = vcvtn.u32.f32 d5, d3
|
16
|
+
0xbb,0xff,0x60,0x61 = vcvtn.s32.f32 q3, q8
|
17
|
+
0xbb,0xff,0xc6,0xa1 = vcvtn.u32.f32 q5, q3
|
18
|
+
0xbb,0xff,0x25,0xb2 = vcvtp.s32.f32 d11, d21
|
19
|
+
0xbb,0xff,0xa7,0xe2 = vcvtp.u32.f32 d14, d23
|
20
|
+
0xbb,0xff,0x6e,0x82 = vcvtp.s32.f32 q4, q15
|
21
|
+
0xfb,0xff,0xe0,0x22 = vcvtp.u32.f32 q9, q8
|
22
|
+
0xba,0xff,0x00,0x34 = vrintn.f32 d3, d0
|
23
|
+
0xba,0xff,0x48,0x24 = vrintn.f32 q1, q4
|
24
|
+
0xba,0xff,0x8c,0x54 = vrintx.f32 d5, d12
|
25
|
+
0xba,0xff,0xc6,0x04 = vrintx.f32 q0, q3
|
26
|
+
0xba,0xff,0x00,0x35 = vrinta.f32 d3, d0
|
27
|
+
0xfa,0xff,0x44,0x05 = vrinta.f32 q8, q2
|
28
|
+
0xba,0xff,0xa2,0xc5 = vrintz.f32 d12, d18
|
29
|
+
0xfa,0xff,0xc8,0x25 = vrintz.f32 q9, q4
|
30
|
+
0xba,0xff,0x80,0x36 = vrintm.f32 d3, d0
|
31
|
+
0xba,0xff,0xc8,0x26 = vrintm.f32 q1, q4
|
32
|
+
0xba,0xff,0x80,0x37 = vrintp.f32 d3, d0
|
33
|
+
0xba,0xff,0xc8,0x27 = vrintp.f32 q1, q4
|
34
|
+
0xba,0xff,0x00,0x34 = vrintn.f32 d3, d0
|
35
|
+
0xba,0xff,0xc6,0x04 = vrintx.f32 q0, q3
|
36
|
+
0xba,0xff,0x00,0x35 = vrinta.f32 d3, d0
|
37
|
+
0xfa,0xff,0xc8,0x25 = vrintz.f32 q9, q4
|
38
|
+
0xba,0xff,0xc8,0x27 = vrintp.f32 q1, q4
|
@@ -0,0 +1,19 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB,
|
2
|
+
0x6e,0xeb,0x00,0x0c = sbc.w r12, lr, r0
|
3
|
+
0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #32
|
4
|
+
0x67,0xeb,0x1f,0x42 = sbc.w r2, r7, pc, lsr #16
|
5
|
+
0x66,0xeb,0x0a,0x03 = sbc.w r3, r6, r10
|
6
|
+
0x65,0xeb,0x0e,0x44 = sbc.w r4, r5, lr, lsl #16
|
7
|
+
0x64,0xeb,0x2b,0x05 = sbc.w r5, r4, r11, asr #32
|
8
|
+
0x63,0xeb,0x2d,0x46 = sbc.w r6, r3, sp, asr #16
|
9
|
+
0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx
|
10
|
+
0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #16
|
11
|
+
0x0e,0xea,0x00,0x0c = and.w r12, lr, r0
|
12
|
+
0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #32
|
13
|
+
0x07,0xea,0x1f,0x42 = and.w r2, r7, pc, lsr #16
|
14
|
+
0x06,0xea,0x0a,0x03 = and.w r3, r6, r10
|
15
|
+
0x05,0xea,0x0e,0x44 = and.w r4, r5, lr, lsl #16
|
16
|
+
0x04,0xea,0x2b,0x05 = and.w r5, r4, r11, asr #32
|
17
|
+
0x03,0xea,0x2d,0x46 = and.w r6, r3, sp, asr #16
|
18
|
+
0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx
|
19
|
+
0x01,0xea,0x30,0x48 = and.w r8, r1, r0, ror #16
|
@@ -0,0 +1,19 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB,
|
2
|
+
0x91,0x42 = cmp r1, r2
|
3
|
+
0x16,0xbc = pop {r1, r2, r4}
|
4
|
+
0xfe,0xde = trap
|
5
|
+
0xc8,0x47 = blx r9
|
6
|
+
0xd0,0x47 = blx r10
|
7
|
+
0x1a,0xba = rev r2, r3
|
8
|
+
0x63,0xba = rev16 r3, r4
|
9
|
+
0xf5,0xba = revsh r5, r6
|
10
|
+
0x5a,0xb2 = sxtb r2, r3
|
11
|
+
0x1a,0xb2 = sxth r2, r3
|
12
|
+
0x2c,0x42 = tst r4, r5
|
13
|
+
0xf3,0xb2 = uxtb r3, r6
|
14
|
+
0xb3,0xb2 = uxth r3, r6
|
15
|
+
0x8b,0x58 = ldr r3, [r1, r2]
|
16
|
+
0x02,0xbe = bkpt #2
|
17
|
+
0xc0,0x46 = mov r8, r8
|
18
|
+
0x67,0xb6 = cpsie aif
|
19
|
+
0x78,0x46 = mov r0, pc
|
@@ -0,0 +1,85 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB,
|
2
|
+
0x00,0xe4 = b #-2048
|
3
|
+
0xff,0xe3 = b #2046
|
4
|
+
0xff,0xf7,0x00,0xbc = b.w #-2048
|
5
|
+
0x00,0xf0,0xff,0xbb = b.w #2046
|
6
|
+
0x66,0xf6,0x30,0xbc = b.w #-1677216
|
7
|
+
0x99,0xf1,0xcf,0xbb = b.w #1677214
|
8
|
+
0x00,0xe4 = b #-2048
|
9
|
+
0xff,0xe3 = b #2046
|
10
|
+
0xff,0xf7,0xff,0xbb = b.w #-2050
|
11
|
+
0x00,0xf0,0x00,0xbc = b.w #2048
|
12
|
+
0x66,0xf6,0x30,0xbc = b.w #-1677216
|
13
|
+
0x99,0xf1,0xcf,0xbb = b.w #1677214
|
14
|
+
0x08,0xbf = it eq
|
15
|
+
0x00,0xe4 = beq #-2048
|
16
|
+
0x18,0xbf = it ne
|
17
|
+
0x01,0xe4 = bne #-2046
|
18
|
+
0xc8,0xbf = it gt
|
19
|
+
0xff,0xf7,0x00,0xbc = bgt.w #-2048
|
20
|
+
0xd8,0xbf = it le
|
21
|
+
0x00,0xf0,0xff,0xbb = ble.w #2046
|
22
|
+
0xa8,0xbf = it ge
|
23
|
+
0x66,0xf6,0x30,0xbc = bge.w #-1677216
|
24
|
+
0xb8,0xbf = it lt
|
25
|
+
0x99,0xf1,0xcf,0xbb = blt.w #1677214
|
26
|
+
0x80,0xd0 = beq #-256
|
27
|
+
0x7f,0xd1 = bne #254
|
28
|
+
0x3f,0xf5,0x80,0xaf = bmi.w #-256
|
29
|
+
0x40,0xf0,0x7f,0x80 = bne.w #254
|
30
|
+
0xc0,0xf6,0x00,0x80 = blt.w #-1048576
|
31
|
+
0xbf,0xf2,0xff,0xaf = bge.w #1048574
|
32
|
+
0x80,0xd1 = bne #-256
|
33
|
+
0x7f,0xdc = bgt #254
|
34
|
+
0x7f,0xf4,0x7f,0xaf = bne.w #-258
|
35
|
+
0x00,0xf3,0x80,0x80 = bgt.w #256
|
36
|
+
0x40,0xf4,0x00,0x80 = bne.w #-1048576
|
37
|
+
0x3f,0xf3,0xff,0xaf = bgt.w #1048574
|
38
|
+
0x08,0xbf = it eq
|
39
|
+
0x08,0x44 = addeq r0, r1
|
40
|
+
0x40,0xd1 = bne #128
|
41
|
+
0x0c,0xbf = ite eq
|
42
|
+
0x08,0x44 = addeq r0, r1
|
43
|
+
0x40,0xe0 = bne #128
|
44
|
+
0x00,0xe4 = b #-2048
|
45
|
+
0xff,0xe3 = b #2046
|
46
|
+
0xff,0xf7,0x00,0xbc = b.w #-2048
|
47
|
+
0x00,0xf0,0xff,0xbb = b.w #2046
|
48
|
+
0x66,0xf6,0x30,0xbc = b.w #-1677216
|
49
|
+
0x99,0xf1,0xcf,0xbb = b.w #1677214
|
50
|
+
0x00,0xe4 = b #-2048
|
51
|
+
0xff,0xe3 = b #2046
|
52
|
+
0xff,0xf7,0xff,0xbb = b.w #-2050
|
53
|
+
0x00,0xf0,0x00,0xbc = b.w #2048
|
54
|
+
0x66,0xf6,0x30,0xbc = b.w #-1677216
|
55
|
+
0x99,0xf1,0xcf,0xbb = b.w #1677214
|
56
|
+
0x08,0xbf = it eq
|
57
|
+
0x00,0xe4 = beq #-2048
|
58
|
+
0x18,0xbf = it ne
|
59
|
+
0x01,0xe4 = bne #-2046
|
60
|
+
0xc8,0xbf = it gt
|
61
|
+
0xff,0xf7,0x00,0xbc = bgt.w #-2048
|
62
|
+
0xd8,0xbf = it le
|
63
|
+
0x00,0xf0,0xff,0xbb = ble.w #2046
|
64
|
+
0xa8,0xbf = it ge
|
65
|
+
0x66,0xf6,0x30,0xbc = bge.w #-1677216
|
66
|
+
0xb8,0xbf = it lt
|
67
|
+
0x99,0xf1,0xcf,0xbb = blt.w #1677214
|
68
|
+
0x80,0xd0 = beq #-256
|
69
|
+
0x7f,0xd1 = bne #254
|
70
|
+
0x3f,0xf5,0x80,0xaf = bmi.w #-256
|
71
|
+
0x40,0xf0,0x7f,0x80 = bne.w #254
|
72
|
+
0xc0,0xf6,0x00,0x80 = blt.w #-1048576
|
73
|
+
0xbf,0xf2,0xff,0xaf = bge.w #1048574
|
74
|
+
0x80,0xd1 = bne #-256
|
75
|
+
0x7f,0xdc = bgt #254
|
76
|
+
0x7f,0xf4,0x7f,0xaf = bne.w #-258
|
77
|
+
0x00,0xf3,0x80,0x80 = bgt.w #256
|
78
|
+
0x40,0xf4,0x00,0x80 = bne.w #-1048576
|
79
|
+
0x3f,0xf3,0xff,0xaf = bgt.w #1048574
|
80
|
+
0x08,0xbf = it eq
|
81
|
+
0x08,0x44 = addeq r0, r1
|
82
|
+
0x40,0xd1 = bne #128
|
83
|
+
0x0c,0xbf = ite eq
|
84
|
+
0x08,0x44 = addeq r0, r1
|
85
|
+
0x40,0xe0 = bne #128
|
@@ -0,0 +1,41 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None
|
2
|
+
0xef,0xf3,0x00,0x80 = mrs r0, apsr
|
3
|
+
0xef,0xf3,0x01,0x80 = mrs r0, iapsr
|
4
|
+
0xef,0xf3,0x02,0x80 = mrs r0, eapsr
|
5
|
+
0xef,0xf3,0x03,0x80 = mrs r0, xpsr
|
6
|
+
0xef,0xf3,0x05,0x80 = mrs r0, ipsr
|
7
|
+
0xef,0xf3,0x06,0x80 = mrs r0, epsr
|
8
|
+
0xef,0xf3,0x07,0x80 = mrs r0, iepsr
|
9
|
+
0xef,0xf3,0x08,0x80 = mrs r0, msp
|
10
|
+
0xef,0xf3,0x09,0x80 = mrs r0, psp
|
11
|
+
0xef,0xf3,0x10,0x80 = mrs r0, primask
|
12
|
+
0xef,0xf3,0x11,0x80 = mrs r0, basepri
|
13
|
+
0xef,0xf3,0x12,0x80 = mrs r0, basepri_max
|
14
|
+
0xef,0xf3,0x13,0x80 = mrs r0, faultmask
|
15
|
+
0xef,0xf3,0x14,0x80 = mrs r0, control
|
16
|
+
0x80,0xf3,0x00,0x88 = msr apsr, r0
|
17
|
+
0x80,0xf3,0x00,0x88 = msr apsr, r0
|
18
|
+
0x80,0xf3,0x00,0x84 = msr apsr_g, r0
|
19
|
+
0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0
|
20
|
+
0x80,0xf3,0x01,0x88 = msr iapsr, r0
|
21
|
+
0x80,0xf3,0x01,0x88 = msr iapsr, r0
|
22
|
+
0x80,0xf3,0x01,0x84 = msr iapsr_g, r0
|
23
|
+
0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0
|
24
|
+
0x80,0xf3,0x02,0x88 = msr eapsr, r0
|
25
|
+
0x80,0xf3,0x02,0x88 = msr eapsr, r0
|
26
|
+
0x80,0xf3,0x02,0x84 = msr eapsr_g, r0
|
27
|
+
0x80,0xf3,0x02,0x8c = msr eapsr_nzcvqg, r0
|
28
|
+
0x80,0xf3,0x03,0x88 = msr xpsr, r0
|
29
|
+
0x80,0xf3,0x03,0x88 = msr xpsr, r0
|
30
|
+
0x80,0xf3,0x03,0x84 = msr xpsr_g, r0
|
31
|
+
0x80,0xf3,0x03,0x8c = msr xpsr_nzcvqg, r0
|
32
|
+
0x80,0xf3,0x05,0x88 = msr ipsr, r0
|
33
|
+
0x80,0xf3,0x06,0x88 = msr epsr, r0
|
34
|
+
0x80,0xf3,0x07,0x88 = msr iepsr, r0
|
35
|
+
0x80,0xf3,0x08,0x88 = msr msp, r0
|
36
|
+
0x80,0xf3,0x09,0x88 = msr psp, r0
|
37
|
+
0x80,0xf3,0x10,0x88 = msr primask, r0
|
38
|
+
0x80,0xf3,0x11,0x88 = msr basepri, r0
|
39
|
+
0x80,0xf3,0x12,0x88 = msr basepri_max, r0
|
40
|
+
0x80,0xf3,0x13,0x88 = msr faultmask, r0
|
41
|
+
0x80,0xf3,0x14,0x88 = msr control, r0
|
@@ -0,0 +1,379 @@
|
|
1
|
+
# CS_ARCH_ARM, CS_MODE_THUMB,
|
2
|
+
0x12,0xea,0x01,0x00 = ands.w r0, r2, r1
|
3
|
+
0x0a,0x40 = ands r2, r1
|
4
|
+
0x0a,0x40 = ands r2, r1
|
5
|
+
0x10,0xea,0x01,0x00 = ands.w r0, r0, r1
|
6
|
+
0x11,0xea,0x03,0x03 = ands.w r3, r1, r3
|
7
|
+
0x01,0xea,0x00,0x00 = and.w r0, r1, r0
|
8
|
+
0x0f,0x40 = ands r7, r1
|
9
|
+
0x0f,0x40 = ands r7, r1
|
10
|
+
0x11,0xea,0x08,0x08 = ands.w r8, r1, r8
|
11
|
+
0x18,0xea,0x01,0x08 = ands.w r8, r8, r1
|
12
|
+
0x18,0xea,0x00,0x00 = ands.w r0, r8, r0
|
13
|
+
0x11,0xea,0x08,0x01 = ands.w r1, r1, r8
|
14
|
+
0x12,0xea,0x41,0x02 = ands.w r2, r2, r1, lsl #1
|
15
|
+
0x11,0xea,0x50,0x00 = ands.w r0, r1, r0, lsr #1
|
16
|
+
0x08,0xbf = it eq
|
17
|
+
0x02,0xea,0x01,0x00 = andeq.w r0, r2, r1
|
18
|
+
0x08,0xbf = it eq
|
19
|
+
0x0b,0x40 = andeq r3, r1
|
20
|
+
0x08,0xbf = it eq
|
21
|
+
0x0b,0x40 = andeq r3, r1
|
22
|
+
0x08,0xbf = it eq
|
23
|
+
0x00,0xea,0x01,0x00 = andeq.w r0, r0, r1
|
24
|
+
0x08,0xbf = it eq
|
25
|
+
0x01,0xea,0x02,0x02 = andeq.w r2, r1, r2
|
26
|
+
0x08,0xbf = it eq
|
27
|
+
0x11,0xea,0x00,0x00 = andseq.w r0, r1, r0
|
28
|
+
0x08,0xbf = it eq
|
29
|
+
0x0f,0x40 = andeq r7, r1
|
30
|
+
0x08,0xbf = it eq
|
31
|
+
0x0f,0x40 = andeq r7, r1
|
32
|
+
0x08,0xbf = it eq
|
33
|
+
0x01,0xea,0x08,0x08 = andeq.w r8, r1, r8
|
34
|
+
0x08,0xbf = it eq
|
35
|
+
0x08,0xea,0x01,0x08 = andeq.w r8, r8, r1
|
36
|
+
0x08,0xbf = it eq
|
37
|
+
0x08,0xea,0x04,0x04 = andeq.w r4, r8, r4
|
38
|
+
0x08,0xbf = it eq
|
39
|
+
0x04,0xea,0x08,0x04 = andeq.w r4, r4, r8
|
40
|
+
0x08,0xbf = it eq
|
41
|
+
0x00,0xea,0x41,0x00 = andeq.w r0, r0, r1, lsl #1
|
42
|
+
0x08,0xbf = it eq
|
43
|
+
0x01,0xea,0x55,0x05 = andeq.w r5, r1, r5, lsr #1
|
44
|
+
0x92,0xea,0x01,0x00 = eors.w r0, r2, r1
|
45
|
+
0x4d,0x40 = eors r5, r1
|
46
|
+
0x4d,0x40 = eors r5, r1
|
47
|
+
0x90,0xea,0x01,0x00 = eors.w r0, r0, r1
|
48
|
+
0x91,0xea,0x02,0x02 = eors.w r2, r1, r2
|
49
|
+
0x81,0xea,0x01,0x01 = eor.w r1, r1, r1
|
50
|
+
0x4f,0x40 = eors r7, r1
|
51
|
+
0x4f,0x40 = eors r7, r1
|
52
|
+
0x91,0xea,0x08,0x08 = eors.w r8, r1, r8
|
53
|
+
0x98,0xea,0x01,0x08 = eors.w r8, r8, r1
|
54
|
+
0x98,0xea,0x06,0x06 = eors.w r6, r8, r6
|
55
|
+
0x90,0xea,0x08,0x00 = eors.w r0, r0, r8
|
56
|
+
0x92,0xea,0x41,0x02 = eors.w r2, r2, r1, lsl #1
|
57
|
+
0x91,0xea,0x50,0x00 = eors.w r0, r1, r0, lsr #1
|
58
|
+
0x08,0xbf = it eq
|
59
|
+
0x82,0xea,0x01,0x03 = eoreq.w r3, r2, r1
|
60
|
+
0x08,0xbf = it eq
|
61
|
+
0x48,0x40 = eoreq r0, r1
|
62
|
+
0x08,0xbf = it eq
|
63
|
+
0x4a,0x40 = eoreq r2, r1
|
64
|
+
0x08,0xbf = it eq
|
65
|
+
0x83,0xea,0x01,0x03 = eoreq.w r3, r3, r1
|
66
|
+
0x08,0xbf = it eq
|
67
|
+
0x81,0xea,0x00,0x00 = eoreq.w r0, r1, r0
|
68
|
+
0x08,0xbf = it eq
|
69
|
+
0x91,0xea,0x01,0x01 = eorseq.w r1, r1, r1
|
70
|
+
0x08,0xbf = it eq
|
71
|
+
0x4f,0x40 = eoreq r7, r1
|
72
|
+
0x08,0xbf = it eq
|
73
|
+
0x4f,0x40 = eoreq r7, r1
|
74
|
+
0x08,0xbf = it eq
|
75
|
+
0x81,0xea,0x08,0x08 = eoreq.w r8, r1, r8
|
76
|
+
0x08,0xbf = it eq
|
77
|
+
0x88,0xea,0x01,0x08 = eoreq.w r8, r8, r1
|
78
|
+
0x08,0xbf = it eq
|
79
|
+
0x88,0xea,0x00,0x00 = eoreq.w r0, r8, r0
|
80
|
+
0x08,0xbf = it eq
|
81
|
+
0x83,0xea,0x08,0x03 = eoreq.w r3, r3, r8
|
82
|
+
0x08,0xbf = it eq
|
83
|
+
0x84,0xea,0x41,0x04 = eoreq.w r4, r4, r1, lsl #1
|
84
|
+
0x08,0xbf = it eq
|
85
|
+
0x81,0xea,0x50,0x00 = eoreq.w r0, r1, r0, lsr #1
|
86
|
+
0x12,0xfa,0x01,0xf0 = lsls.w r0, r2, r1
|
87
|
+
0x8a,0x40 = lsls r2, r1
|
88
|
+
0x11,0xfa,0x02,0xf2 = lsls.w r2, r1, r2
|
89
|
+
0x10,0xfa,0x01,0xf0 = lsls.w r0, r0, r1
|
90
|
+
0x11,0xfa,0x04,0xf4 = lsls.w r4, r1, r4
|
91
|
+
0x01,0xfa,0x04,0xf4 = lsl.w r4, r1, r4
|
92
|
+
0x8f,0x40 = lsls r7, r1
|
93
|
+
0x11,0xfa,0x08,0xf8 = lsls.w r8, r1, r8
|
94
|
+
0x18,0xfa,0x01,0xf8 = lsls.w r8, r8, r1
|
95
|
+
0x18,0xfa,0x03,0xf3 = lsls.w r3, r8, r3
|
96
|
+
0x15,0xfa,0x08,0xf5 = lsls.w r5, r5, r8
|
97
|
+
0x08,0xbf = it eq
|
98
|
+
0x02,0xfa,0x01,0xf0 = lsleq.w r0, r2, r1
|
99
|
+
0x08,0xbf = it eq
|
100
|
+
0x8a,0x40 = lsleq r2, r1
|
101
|
+
0x08,0xbf = it eq
|
102
|
+
0x01,0xfa,0x02,0xf2 = lsleq.w r2, r1, r2
|
103
|
+
0x08,0xbf = it eq
|
104
|
+
0x00,0xfa,0x01,0xf0 = lsleq.w r0, r0, r1
|
105
|
+
0x08,0xbf = it eq
|
106
|
+
0x01,0xfa,0x03,0xf3 = lsleq.w r3, r1, r3
|
107
|
+
0x08,0xbf = it eq
|
108
|
+
0x11,0xfa,0x04,0xf4 = lslseq.w r4, r1, r4
|
109
|
+
0x08,0xbf = it eq
|
110
|
+
0x8f,0x40 = lsleq r7, r1
|
111
|
+
0x08,0xbf = it eq
|
112
|
+
0x01,0xfa,0x08,0xf8 = lsleq.w r8, r1, r8
|
113
|
+
0x08,0xbf = it eq
|
114
|
+
0x08,0xfa,0x01,0xf8 = lsleq.w r8, r8, r1
|
115
|
+
0x08,0xbf = it eq
|
116
|
+
0x08,0xfa,0x00,0xf0 = lsleq.w r0, r8, r0
|
117
|
+
0x08,0xbf = it eq
|
118
|
+
0x03,0xfa,0x08,0xf3 = lsleq.w r3, r3, r8
|
119
|
+
0x32,0xfa,0x01,0xf6 = lsrs.w r6, r2, r1
|
120
|
+
0xca,0x40 = lsrs r2, r1
|
121
|
+
0x31,0xfa,0x02,0xf2 = lsrs.w r2, r1, r2
|
122
|
+
0x32,0xfa,0x01,0xf2 = lsrs.w r2, r2, r1
|
123
|
+
0x31,0xfa,0x03,0xf3 = lsrs.w r3, r1, r3
|
124
|
+
0x21,0xfa,0x04,0xf4 = lsr.w r4, r1, r4
|
125
|
+
0xcf,0x40 = lsrs r7, r1
|
126
|
+
0x31,0xfa,0x08,0xf8 = lsrs.w r8, r1, r8
|
127
|
+
0x38,0xfa,0x01,0xf8 = lsrs.w r8, r8, r1
|
128
|
+
0x38,0xfa,0x02,0xf2 = lsrs.w r2, r8, r2
|
129
|
+
0x35,0xfa,0x08,0xf5 = lsrs.w r5, r5, r8
|
130
|
+
0x08,0xbf = it eq
|
131
|
+
0x22,0xfa,0x01,0xf6 = lsreq.w r6, r2, r1
|
132
|
+
0x08,0xbf = it eq
|
133
|
+
0xcf,0x40 = lsreq r7, r1
|
134
|
+
0x08,0xbf = it eq
|
135
|
+
0x21,0xfa,0x07,0xf7 = lsreq.w r7, r1, r7
|
136
|
+
0x08,0xbf = it eq
|
137
|
+
0x27,0xfa,0x01,0xf7 = lsreq.w r7, r7, r1
|
138
|
+
0x08,0xbf = it eq
|
139
|
+
0x21,0xfa,0x02,0xf2 = lsreq.w r2, r1, r2
|
140
|
+
0x08,0xbf = it eq
|
141
|
+
0x31,0xfa,0x00,0xf0 = lsrseq.w r0, r1, r0
|
142
|
+
0x08,0xbf = it eq
|
143
|
+
0xcf,0x40 = lsreq r7, r1
|
144
|
+
0x08,0xbf = it eq
|
145
|
+
0x21,0xfa,0x08,0xf8 = lsreq.w r8, r1, r8
|
146
|
+
0x08,0xbf = it eq
|
147
|
+
0x28,0xfa,0x01,0xf8 = lsreq.w r8, r8, r1
|
148
|
+
0x08,0xbf = it eq
|
149
|
+
0x28,0xfa,0x01,0xf1 = lsreq.w r1, r8, r1
|
150
|
+
0x08,0xbf = it eq
|
151
|
+
0x24,0xfa,0x08,0xf4 = lsreq.w r4, r4, r8
|
152
|
+
0x56,0xfa,0x05,0xf7 = asrs.w r7, r6, r5
|
153
|
+
0x08,0x41 = asrs r0, r1
|
154
|
+
0x51,0xfa,0x00,0xf0 = asrs.w r0, r1, r0
|
155
|
+
0x53,0xfa,0x01,0xf3 = asrs.w r3, r3, r1
|
156
|
+
0x51,0xfa,0x01,0xf1 = asrs.w r1, r1, r1
|
157
|
+
0x41,0xfa,0x00,0xf0 = asr.w r0, r1, r0
|
158
|
+
0x0f,0x41 = asrs r7, r1
|
159
|
+
0x51,0xfa,0x08,0xf8 = asrs.w r8, r1, r8
|
160
|
+
0x58,0xfa,0x01,0xf8 = asrs.w r8, r8, r1
|
161
|
+
0x58,0xfa,0x05,0xf5 = asrs.w r5, r8, r5
|
162
|
+
0x55,0xfa,0x08,0xf5 = asrs.w r5, r5, r8
|
163
|
+
0x08,0xbf = it eq
|
164
|
+
0x42,0xfa,0x01,0xf0 = asreq.w r0, r2, r1
|
165
|
+
0x08,0xbf = it eq
|
166
|
+
0x0a,0x41 = asreq r2, r1
|
167
|
+
0x08,0xbf = it eq
|
168
|
+
0x42,0xfa,0x01,0xf1 = asreq.w r1, r2, r1
|
169
|
+
0x08,0xbf = it eq
|
170
|
+
0x44,0xfa,0x01,0xf4 = asreq.w r4, r4, r1
|
171
|
+
0x08,0xbf = it eq
|
172
|
+
0x41,0xfa,0x06,0xf6 = asreq.w r6, r1, r6
|
173
|
+
0x08,0xbf = it eq
|
174
|
+
0x51,0xfa,0x03,0xf3 = asrseq.w r3, r1, r3
|
175
|
+
0x08,0xbf = it eq
|
176
|
+
0x0f,0x41 = asreq r7, r1
|
177
|
+
0x08,0xbf = it eq
|
178
|
+
0x41,0xfa,0x08,0xf8 = asreq.w r8, r1, r8
|
179
|
+
0x08,0xbf = it eq
|
180
|
+
0x48,0xfa,0x01,0xf8 = asreq.w r8, r8, r1
|
181
|
+
0x08,0xbf = it eq
|
182
|
+
0x48,0xfa,0x01,0xf1 = asreq.w r1, r8, r1
|
183
|
+
0x08,0xbf = it eq
|
184
|
+
0x43,0xfa,0x08,0xf3 = asreq.w r3, r3, r8
|
185
|
+
0x52,0xeb,0x01,0x05 = adcs.w r5, r2, r1
|
186
|
+
0x4d,0x41 = adcs r5, r1
|
187
|
+
0x4b,0x41 = adcs r3, r1
|
188
|
+
0x52,0xeb,0x01,0x02 = adcs.w r2, r2, r1
|
189
|
+
0x51,0xeb,0x03,0x03 = adcs.w r3, r1, r3
|
190
|
+
0x41,0xeb,0x00,0x00 = adc.w r0, r1, r0
|
191
|
+
0x4f,0x41 = adcs r7, r1
|
192
|
+
0x4f,0x41 = adcs r7, r1
|
193
|
+
0x51,0xeb,0x08,0x08 = adcs.w r8, r1, r8
|
194
|
+
0x58,0xeb,0x01,0x08 = adcs.w r8, r8, r1
|
195
|
+
0x58,0xeb,0x05,0x05 = adcs.w r5, r8, r5
|
196
|
+
0x52,0xeb,0x08,0x02 = adcs.w r2, r2, r8
|
197
|
+
0x53,0xeb,0x41,0x03 = adcs.w r3, r3, r1, lsl #1
|
198
|
+
0x51,0xeb,0x54,0x04 = adcs.w r4, r1, r4, lsr #1
|
199
|
+
0x08,0xbf = it eq
|
200
|
+
0x42,0xeb,0x03,0x01 = adceq.w r1, r2, r3
|
201
|
+
0x08,0xbf = it eq
|
202
|
+
0x49,0x41 = adceq r1, r1
|
203
|
+
0x08,0xbf = it eq
|
204
|
+
0x4b,0x41 = adceq r3, r1
|
205
|
+
0x08,0xbf = it eq
|
206
|
+
0x43,0xeb,0x01,0x03 = adceq.w r3, r3, r1
|
207
|
+
0x08,0xbf = it eq
|
208
|
+
0x41,0xeb,0x00,0x00 = adceq.w r0, r1, r0
|
209
|
+
0x08,0xbf = it eq
|
210
|
+
0x51,0xeb,0x03,0x03 = adcseq.w r3, r1, r3
|
211
|
+
0x08,0xbf = it eq
|
212
|
+
0x4f,0x41 = adceq r7, r1
|
213
|
+
0x08,0xbf = it eq
|
214
|
+
0x4f,0x41 = adceq r7, r1
|
215
|
+
0x08,0xbf = it eq
|
216
|
+
0x41,0xeb,0x08,0x08 = adceq.w r8, r1, r8
|
217
|
+
0x08,0xbf = it eq
|
218
|
+
0x48,0xeb,0x01,0x08 = adceq.w r8, r8, r1
|
219
|
+
0x08,0xbf = it eq
|
220
|
+
0x48,0xeb,0x03,0x03 = adceq.w r3, r8, r3
|
221
|
+
0x08,0xbf = it eq
|
222
|
+
0x41,0xeb,0x08,0x01 = adceq.w r1, r1, r8
|
223
|
+
0x08,0xbf = it eq
|
224
|
+
0x42,0xeb,0x41,0x02 = adceq.w r2, r2, r1, lsl #1
|
225
|
+
0x08,0xbf = it eq
|
226
|
+
0x41,0xeb,0x51,0x01 = adceq.w r1, r1, r1, lsr #1
|
227
|
+
0x72,0xeb,0x01,0x03 = sbcs.w r3, r2, r1
|
228
|
+
0x8c,0x41 = sbcs r4, r1
|
229
|
+
0x74,0xeb,0x01,0x01 = sbcs.w r1, r4, r1
|
230
|
+
0x74,0xeb,0x01,0x04 = sbcs.w r4, r4, r1
|
231
|
+
0x71,0xeb,0x02,0x02 = sbcs.w r2, r1, r2
|
232
|
+
0x61,0xeb,0x00,0x00 = sbc.w r0, r1, r0
|
233
|
+
0x8f,0x41 = sbcs r7, r1
|
234
|
+
0x71,0xeb,0x08,0x08 = sbcs.w r8, r1, r8
|
235
|
+
0x78,0xeb,0x01,0x08 = sbcs.w r8, r8, r1
|
236
|
+
0x78,0xeb,0x04,0x04 = sbcs.w r4, r8, r4
|
237
|
+
0x73,0xeb,0x08,0x03 = sbcs.w r3, r3, r8
|
238
|
+
0x72,0xeb,0x41,0x02 = sbcs.w r2, r2, r1, lsl #1
|
239
|
+
0x71,0xeb,0x55,0x05 = sbcs.w r5, r1, r5, lsr #1
|
240
|
+
0x08,0xbf = it eq
|
241
|
+
0x62,0xeb,0x01,0x05 = sbceq.w r5, r2, r1
|
242
|
+
0x08,0xbf = it eq
|
243
|
+
0x8d,0x41 = sbceq r5, r1
|
244
|
+
0x08,0xbf = it eq
|
245
|
+
0x65,0xeb,0x01,0x01 = sbceq.w r1, r5, r1
|
246
|
+
0x08,0xbf = it eq
|
247
|
+
0x65,0xeb,0x01,0x05 = sbceq.w r5, r5, r1
|
248
|
+
0x08,0xbf = it eq
|
249
|
+
0x61,0xeb,0x00,0x00 = sbceq.w r0, r1, r0
|
250
|
+
0x08,0xbf = it eq
|
251
|
+
0x71,0xeb,0x02,0x02 = sbcseq.w r2, r1, r2
|
252
|
+
0x08,0xbf = it eq
|
253
|
+
0x8f,0x41 = sbceq r7, r1
|
254
|
+
0x08,0xbf = it eq
|
255
|
+
0x61,0xeb,0x08,0x08 = sbceq.w r8, r1, r8
|
256
|
+
0x08,0xbf = it eq
|
257
|
+
0x68,0xeb,0x01,0x08 = sbceq.w r8, r8, r1
|
258
|
+
0x08,0xbf = it eq
|
259
|
+
0x68,0xeb,0x07,0x07 = sbceq.w r7, r8, r7
|
260
|
+
0x08,0xbf = it eq
|
261
|
+
0x67,0xeb,0x08,0x07 = sbceq.w r7, r7, r8
|
262
|
+
0x08,0xbf = it eq
|
263
|
+
0x62,0xeb,0x41,0x02 = sbceq.w r2, r2, r1, lsl #1
|
264
|
+
0x08,0xbf = it eq
|
265
|
+
0x61,0xeb,0x55,0x05 = sbceq.w r5, r1, r5, lsr #1
|
266
|
+
0x72,0xfa,0x01,0xf3 = rors.w r3, r2, r1
|
267
|
+
0xc8,0x41 = rors r0, r1
|
268
|
+
0x70,0xfa,0x01,0xf1 = rors.w r1, r0, r1
|
269
|
+
0x72,0xfa,0x01,0xf2 = rors.w r2, r2, r1
|
270
|
+
0x71,0xfa,0x02,0xf2 = rors.w r2, r1, r2
|
271
|
+
0x61,0xfa,0x05,0xf5 = ror.w r5, r1, r5
|
272
|
+
0xcf,0x41 = rors r7, r1
|
273
|
+
0x71,0xfa,0x08,0xf8 = rors.w r8, r1, r8
|
274
|
+
0x78,0xfa,0x01,0xf8 = rors.w r8, r8, r1
|
275
|
+
0x78,0xfa,0x06,0xf6 = rors.w r6, r8, r6
|
276
|
+
0x76,0xfa,0x08,0xf6 = rors.w r6, r6, r8
|
277
|
+
0x08,0xbf = it eq
|
278
|
+
0x62,0xfa,0x01,0xf4 = roreq.w r4, r2, r1
|
279
|
+
0x08,0xbf = it eq
|
280
|
+
0xcc,0x41 = roreq r4, r1
|
281
|
+
0x08,0xbf = it eq
|
282
|
+
0x64,0xfa,0x01,0xf1 = roreq.w r1, r4, r1
|
283
|
+
0x08,0xbf = it eq
|
284
|
+
0x64,0xfa,0x01,0xf4 = roreq.w r4, r4, r1
|
285
|
+
0x08,0xbf = it eq
|
286
|
+
0x61,0xfa,0x00,0xf0 = roreq.w r0, r1, r0
|
287
|
+
0x08,0xbf = it eq
|
288
|
+
0x71,0xfa,0x00,0xf0 = rorseq.w r0, r1, r0
|
289
|
+
0x08,0xbf = it eq
|
290
|
+
0xcf,0x41 = roreq r7, r1
|
291
|
+
0x08,0xbf = it eq
|
292
|
+
0x61,0xfa,0x08,0xf8 = roreq.w r8, r1, r8
|
293
|
+
0x08,0xbf = it eq
|
294
|
+
0x68,0xfa,0x01,0xf8 = roreq.w r8, r8, r1
|
295
|
+
0x08,0xbf = it eq
|
296
|
+
0x68,0xfa,0x03,0xf3 = roreq.w r3, r8, r3
|
297
|
+
0x08,0xbf = it eq
|
298
|
+
0x61,0xfa,0x08,0xf1 = roreq.w r1, r1, r8
|
299
|
+
0x52,0xea,0x01,0x07 = orrs.w r7, r2, r1
|
300
|
+
0x0a,0x43 = orrs r2, r1
|
301
|
+
0x0b,0x43 = orrs r3, r1
|
302
|
+
0x54,0xea,0x01,0x04 = orrs.w r4, r4, r1
|
303
|
+
0x51,0xea,0x05,0x05 = orrs.w r5, r1, r5
|
304
|
+
0x41,0xea,0x02,0x02 = orr.w r2, r1, r2
|
305
|
+
0x0f,0x43 = orrs r7, r1
|
306
|
+
0x0f,0x43 = orrs r7, r1
|
307
|
+
0x51,0xea,0x08,0x08 = orrs.w r8, r1, r8
|
308
|
+
0x58,0xea,0x01,0x08 = orrs.w r8, r8, r1
|
309
|
+
0x58,0xea,0x01,0x01 = orrs.w r1, r8, r1
|
310
|
+
0x50,0xea,0x08,0x00 = orrs.w r0, r0, r8
|
311
|
+
0x51,0xea,0x41,0x01 = orrs.w r1, r1, r1, lsl #1
|
312
|
+
0x51,0xea,0x50,0x00 = orrs.w r0, r1, r0, lsr #1
|
313
|
+
0x08,0xbf = it eq
|
314
|
+
0x42,0xea,0x01,0x00 = orreq.w r0, r2, r1
|
315
|
+
0x08,0xbf = it eq
|
316
|
+
0x0d,0x43 = orreq r5, r1
|
317
|
+
0x08,0xbf = it eq
|
318
|
+
0x0d,0x43 = orreq r5, r1
|
319
|
+
0x08,0xbf = it eq
|
320
|
+
0x42,0xea,0x01,0x02 = orreq.w r2, r2, r1
|
321
|
+
0x08,0xbf = it eq
|
322
|
+
0x41,0xea,0x03,0x03 = orreq.w r3, r1, r3
|
323
|
+
0x08,0xbf = it eq
|
324
|
+
0x51,0xea,0x04,0x04 = orrseq.w r4, r1, r4
|
325
|
+
0x08,0xbf = it eq
|
326
|
+
0x0f,0x43 = orreq r7, r1
|
327
|
+
0x08,0xbf = it eq
|
328
|
+
0x0f,0x43 = orreq r7, r1
|
329
|
+
0x08,0xbf = it eq
|
330
|
+
0x41,0xea,0x08,0x08 = orreq.w r8, r1, r8
|
331
|
+
0x08,0xbf = it eq
|
332
|
+
0x48,0xea,0x01,0x08 = orreq.w r8, r8, r1
|
333
|
+
0x08,0xbf = it eq
|
334
|
+
0x48,0xea,0x00,0x00 = orreq.w r0, r8, r0
|
335
|
+
0x08,0xbf = it eq
|
336
|
+
0x40,0xea,0x08,0x00 = orreq.w r0, r0, r8
|
337
|
+
0x08,0xbf = it eq
|
338
|
+
0x42,0xea,0x41,0x02 = orreq.w r2, r2, r1, lsl #1
|
339
|
+
0x08,0xbf = it eq
|
340
|
+
0x41,0xea,0x52,0x02 = orreq.w r2, r1, r2, lsr #1
|
341
|
+
0x32,0xea,0x01,0x03 = bics.w r3, r2, r1
|
342
|
+
0x8a,0x43 = bics r2, r1
|
343
|
+
0x32,0xea,0x01,0x01 = bics.w r1, r2, r1
|
344
|
+
0x32,0xea,0x01,0x02 = bics.w r2, r2, r1
|
345
|
+
0x31,0xea,0x00,0x00 = bics.w r0, r1, r0
|
346
|
+
0x21,0xea,0x00,0x00 = bic.w r0, r1, r0
|
347
|
+
0x8f,0x43 = bics r7, r1
|
348
|
+
0x31,0xea,0x08,0x08 = bics.w r8, r1, r8
|
349
|
+
0x38,0xea,0x01,0x08 = bics.w r8, r8, r1
|
350
|
+
0x38,0xea,0x07,0x07 = bics.w r7, r8, r7
|
351
|
+
0x35,0xea,0x08,0x05 = bics.w r5, r5, r8
|
352
|
+
0x33,0xea,0x41,0x03 = bics.w r3, r3, r1, lsl #1
|
353
|
+
0x31,0xea,0x54,0x04 = bics.w r4, r1, r4, lsr #1
|
354
|
+
0x08,0xbf = it eq
|
355
|
+
0x22,0xea,0x01,0x00 = biceq.w r0, r2, r1
|
356
|
+
0x08,0xbf = it eq
|
357
|
+
0x8d,0x43 = biceq r5, r1
|
358
|
+
0x08,0xbf = it eq
|
359
|
+
0x25,0xea,0x01,0x01 = biceq.w r1, r5, r1
|
360
|
+
0x08,0xbf = it eq
|
361
|
+
0x24,0xea,0x01,0x04 = biceq.w r4, r4, r1
|
362
|
+
0x08,0xbf = it eq
|
363
|
+
0x21,0xea,0x02,0x02 = biceq.w r2, r1, r2
|
364
|
+
0x08,0xbf = it eq
|
365
|
+
0x31,0xea,0x05,0x05 = bicseq.w r5, r1, r5
|
366
|
+
0x08,0xbf = it eq
|
367
|
+
0x8f,0x43 = biceq r7, r1
|
368
|
+
0x08,0xbf = it eq
|
369
|
+
0x21,0xea,0x08,0x08 = biceq.w r8, r1, r8
|
370
|
+
0x08,0xbf = it eq
|
371
|
+
0x28,0xea,0x01,0x08 = biceq.w r8, r8, r1
|
372
|
+
0x08,0xbf = it eq
|
373
|
+
0x28,0xea,0x00,0x00 = biceq.w r0, r8, r0
|
374
|
+
0x08,0xbf = it eq
|
375
|
+
0x22,0xea,0x08,0x02 = biceq.w r2, r2, r8
|
376
|
+
0x08,0xbf = it eq
|
377
|
+
0x24,0xea,0x41,0x04 = biceq.w r4, r4, r1, lsl #1
|
378
|
+
0x08,0xbf = it eq
|
379
|
+
0x21,0xea,0x55,0x05 = biceq.w r5, r1, r5, lsr #1
|