crabstone 3.0.3 → 4.0.0
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- checksums.yaml +5 -5
- data/CHANGES.md +45 -42
- data/README.md +16 -33
- data/lib/crabstone.rb +5 -557
- data/lib/crabstone/arch.rb +37 -0
- data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
- data/lib/crabstone/arch/3/arm64.rb +124 -0
- data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
- data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
- data/lib/crabstone/arch/3/mips.rb +57 -0
- data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
- data/lib/crabstone/arch/3/ppc.rb +73 -0
- data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
- data/lib/crabstone/arch/3/sparc.rb +60 -0
- data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
- data/lib/crabstone/arch/3/sysz.rb +67 -0
- data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
- data/lib/crabstone/arch/3/x86.rb +82 -0
- data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
- data/lib/crabstone/arch/3/xcore.rb +59 -0
- data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
- data/lib/crabstone/arch/4/arm.rb +110 -0
- data/lib/crabstone/arch/4/arm64.rb +125 -0
- data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
- data/lib/crabstone/arch/4/arm_const.rb +785 -0
- data/lib/crabstone/arch/4/evm.rb +20 -0
- data/lib/crabstone/arch/4/evm_const.rb +161 -0
- data/lib/crabstone/arch/4/m680x.rb +106 -0
- data/lib/crabstone/arch/4/m680x_const.rb +426 -0
- data/lib/crabstone/arch/4/m68k.rb +129 -0
- data/lib/crabstone/arch/4/m68k_const.rb +496 -0
- data/lib/crabstone/arch/4/mips.rb +57 -0
- data/lib/crabstone/arch/4/mips_const.rb +869 -0
- data/lib/crabstone/arch/4/ppc.rb +73 -0
- data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
- data/lib/crabstone/arch/4/sparc.rb +60 -0
- data/lib/crabstone/arch/4/sparc_const.rb +439 -0
- data/lib/crabstone/arch/4/sysz.rb +67 -0
- data/lib/crabstone/arch/4/sysz_const.rb +763 -0
- data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
- data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
- data/lib/crabstone/arch/4/x86.rb +91 -0
- data/lib/crabstone/arch/4/x86_const.rb +1972 -0
- data/lib/crabstone/arch/4/xcore.rb +59 -0
- data/lib/crabstone/arch/4/xcore_const.rb +171 -0
- data/lib/crabstone/arch/extension.rb +27 -0
- data/lib/crabstone/arch/register.rb +36 -0
- data/lib/crabstone/binding.rb +60 -0
- data/lib/crabstone/binding/3/detail.rb +36 -0
- data/lib/crabstone/binding/3/instruction.rb +23 -0
- data/lib/crabstone/binding/4/detail.rb +40 -0
- data/lib/crabstone/binding/4/instruction.rb +23 -0
- data/lib/crabstone/binding/structs.rb +32 -0
- data/lib/crabstone/constants.rb +110 -0
- data/lib/crabstone/cs_version.rb +49 -0
- data/lib/crabstone/disassembler.rb +153 -0
- data/lib/crabstone/error.rb +60 -0
- data/lib/crabstone/instruction.rb +183 -0
- data/lib/crabstone/version.rb +5 -0
- metadata +128 -324
- data/MANIFEST +0 -312
- data/Rakefile +0 -27
- data/bin/genconst +0 -66
- data/bin/genreg +0 -99
- data/crabstone.gemspec +0 -27
- data/examples/hello_world.rb +0 -43
- data/lib/arch/arm64.rb +0 -167
- data/lib/arch/arm64_registers.rb +0 -295
- data/lib/arch/arm_registers.rb +0 -149
- data/lib/arch/mips.rb +0 -78
- data/lib/arch/mips_registers.rb +0 -208
- data/lib/arch/ppc.rb +0 -90
- data/lib/arch/ppc_registers.rb +0 -209
- data/lib/arch/sparc.rb +0 -79
- data/lib/arch/sparc_registers.rb +0 -121
- data/lib/arch/systemz.rb +0 -79
- data/lib/arch/sysz_registers.rb +0 -66
- data/lib/arch/x86.rb +0 -107
- data/lib/arch/x86_registers.rb +0 -265
- data/lib/arch/xcore.rb +0 -78
- data/lib/arch/xcore_registers.rb +0 -57
- data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
- data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
- data/test/MC/AArch64/neon-2velem.s.cs +0 -113
- data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
- data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
- data/test/MC/AArch64/neon-across.s.cs +0 -40
- data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
- data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
- data/test/MC/AArch64/neon-crypto.s.cs +0 -15
- data/test/MC/AArch64/neon-extract.s.cs +0 -3
- data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
- data/test/MC/AArch64/neon-max-min.s.cs +0 -37
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
- data/test/MC/AArch64/neon-mov.s.cs +0 -74
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
- data/test/MC/AArch64/neon-perm.s.cs +0 -43
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
- data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
- data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
- data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
- data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
- data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
- data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
- data/test/MC/AArch64/neon-shift.s.cs +0 -22
- data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
- data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
- data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
- data/test/MC/AArch64/neon-tbl.s.cs +0 -21
- data/test/MC/AArch64/trace-regs.s.cs +0 -383
- data/test/MC/ARM/arm-aliases.s.cs +0 -7
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
- data/test/MC/ARM/arm-it-block.s.cs +0 -2
- data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
- data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
- data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
- data/test/MC/ARM/arm_instructions.s.cs +0 -25
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
- data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
- data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
- data/test/MC/ARM/crc32-thumb.s.cs +0 -7
- data/test/MC/ARM/crc32.s.cs +0 -7
- data/test/MC/ARM/dot-req.s.cs +0 -3
- data/test/MC/ARM/fp-armv8.s.cs +0 -52
- data/test/MC/ARM/idiv-thumb.s.cs +0 -3
- data/test/MC/ARM/idiv.s.cs +0 -3
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
- data/test/MC/ARM/mode-switch.s.cs +0 -7
- data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
- data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
- data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
- data/test/MC/ARM/neon-crypto.s.cs +0 -16
- data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
- data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
- data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
- data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neon-v8.s.cs +0 -38
- data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
- data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
- data/test/MC/ARM/neon-vswp.s.cs +0 -3
- data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
- data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
- data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
- data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
- data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
- data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
- data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
- data/test/MC/ARM/thumb-hints.s.cs +0 -12
- data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
- data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
- data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
- data/test/MC/ARM/thumb.s.cs +0 -19
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
- data/test/MC/ARM/thumb2-branches.s.cs +0 -85
- data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
- data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
- data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
- data/test/MC/ARM/vfp4.s.cs +0 -13
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
- data/test/MC/ARM/vpush-vpop.s.cs +0 -9
- data/test/MC/Mips/hilo-addressing.s.cs +0 -4
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
- data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
- data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
- data/test/MC/Mips/micromips-expansions.s.cs +0 -20
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
- data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
- data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
- data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
- data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
- data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
- data/test/MC/Mips/mips-expansions.s.cs +0 -20
- data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
- data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
- data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
- data/test/MC/Mips/mips-register-names.s.cs +0 -33
- data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
- data/test/MC/Mips/mips64-instructions.s.cs +0 -3
- data/test/MC/Mips/mips64-register-names.s.cs +0 -33
- data/test/MC/Mips/mips_directives.s.cs +0 -12
- data/test/MC/Mips/nabi-regs.s.cs +0 -12
- data/test/MC/Mips/set-at-directive.s.cs +0 -6
- data/test/MC/Mips/test_2r.s.cs +0 -16
- data/test/MC/Mips/test_2rf.s.cs +0 -33
- data/test/MC/Mips/test_3r.s.cs +0 -243
- data/test/MC/Mips/test_3rf.s.cs +0 -83
- data/test/MC/Mips/test_bit.s.cs +0 -49
- data/test/MC/Mips/test_cbranch.s.cs +0 -11
- data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
- data/test/MC/Mips/test_elm.s.cs +0 -16
- data/test/MC/Mips/test_elm_insert.s.cs +0 -4
- data/test/MC/Mips/test_elm_insve.s.cs +0 -5
- data/test/MC/Mips/test_i10.s.cs +0 -5
- data/test/MC/Mips/test_i5.s.cs +0 -45
- data/test/MC/Mips/test_i8.s.cs +0 -11
- data/test/MC/Mips/test_lsa.s.cs +0 -5
- data/test/MC/Mips/test_mi10.s.cs +0 -24
- data/test/MC/Mips/test_vec.s.cs +0 -8
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
- data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
- data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
- data/test/MC/README +0 -6
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
- data/test/MC/Sparc/sparc-vis.s.cs +0 -2
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
- data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
- data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
- data/test/MC/SystemZ/insn-good.s.cs +0 -2265
- data/test/MC/SystemZ/regs-good.s.cs +0 -45
- data/test/MC/X86/3DNow.s.cs +0 -29
- data/test/MC/X86/address-size.s.cs +0 -5
- data/test/MC/X86/avx512-encodings.s.cs +0 -12
- data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
- data/test/MC/X86/x86-32-avx.s.cs +0 -833
- data/test/MC/X86/x86-32-fma3.s.cs +0 -169
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
- data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
- data/test/MC/X86/x86_64-encoding.s.cs +0 -59
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
- data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
- data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
- data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
- data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
- data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
- data/test/README +0 -6
- data/test/test.rb +0 -205
- data/test/test.rb.SPEC +0 -235
- data/test/test_arm.rb +0 -202
- data/test/test_arm.rb.SPEC +0 -275
- data/test/test_arm64.rb +0 -150
- data/test/test_arm64.rb.SPEC +0 -116
- data/test/test_detail.rb +0 -228
- data/test/test_detail.rb.SPEC +0 -322
- data/test/test_exhaustive.rb +0 -80
- data/test/test_mips.rb +0 -118
- data/test/test_mips.rb.SPEC +0 -91
- data/test/test_ppc.rb +0 -137
- data/test/test_ppc.rb.SPEC +0 -84
- data/test/test_sanity.rb +0 -83
- data/test/test_skipdata.rb +0 -111
- data/test/test_skipdata.rb.SPEC +0 -58
- data/test/test_sparc.rb +0 -113
- data/test/test_sparc.rb.SPEC +0 -116
- data/test/test_sysz.rb +0 -111
- data/test/test_sysz.rb.SPEC +0 -61
- data/test/test_x86.rb +0 -189
- data/test/test_x86.rb.SPEC +0 -579
- data/test/test_xcore.rb +0 -100
- data/test/test_xcore.rb.SPEC +0 -75
@@ -0,0 +1,57 @@
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# frozen_string_literal: true
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# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
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require 'ffi'
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require 'crabstone/arch/extension'
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require_relative 'mips_const'
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module Crabstone
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module MIPS
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class OperandMemory < FFI::Struct
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layout(
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:base, :uint,
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:disp, :long
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)
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end
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class OperandValue < FFI::Union
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layout(
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:reg, :uint,
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:imm, :long,
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:mem, OperandMemory
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)
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end
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class Operand < FFI::Struct
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layout(
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:type, :uint,
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:value, OperandValue
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)
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include Crabstone::Extension::Operand
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def reg?
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self[:type] == OP_REG
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end
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def imm?
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self[:type] == OP_IMM
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end
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def mem?
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self[:type] == OP_MEM
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end
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end
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class Instruction < FFI::Struct
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layout(
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:op_count, :uint8,
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:operands, [Operand, 10]
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)
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include Crabstone::Extension::Instruction
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end
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end
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end
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# frozen_string_literal: true
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# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
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require 'crabstone/arch/register'
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module Crabstone
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module MIPS
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OP_INVALID = 0
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OP_REG = 1
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OP_IMM = 2
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OP_MEM = 3
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REG_INVALID = 0
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REG_PC = 1
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REG_0 = 2
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REG_1 = 3
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REG_2 = 4
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REG_3 = 5
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REG_4 = 6
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REG_5 = 7
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REG_6 = 8
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REG_7 = 9
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REG_8 = 10
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REG_9 = 11
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REG_10 = 12
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REG_11 = 13
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REG_12 = 14
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REG_13 = 15
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REG_14 = 16
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REG_15 = 17
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REG_16 = 18
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REG_17 = 19
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REG_18 = 20
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REG_19 = 21
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REG_20 = 22
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REG_21 = 23
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REG_22 = 24
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REG_23 = 25
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REG_24 = 26
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REG_25 = 27
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REG_26 = 28
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REG_27 = 29
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44
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REG_28 = 30
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REG_29 = 31
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REG_30 = 32
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REG_31 = 33
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REG_DSPCCOND = 34
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REG_DSPCARRY = 35
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REG_DSPEFI = 36
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REG_DSPOUTFLAG = 37
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REG_DSPOUTFLAG16_19 = 38
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REG_DSPOUTFLAG20 = 39
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REG_DSPOUTFLAG21 = 40
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REG_DSPOUTFLAG22 = 41
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REG_DSPOUTFLAG23 = 42
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REG_DSPPOS = 43
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REG_DSPSCOUNT = 44
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REG_AC0 = 45
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REG_AC1 = 46
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REG_AC2 = 47
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REG_AC3 = 48
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REG_CC0 = 49
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REG_CC1 = 50
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REG_CC2 = 51
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REG_CC3 = 52
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REG_CC4 = 53
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REG_CC5 = 54
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REG_CC6 = 55
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REG_CC7 = 56
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REG_F0 = 57
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REG_F1 = 58
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REG_F2 = 59
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REG_F3 = 60
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REG_F4 = 61
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REG_F5 = 62
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REG_F6 = 63
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REG_F7 = 64
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REG_F8 = 65
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REG_F9 = 66
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REG_F10 = 67
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REG_F11 = 68
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REG_F12 = 69
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REG_F13 = 70
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REG_F14 = 71
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REG_F15 = 72
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REG_F16 = 73
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REG_F17 = 74
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REG_F18 = 75
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REG_F19 = 76
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REG_F20 = 77
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REG_F21 = 78
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REG_F22 = 79
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REG_F23 = 80
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REG_F24 = 81
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REG_F25 = 82
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REG_F26 = 83
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REG_F27 = 84
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REG_F28 = 85
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REG_F29 = 86
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REG_F30 = 87
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REG_F31 = 88
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REG_FCC0 = 89
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REG_FCC1 = 90
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REG_FCC2 = 91
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REG_FCC3 = 92
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REG_FCC4 = 93
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REG_FCC5 = 94
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109
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REG_FCC6 = 95
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REG_FCC7 = 96
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111
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REG_W0 = 97
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112
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REG_W1 = 98
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REG_W2 = 99
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REG_W3 = 100
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REG_W4 = 101
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REG_W5 = 102
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REG_W6 = 103
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REG_W7 = 104
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REG_W8 = 105
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REG_W9 = 106
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121
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REG_W10 = 107
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REG_W11 = 108
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123
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REG_W12 = 109
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REG_W13 = 110
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REG_W14 = 111
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126
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REG_W15 = 112
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127
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REG_W16 = 113
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REG_W17 = 114
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REG_W18 = 115
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REG_W19 = 116
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REG_W20 = 117
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REG_W21 = 118
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REG_W22 = 119
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REG_W23 = 120
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REG_W24 = 121
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REG_W25 = 122
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REG_W26 = 123
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REG_W27 = 124
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REG_W28 = 125
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REG_W29 = 126
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REG_W30 = 127
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REG_W31 = 128
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REG_HI = 129
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REG_LO = 130
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REG_P0 = 131
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REG_P1 = 132
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REG_P2 = 133
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REG_MPL0 = 134
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REG_MPL1 = 135
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REG_MPL2 = 136
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REG_ENDING = 137
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REG_ZERO = REG_0
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REG_AT = REG_1
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REG_V0 = REG_2
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REG_V1 = REG_3
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REG_A0 = REG_4
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REG_A1 = REG_5
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REG_A2 = REG_6
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REG_A3 = REG_7
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REG_T0 = REG_8
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REG_T1 = REG_9
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REG_T2 = REG_10
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REG_T3 = REG_11
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REG_T4 = REG_12
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REG_T5 = REG_13
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REG_T6 = REG_14
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REG_T7 = REG_15
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REG_S0 = REG_16
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REG_S1 = REG_17
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REG_S2 = REG_18
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REG_S3 = REG_19
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REG_S4 = REG_20
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REG_S5 = REG_21
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REG_S6 = REG_22
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REG_S7 = REG_23
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REG_T8 = REG_24
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REG_T9 = REG_25
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REG_K0 = REG_26
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REG_K1 = REG_27
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REG_GP = REG_28
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REG_SP = REG_29
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REG_FP = REG_30
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REG_S8 = REG_30
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REG_RA = REG_31
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REG_HI0 = REG_AC0
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REG_HI1 = REG_AC1
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REG_HI2 = REG_AC2
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REG_HI3 = REG_AC3
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REG_LO0 = REG_HI0
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REG_LO1 = REG_HI1
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REG_LO2 = REG_HI2
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REG_LO3 = REG_HI3
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+
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INS_INVALID = 0
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INS_ABSQ_S = 1
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INS_ADD = 2
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INS_ADDIUPC = 3
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INS_ADDIUR1SP = 4
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INS_ADDIUR2 = 5
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INS_ADDIUS5 = 6
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INS_ADDIUSP = 7
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INS_ADDQH = 8
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INS_ADDQH_R = 9
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INS_ADDQ = 10
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INS_ADDQ_S = 11
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INS_ADDSC = 12
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INS_ADDS_A = 13
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INS_ADDS_S = 14
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INS_ADDS_U = 15
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210
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INS_ADDU16 = 16
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211
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+
INS_ADDUH = 17
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212
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INS_ADDUH_R = 18
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213
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INS_ADDU = 19
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214
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INS_ADDU_S = 20
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215
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+
INS_ADDVI = 21
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216
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INS_ADDV = 22
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217
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+
INS_ADDWC = 23
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218
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+
INS_ADD_A = 24
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219
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+
INS_ADDI = 25
|
220
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+
INS_ADDIU = 26
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221
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+
INS_ALIGN = 27
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222
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+
INS_ALUIPC = 28
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223
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+
INS_AND = 29
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224
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+
INS_AND16 = 30
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225
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+
INS_ANDI16 = 31
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226
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+
INS_ANDI = 32
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227
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+
INS_APPEND = 33
|
228
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+
INS_ASUB_S = 34
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229
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+
INS_ASUB_U = 35
|
230
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+
INS_AUI = 36
|
231
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+
INS_AUIPC = 37
|
232
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+
INS_AVER_S = 38
|
233
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+
INS_AVER_U = 39
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234
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+
INS_AVE_S = 40
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235
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+
INS_AVE_U = 41
|
236
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+
INS_B16 = 42
|
237
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+
INS_BADDU = 43
|
238
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+
INS_BAL = 44
|
239
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+
INS_BALC = 45
|
240
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+
INS_BALIGN = 46
|
241
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+
INS_BBIT0 = 47
|
242
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+
INS_BBIT032 = 48
|
243
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+
INS_BBIT1 = 49
|
244
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+
INS_BBIT132 = 50
|
245
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+
INS_BC = 51
|
246
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+
INS_BC0F = 52
|
247
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+
INS_BC0FL = 53
|
248
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+
INS_BC0T = 54
|
249
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+
INS_BC0TL = 55
|
250
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+
INS_BC1EQZ = 56
|
251
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+
INS_BC1F = 57
|
252
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+
INS_BC1FL = 58
|
253
|
+
INS_BC1NEZ = 59
|
254
|
+
INS_BC1T = 60
|
255
|
+
INS_BC1TL = 61
|
256
|
+
INS_BC2EQZ = 62
|
257
|
+
INS_BC2F = 63
|
258
|
+
INS_BC2FL = 64
|
259
|
+
INS_BC2NEZ = 65
|
260
|
+
INS_BC2T = 66
|
261
|
+
INS_BC2TL = 67
|
262
|
+
INS_BC3F = 68
|
263
|
+
INS_BC3FL = 69
|
264
|
+
INS_BC3T = 70
|
265
|
+
INS_BC3TL = 71
|
266
|
+
INS_BCLRI = 72
|
267
|
+
INS_BCLR = 73
|
268
|
+
INS_BEQ = 74
|
269
|
+
INS_BEQC = 75
|
270
|
+
INS_BEQL = 76
|
271
|
+
INS_BEQZ16 = 77
|
272
|
+
INS_BEQZALC = 78
|
273
|
+
INS_BEQZC = 79
|
274
|
+
INS_BGEC = 80
|
275
|
+
INS_BGEUC = 81
|
276
|
+
INS_BGEZ = 82
|
277
|
+
INS_BGEZAL = 83
|
278
|
+
INS_BGEZALC = 84
|
279
|
+
INS_BGEZALL = 85
|
280
|
+
INS_BGEZALS = 86
|
281
|
+
INS_BGEZC = 87
|
282
|
+
INS_BGEZL = 88
|
283
|
+
INS_BGTZ = 89
|
284
|
+
INS_BGTZALC = 90
|
285
|
+
INS_BGTZC = 91
|
286
|
+
INS_BGTZL = 92
|
287
|
+
INS_BINSLI = 93
|
288
|
+
INS_BINSL = 94
|
289
|
+
INS_BINSRI = 95
|
290
|
+
INS_BINSR = 96
|
291
|
+
INS_BITREV = 97
|
292
|
+
INS_BITSWAP = 98
|
293
|
+
INS_BLEZ = 99
|
294
|
+
INS_BLEZALC = 100
|
295
|
+
INS_BLEZC = 101
|
296
|
+
INS_BLEZL = 102
|
297
|
+
INS_BLTC = 103
|
298
|
+
INS_BLTUC = 104
|
299
|
+
INS_BLTZ = 105
|
300
|
+
INS_BLTZAL = 106
|
301
|
+
INS_BLTZALC = 107
|
302
|
+
INS_BLTZALL = 108
|
303
|
+
INS_BLTZALS = 109
|
304
|
+
INS_BLTZC = 110
|
305
|
+
INS_BLTZL = 111
|
306
|
+
INS_BMNZI = 112
|
307
|
+
INS_BMNZ = 113
|
308
|
+
INS_BMZI = 114
|
309
|
+
INS_BMZ = 115
|
310
|
+
INS_BNE = 116
|
311
|
+
INS_BNEC = 117
|
312
|
+
INS_BNEGI = 118
|
313
|
+
INS_BNEG = 119
|
314
|
+
INS_BNEL = 120
|
315
|
+
INS_BNEZ16 = 121
|
316
|
+
INS_BNEZALC = 122
|
317
|
+
INS_BNEZC = 123
|
318
|
+
INS_BNVC = 124
|
319
|
+
INS_BNZ = 125
|
320
|
+
INS_BOVC = 126
|
321
|
+
INS_BPOSGE32 = 127
|
322
|
+
INS_BREAK = 128
|
323
|
+
INS_BREAK16 = 129
|
324
|
+
INS_BSELI = 130
|
325
|
+
INS_BSEL = 131
|
326
|
+
INS_BSETI = 132
|
327
|
+
INS_BSET = 133
|
328
|
+
INS_BZ = 134
|
329
|
+
INS_BEQZ = 135
|
330
|
+
INS_B = 136
|
331
|
+
INS_BNEZ = 137
|
332
|
+
INS_BTEQZ = 138
|
333
|
+
INS_BTNEZ = 139
|
334
|
+
INS_CACHE = 140
|
335
|
+
INS_CEIL = 141
|
336
|
+
INS_CEQI = 142
|
337
|
+
INS_CEQ = 143
|
338
|
+
INS_CFC1 = 144
|
339
|
+
INS_CFCMSA = 145
|
340
|
+
INS_CINS = 146
|
341
|
+
INS_CINS32 = 147
|
342
|
+
INS_CLASS = 148
|
343
|
+
INS_CLEI_S = 149
|
344
|
+
INS_CLEI_U = 150
|
345
|
+
INS_CLE_S = 151
|
346
|
+
INS_CLE_U = 152
|
347
|
+
INS_CLO = 153
|
348
|
+
INS_CLTI_S = 154
|
349
|
+
INS_CLTI_U = 155
|
350
|
+
INS_CLT_S = 156
|
351
|
+
INS_CLT_U = 157
|
352
|
+
INS_CLZ = 158
|
353
|
+
INS_CMPGDU = 159
|
354
|
+
INS_CMPGU = 160
|
355
|
+
INS_CMPU = 161
|
356
|
+
INS_CMP = 162
|
357
|
+
INS_COPY_S = 163
|
358
|
+
INS_COPY_U = 164
|
359
|
+
INS_CTC1 = 165
|
360
|
+
INS_CTCMSA = 166
|
361
|
+
INS_CVT = 167
|
362
|
+
INS_C = 168
|
363
|
+
INS_CMPI = 169
|
364
|
+
INS_DADD = 170
|
365
|
+
INS_DADDI = 171
|
366
|
+
INS_DADDIU = 172
|
367
|
+
INS_DADDU = 173
|
368
|
+
INS_DAHI = 174
|
369
|
+
INS_DALIGN = 175
|
370
|
+
INS_DATI = 176
|
371
|
+
INS_DAUI = 177
|
372
|
+
INS_DBITSWAP = 178
|
373
|
+
INS_DCLO = 179
|
374
|
+
INS_DCLZ = 180
|
375
|
+
INS_DDIV = 181
|
376
|
+
INS_DDIVU = 182
|
377
|
+
INS_DERET = 183
|
378
|
+
INS_DEXT = 184
|
379
|
+
INS_DEXTM = 185
|
380
|
+
INS_DEXTU = 186
|
381
|
+
INS_DI = 187
|
382
|
+
INS_DINS = 188
|
383
|
+
INS_DINSM = 189
|
384
|
+
INS_DINSU = 190
|
385
|
+
INS_DIV = 191
|
386
|
+
INS_DIVU = 192
|
387
|
+
INS_DIV_S = 193
|
388
|
+
INS_DIV_U = 194
|
389
|
+
INS_DLSA = 195
|
390
|
+
INS_DMFC0 = 196
|
391
|
+
INS_DMFC1 = 197
|
392
|
+
INS_DMFC2 = 198
|
393
|
+
INS_DMOD = 199
|
394
|
+
INS_DMODU = 200
|
395
|
+
INS_DMTC0 = 201
|
396
|
+
INS_DMTC1 = 202
|
397
|
+
INS_DMTC2 = 203
|
398
|
+
INS_DMUH = 204
|
399
|
+
INS_DMUHU = 205
|
400
|
+
INS_DMUL = 206
|
401
|
+
INS_DMULT = 207
|
402
|
+
INS_DMULTU = 208
|
403
|
+
INS_DMULU = 209
|
404
|
+
INS_DOTP_S = 210
|
405
|
+
INS_DOTP_U = 211
|
406
|
+
INS_DPADD_S = 212
|
407
|
+
INS_DPADD_U = 213
|
408
|
+
INS_DPAQX_SA = 214
|
409
|
+
INS_DPAQX_S = 215
|
410
|
+
INS_DPAQ_SA = 216
|
411
|
+
INS_DPAQ_S = 217
|
412
|
+
INS_DPAU = 218
|
413
|
+
INS_DPAX = 219
|
414
|
+
INS_DPA = 220
|
415
|
+
INS_DPOP = 221
|
416
|
+
INS_DPSQX_SA = 222
|
417
|
+
INS_DPSQX_S = 223
|
418
|
+
INS_DPSQ_SA = 224
|
419
|
+
INS_DPSQ_S = 225
|
420
|
+
INS_DPSUB_S = 226
|
421
|
+
INS_DPSUB_U = 227
|
422
|
+
INS_DPSU = 228
|
423
|
+
INS_DPSX = 229
|
424
|
+
INS_DPS = 230
|
425
|
+
INS_DROTR = 231
|
426
|
+
INS_DROTR32 = 232
|
427
|
+
INS_DROTRV = 233
|
428
|
+
INS_DSBH = 234
|
429
|
+
INS_DSHD = 235
|
430
|
+
INS_DSLL = 236
|
431
|
+
INS_DSLL32 = 237
|
432
|
+
INS_DSLLV = 238
|
433
|
+
INS_DSRA = 239
|
434
|
+
INS_DSRA32 = 240
|
435
|
+
INS_DSRAV = 241
|
436
|
+
INS_DSRL = 242
|
437
|
+
INS_DSRL32 = 243
|
438
|
+
INS_DSRLV = 244
|
439
|
+
INS_DSUB = 245
|
440
|
+
INS_DSUBU = 246
|
441
|
+
INS_EHB = 247
|
442
|
+
INS_EI = 248
|
443
|
+
INS_ERET = 249
|
444
|
+
INS_EXT = 250
|
445
|
+
INS_EXTP = 251
|
446
|
+
INS_EXTPDP = 252
|
447
|
+
INS_EXTPDPV = 253
|
448
|
+
INS_EXTPV = 254
|
449
|
+
INS_EXTRV_RS = 255
|
450
|
+
INS_EXTRV_R = 256
|
451
|
+
INS_EXTRV_S = 257
|
452
|
+
INS_EXTRV = 258
|
453
|
+
INS_EXTR_RS = 259
|
454
|
+
INS_EXTR_R = 260
|
455
|
+
INS_EXTR_S = 261
|
456
|
+
INS_EXTR = 262
|
457
|
+
INS_EXTS = 263
|
458
|
+
INS_EXTS32 = 264
|
459
|
+
INS_ABS = 265
|
460
|
+
INS_FADD = 266
|
461
|
+
INS_FCAF = 267
|
462
|
+
INS_FCEQ = 268
|
463
|
+
INS_FCLASS = 269
|
464
|
+
INS_FCLE = 270
|
465
|
+
INS_FCLT = 271
|
466
|
+
INS_FCNE = 272
|
467
|
+
INS_FCOR = 273
|
468
|
+
INS_FCUEQ = 274
|
469
|
+
INS_FCULE = 275
|
470
|
+
INS_FCULT = 276
|
471
|
+
INS_FCUNE = 277
|
472
|
+
INS_FCUN = 278
|
473
|
+
INS_FDIV = 279
|
474
|
+
INS_FEXDO = 280
|
475
|
+
INS_FEXP2 = 281
|
476
|
+
INS_FEXUPL = 282
|
477
|
+
INS_FEXUPR = 283
|
478
|
+
INS_FFINT_S = 284
|
479
|
+
INS_FFINT_U = 285
|
480
|
+
INS_FFQL = 286
|
481
|
+
INS_FFQR = 287
|
482
|
+
INS_FILL = 288
|
483
|
+
INS_FLOG2 = 289
|
484
|
+
INS_FLOOR = 290
|
485
|
+
INS_FMADD = 291
|
486
|
+
INS_FMAX_A = 292
|
487
|
+
INS_FMAX = 293
|
488
|
+
INS_FMIN_A = 294
|
489
|
+
INS_FMIN = 295
|
490
|
+
INS_MOV = 296
|
491
|
+
INS_FMSUB = 297
|
492
|
+
INS_FMUL = 298
|
493
|
+
INS_MUL = 299
|
494
|
+
INS_NEG = 300
|
495
|
+
INS_FRCP = 301
|
496
|
+
INS_FRINT = 302
|
497
|
+
INS_FRSQRT = 303
|
498
|
+
INS_FSAF = 304
|
499
|
+
INS_FSEQ = 305
|
500
|
+
INS_FSLE = 306
|
501
|
+
INS_FSLT = 307
|
502
|
+
INS_FSNE = 308
|
503
|
+
INS_FSOR = 309
|
504
|
+
INS_FSQRT = 310
|
505
|
+
INS_SQRT = 311
|
506
|
+
INS_FSUB = 312
|
507
|
+
INS_SUB = 313
|
508
|
+
INS_FSUEQ = 314
|
509
|
+
INS_FSULE = 315
|
510
|
+
INS_FSULT = 316
|
511
|
+
INS_FSUNE = 317
|
512
|
+
INS_FSUN = 318
|
513
|
+
INS_FTINT_S = 319
|
514
|
+
INS_FTINT_U = 320
|
515
|
+
INS_FTQ = 321
|
516
|
+
INS_FTRUNC_S = 322
|
517
|
+
INS_FTRUNC_U = 323
|
518
|
+
INS_HADD_S = 324
|
519
|
+
INS_HADD_U = 325
|
520
|
+
INS_HSUB_S = 326
|
521
|
+
INS_HSUB_U = 327
|
522
|
+
INS_ILVEV = 328
|
523
|
+
INS_ILVL = 329
|
524
|
+
INS_ILVOD = 330
|
525
|
+
INS_ILVR = 331
|
526
|
+
INS_INS = 332
|
527
|
+
INS_INSERT = 333
|
528
|
+
INS_INSV = 334
|
529
|
+
INS_INSVE = 335
|
530
|
+
INS_J = 336
|
531
|
+
INS_JAL = 337
|
532
|
+
INS_JALR = 338
|
533
|
+
INS_JALRS16 = 339
|
534
|
+
INS_JALRS = 340
|
535
|
+
INS_JALS = 341
|
536
|
+
INS_JALX = 342
|
537
|
+
INS_JIALC = 343
|
538
|
+
INS_JIC = 344
|
539
|
+
INS_JR = 345
|
540
|
+
INS_JR16 = 346
|
541
|
+
INS_JRADDIUSP = 347
|
542
|
+
INS_JRC = 348
|
543
|
+
INS_JALRC = 349
|
544
|
+
INS_LB = 350
|
545
|
+
INS_LBU16 = 351
|
546
|
+
INS_LBUX = 352
|
547
|
+
INS_LBU = 353
|
548
|
+
INS_LD = 354
|
549
|
+
INS_LDC1 = 355
|
550
|
+
INS_LDC2 = 356
|
551
|
+
INS_LDC3 = 357
|
552
|
+
INS_LDI = 358
|
553
|
+
INS_LDL = 359
|
554
|
+
INS_LDPC = 360
|
555
|
+
INS_LDR = 361
|
556
|
+
INS_LDXC1 = 362
|
557
|
+
INS_LH = 363
|
558
|
+
INS_LHU16 = 364
|
559
|
+
INS_LHX = 365
|
560
|
+
INS_LHU = 366
|
561
|
+
INS_LI16 = 367
|
562
|
+
INS_LL = 368
|
563
|
+
INS_LLD = 369
|
564
|
+
INS_LSA = 370
|
565
|
+
INS_LUXC1 = 371
|
566
|
+
INS_LUI = 372
|
567
|
+
INS_LW = 373
|
568
|
+
INS_LW16 = 374
|
569
|
+
INS_LWC1 = 375
|
570
|
+
INS_LWC2 = 376
|
571
|
+
INS_LWC3 = 377
|
572
|
+
INS_LWL = 378
|
573
|
+
INS_LWM16 = 379
|
574
|
+
INS_LWM32 = 380
|
575
|
+
INS_LWPC = 381
|
576
|
+
INS_LWP = 382
|
577
|
+
INS_LWR = 383
|
578
|
+
INS_LWUPC = 384
|
579
|
+
INS_LWU = 385
|
580
|
+
INS_LWX = 386
|
581
|
+
INS_LWXC1 = 387
|
582
|
+
INS_LWXS = 388
|
583
|
+
INS_LI = 389
|
584
|
+
INS_MADD = 390
|
585
|
+
INS_MADDF = 391
|
586
|
+
INS_MADDR_Q = 392
|
587
|
+
INS_MADDU = 393
|
588
|
+
INS_MADDV = 394
|
589
|
+
INS_MADD_Q = 395
|
590
|
+
INS_MAQ_SA = 396
|
591
|
+
INS_MAQ_S = 397
|
592
|
+
INS_MAXA = 398
|
593
|
+
INS_MAXI_S = 399
|
594
|
+
INS_MAXI_U = 400
|
595
|
+
INS_MAX_A = 401
|
596
|
+
INS_MAX = 402
|
597
|
+
INS_MAX_S = 403
|
598
|
+
INS_MAX_U = 404
|
599
|
+
INS_MFC0 = 405
|
600
|
+
INS_MFC1 = 406
|
601
|
+
INS_MFC2 = 407
|
602
|
+
INS_MFHC1 = 408
|
603
|
+
INS_MFHI = 409
|
604
|
+
INS_MFLO = 410
|
605
|
+
INS_MINA = 411
|
606
|
+
INS_MINI_S = 412
|
607
|
+
INS_MINI_U = 413
|
608
|
+
INS_MIN_A = 414
|
609
|
+
INS_MIN = 415
|
610
|
+
INS_MIN_S = 416
|
611
|
+
INS_MIN_U = 417
|
612
|
+
INS_MOD = 418
|
613
|
+
INS_MODSUB = 419
|
614
|
+
INS_MODU = 420
|
615
|
+
INS_MOD_S = 421
|
616
|
+
INS_MOD_U = 422
|
617
|
+
INS_MOVE = 423
|
618
|
+
INS_MOVEP = 424
|
619
|
+
INS_MOVF = 425
|
620
|
+
INS_MOVN = 426
|
621
|
+
INS_MOVT = 427
|
622
|
+
INS_MOVZ = 428
|
623
|
+
INS_MSUB = 429
|
624
|
+
INS_MSUBF = 430
|
625
|
+
INS_MSUBR_Q = 431
|
626
|
+
INS_MSUBU = 432
|
627
|
+
INS_MSUBV = 433
|
628
|
+
INS_MSUB_Q = 434
|
629
|
+
INS_MTC0 = 435
|
630
|
+
INS_MTC1 = 436
|
631
|
+
INS_MTC2 = 437
|
632
|
+
INS_MTHC1 = 438
|
633
|
+
INS_MTHI = 439
|
634
|
+
INS_MTHLIP = 440
|
635
|
+
INS_MTLO = 441
|
636
|
+
INS_MTM0 = 442
|
637
|
+
INS_MTM1 = 443
|
638
|
+
INS_MTM2 = 444
|
639
|
+
INS_MTP0 = 445
|
640
|
+
INS_MTP1 = 446
|
641
|
+
INS_MTP2 = 447
|
642
|
+
INS_MUH = 448
|
643
|
+
INS_MUHU = 449
|
644
|
+
INS_MULEQ_S = 450
|
645
|
+
INS_MULEU_S = 451
|
646
|
+
INS_MULQ_RS = 452
|
647
|
+
INS_MULQ_S = 453
|
648
|
+
INS_MULR_Q = 454
|
649
|
+
INS_MULSAQ_S = 455
|
650
|
+
INS_MULSA = 456
|
651
|
+
INS_MULT = 457
|
652
|
+
INS_MULTU = 458
|
653
|
+
INS_MULU = 459
|
654
|
+
INS_MULV = 460
|
655
|
+
INS_MUL_Q = 461
|
656
|
+
INS_MUL_S = 462
|
657
|
+
INS_NLOC = 463
|
658
|
+
INS_NLZC = 464
|
659
|
+
INS_NMADD = 465
|
660
|
+
INS_NMSUB = 466
|
661
|
+
INS_NOR = 467
|
662
|
+
INS_NORI = 468
|
663
|
+
INS_NOT16 = 469
|
664
|
+
INS_NOT = 470
|
665
|
+
INS_OR = 471
|
666
|
+
INS_OR16 = 472
|
667
|
+
INS_ORI = 473
|
668
|
+
INS_PACKRL = 474
|
669
|
+
INS_PAUSE = 475
|
670
|
+
INS_PCKEV = 476
|
671
|
+
INS_PCKOD = 477
|
672
|
+
INS_PCNT = 478
|
673
|
+
INS_PICK = 479
|
674
|
+
INS_POP = 480
|
675
|
+
INS_PRECEQU = 481
|
676
|
+
INS_PRECEQ = 482
|
677
|
+
INS_PRECEU = 483
|
678
|
+
INS_PRECRQU_S = 484
|
679
|
+
INS_PRECRQ = 485
|
680
|
+
INS_PRECRQ_RS = 486
|
681
|
+
INS_PRECR = 487
|
682
|
+
INS_PRECR_SRA = 488
|
683
|
+
INS_PRECR_SRA_R = 489
|
684
|
+
INS_PREF = 490
|
685
|
+
INS_PREPEND = 491
|
686
|
+
INS_RADDU = 492
|
687
|
+
INS_RDDSP = 493
|
688
|
+
INS_RDHWR = 494
|
689
|
+
INS_REPLV = 495
|
690
|
+
INS_REPL = 496
|
691
|
+
INS_RINT = 497
|
692
|
+
INS_ROTR = 498
|
693
|
+
INS_ROTRV = 499
|
694
|
+
INS_ROUND = 500
|
695
|
+
INS_SAT_S = 501
|
696
|
+
INS_SAT_U = 502
|
697
|
+
INS_SB = 503
|
698
|
+
INS_SB16 = 504
|
699
|
+
INS_SC = 505
|
700
|
+
INS_SCD = 506
|
701
|
+
INS_SD = 507
|
702
|
+
INS_SDBBP = 508
|
703
|
+
INS_SDBBP16 = 509
|
704
|
+
INS_SDC1 = 510
|
705
|
+
INS_SDC2 = 511
|
706
|
+
INS_SDC3 = 512
|
707
|
+
INS_SDL = 513
|
708
|
+
INS_SDR = 514
|
709
|
+
INS_SDXC1 = 515
|
710
|
+
INS_SEB = 516
|
711
|
+
INS_SEH = 517
|
712
|
+
INS_SELEQZ = 518
|
713
|
+
INS_SELNEZ = 519
|
714
|
+
INS_SEL = 520
|
715
|
+
INS_SEQ = 521
|
716
|
+
INS_SEQI = 522
|
717
|
+
INS_SH = 523
|
718
|
+
INS_SH16 = 524
|
719
|
+
INS_SHF = 525
|
720
|
+
INS_SHILO = 526
|
721
|
+
INS_SHILOV = 527
|
722
|
+
INS_SHLLV = 528
|
723
|
+
INS_SHLLV_S = 529
|
724
|
+
INS_SHLL = 530
|
725
|
+
INS_SHLL_S = 531
|
726
|
+
INS_SHRAV = 532
|
727
|
+
INS_SHRAV_R = 533
|
728
|
+
INS_SHRA = 534
|
729
|
+
INS_SHRA_R = 535
|
730
|
+
INS_SHRLV = 536
|
731
|
+
INS_SHRL = 537
|
732
|
+
INS_SLDI = 538
|
733
|
+
INS_SLD = 539
|
734
|
+
INS_SLL = 540
|
735
|
+
INS_SLL16 = 541
|
736
|
+
INS_SLLI = 542
|
737
|
+
INS_SLLV = 543
|
738
|
+
INS_SLT = 544
|
739
|
+
INS_SLTI = 545
|
740
|
+
INS_SLTIU = 546
|
741
|
+
INS_SLTU = 547
|
742
|
+
INS_SNE = 548
|
743
|
+
INS_SNEI = 549
|
744
|
+
INS_SPLATI = 550
|
745
|
+
INS_SPLAT = 551
|
746
|
+
INS_SRA = 552
|
747
|
+
INS_SRAI = 553
|
748
|
+
INS_SRARI = 554
|
749
|
+
INS_SRAR = 555
|
750
|
+
INS_SRAV = 556
|
751
|
+
INS_SRL = 557
|
752
|
+
INS_SRL16 = 558
|
753
|
+
INS_SRLI = 559
|
754
|
+
INS_SRLRI = 560
|
755
|
+
INS_SRLR = 561
|
756
|
+
INS_SRLV = 562
|
757
|
+
INS_SSNOP = 563
|
758
|
+
INS_ST = 564
|
759
|
+
INS_SUBQH = 565
|
760
|
+
INS_SUBQH_R = 566
|
761
|
+
INS_SUBQ = 567
|
762
|
+
INS_SUBQ_S = 568
|
763
|
+
INS_SUBSUS_U = 569
|
764
|
+
INS_SUBSUU_S = 570
|
765
|
+
INS_SUBS_S = 571
|
766
|
+
INS_SUBS_U = 572
|
767
|
+
INS_SUBU16 = 573
|
768
|
+
INS_SUBUH = 574
|
769
|
+
INS_SUBUH_R = 575
|
770
|
+
INS_SUBU = 576
|
771
|
+
INS_SUBU_S = 577
|
772
|
+
INS_SUBVI = 578
|
773
|
+
INS_SUBV = 579
|
774
|
+
INS_SUXC1 = 580
|
775
|
+
INS_SW = 581
|
776
|
+
INS_SW16 = 582
|
777
|
+
INS_SWC1 = 583
|
778
|
+
INS_SWC2 = 584
|
779
|
+
INS_SWC3 = 585
|
780
|
+
INS_SWL = 586
|
781
|
+
INS_SWM16 = 587
|
782
|
+
INS_SWM32 = 588
|
783
|
+
INS_SWP = 589
|
784
|
+
INS_SWR = 590
|
785
|
+
INS_SWXC1 = 591
|
786
|
+
INS_SYNC = 592
|
787
|
+
INS_SYNCI = 593
|
788
|
+
INS_SYSCALL = 594
|
789
|
+
INS_TEQ = 595
|
790
|
+
INS_TEQI = 596
|
791
|
+
INS_TGE = 597
|
792
|
+
INS_TGEI = 598
|
793
|
+
INS_TGEIU = 599
|
794
|
+
INS_TGEU = 600
|
795
|
+
INS_TLBP = 601
|
796
|
+
INS_TLBR = 602
|
797
|
+
INS_TLBWI = 603
|
798
|
+
INS_TLBWR = 604
|
799
|
+
INS_TLT = 605
|
800
|
+
INS_TLTI = 606
|
801
|
+
INS_TLTIU = 607
|
802
|
+
INS_TLTU = 608
|
803
|
+
INS_TNE = 609
|
804
|
+
INS_TNEI = 610
|
805
|
+
INS_TRUNC = 611
|
806
|
+
INS_V3MULU = 612
|
807
|
+
INS_VMM0 = 613
|
808
|
+
INS_VMULU = 614
|
809
|
+
INS_VSHF = 615
|
810
|
+
INS_WAIT = 616
|
811
|
+
INS_WRDSP = 617
|
812
|
+
INS_WSBH = 618
|
813
|
+
INS_XOR = 619
|
814
|
+
INS_XOR16 = 620
|
815
|
+
INS_XORI = 621
|
816
|
+
|
817
|
+
INS_NOP = 622
|
818
|
+
INS_NEGU = 623
|
819
|
+
|
820
|
+
INS_JALR_HB = 624
|
821
|
+
INS_JR_HB = 625
|
822
|
+
INS_ENDING = 626
|
823
|
+
|
824
|
+
GRP_INVALID = 0
|
825
|
+
GRP_JUMP = 1
|
826
|
+
GRP_CALL = 2
|
827
|
+
GRP_RET = 3
|
828
|
+
GRP_INT = 4
|
829
|
+
GRP_IRET = 5
|
830
|
+
GRP_PRIVILEGE = 6
|
831
|
+
GRP_BRANCH_RELATIVE = 7
|
832
|
+
GRP_BITCOUNT = 128
|
833
|
+
GRP_DSP = 129
|
834
|
+
GRP_DSPR2 = 130
|
835
|
+
GRP_FPIDX = 131
|
836
|
+
GRP_MSA = 132
|
837
|
+
GRP_MIPS32R2 = 133
|
838
|
+
GRP_MIPS64 = 134
|
839
|
+
GRP_MIPS64R2 = 135
|
840
|
+
GRP_SEINREG = 136
|
841
|
+
GRP_STDENC = 137
|
842
|
+
GRP_SWAP = 138
|
843
|
+
GRP_MICROMIPS = 139
|
844
|
+
GRP_MIPS16MODE = 140
|
845
|
+
GRP_FP64BIT = 141
|
846
|
+
GRP_NONANSFPMATH = 142
|
847
|
+
GRP_NOTFP64BIT = 143
|
848
|
+
GRP_NOTINMICROMIPS = 144
|
849
|
+
GRP_NOTNACL = 145
|
850
|
+
GRP_NOTMIPS32R6 = 146
|
851
|
+
GRP_NOTMIPS64R6 = 147
|
852
|
+
GRP_CNMIPS = 148
|
853
|
+
GRP_MIPS32 = 149
|
854
|
+
GRP_MIPS32R6 = 150
|
855
|
+
GRP_MIPS64R6 = 151
|
856
|
+
GRP_MIPS2 = 152
|
857
|
+
GRP_MIPS3 = 153
|
858
|
+
GRP_MIPS3_32 = 154
|
859
|
+
GRP_MIPS3_32R2 = 155
|
860
|
+
GRP_MIPS4_32 = 156
|
861
|
+
GRP_MIPS4_32R2 = 157
|
862
|
+
GRP_MIPS5_32R2 = 158
|
863
|
+
GRP_GP32BIT = 159
|
864
|
+
GRP_GP64BIT = 160
|
865
|
+
GRP_ENDING = 161
|
866
|
+
|
867
|
+
extend Register
|
868
|
+
end
|
869
|
+
end
|