crabstone 3.0.3 → 4.0.0
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- checksums.yaml +5 -5
- data/CHANGES.md +45 -42
- data/README.md +16 -33
- data/lib/crabstone.rb +5 -557
- data/lib/crabstone/arch.rb +37 -0
- data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
- data/lib/crabstone/arch/3/arm64.rb +124 -0
- data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
- data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
- data/lib/crabstone/arch/3/mips.rb +57 -0
- data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
- data/lib/crabstone/arch/3/ppc.rb +73 -0
- data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
- data/lib/crabstone/arch/3/sparc.rb +60 -0
- data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
- data/lib/crabstone/arch/3/sysz.rb +67 -0
- data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
- data/lib/crabstone/arch/3/x86.rb +82 -0
- data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
- data/lib/crabstone/arch/3/xcore.rb +59 -0
- data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
- data/lib/crabstone/arch/4/arm.rb +110 -0
- data/lib/crabstone/arch/4/arm64.rb +125 -0
- data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
- data/lib/crabstone/arch/4/arm_const.rb +785 -0
- data/lib/crabstone/arch/4/evm.rb +20 -0
- data/lib/crabstone/arch/4/evm_const.rb +161 -0
- data/lib/crabstone/arch/4/m680x.rb +106 -0
- data/lib/crabstone/arch/4/m680x_const.rb +426 -0
- data/lib/crabstone/arch/4/m68k.rb +129 -0
- data/lib/crabstone/arch/4/m68k_const.rb +496 -0
- data/lib/crabstone/arch/4/mips.rb +57 -0
- data/lib/crabstone/arch/4/mips_const.rb +869 -0
- data/lib/crabstone/arch/4/ppc.rb +73 -0
- data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
- data/lib/crabstone/arch/4/sparc.rb +60 -0
- data/lib/crabstone/arch/4/sparc_const.rb +439 -0
- data/lib/crabstone/arch/4/sysz.rb +67 -0
- data/lib/crabstone/arch/4/sysz_const.rb +763 -0
- data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
- data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
- data/lib/crabstone/arch/4/x86.rb +91 -0
- data/lib/crabstone/arch/4/x86_const.rb +1972 -0
- data/lib/crabstone/arch/4/xcore.rb +59 -0
- data/lib/crabstone/arch/4/xcore_const.rb +171 -0
- data/lib/crabstone/arch/extension.rb +27 -0
- data/lib/crabstone/arch/register.rb +36 -0
- data/lib/crabstone/binding.rb +60 -0
- data/lib/crabstone/binding/3/detail.rb +36 -0
- data/lib/crabstone/binding/3/instruction.rb +23 -0
- data/lib/crabstone/binding/4/detail.rb +40 -0
- data/lib/crabstone/binding/4/instruction.rb +23 -0
- data/lib/crabstone/binding/structs.rb +32 -0
- data/lib/crabstone/constants.rb +110 -0
- data/lib/crabstone/cs_version.rb +49 -0
- data/lib/crabstone/disassembler.rb +153 -0
- data/lib/crabstone/error.rb +60 -0
- data/lib/crabstone/instruction.rb +183 -0
- data/lib/crabstone/version.rb +5 -0
- metadata +128 -324
- data/MANIFEST +0 -312
- data/Rakefile +0 -27
- data/bin/genconst +0 -66
- data/bin/genreg +0 -99
- data/crabstone.gemspec +0 -27
- data/examples/hello_world.rb +0 -43
- data/lib/arch/arm64.rb +0 -167
- data/lib/arch/arm64_registers.rb +0 -295
- data/lib/arch/arm_registers.rb +0 -149
- data/lib/arch/mips.rb +0 -78
- data/lib/arch/mips_registers.rb +0 -208
- data/lib/arch/ppc.rb +0 -90
- data/lib/arch/ppc_registers.rb +0 -209
- data/lib/arch/sparc.rb +0 -79
- data/lib/arch/sparc_registers.rb +0 -121
- data/lib/arch/systemz.rb +0 -79
- data/lib/arch/sysz_registers.rb +0 -66
- data/lib/arch/x86.rb +0 -107
- data/lib/arch/x86_registers.rb +0 -265
- data/lib/arch/xcore.rb +0 -78
- data/lib/arch/xcore_registers.rb +0 -57
- data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
- data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
- data/test/MC/AArch64/neon-2velem.s.cs +0 -113
- data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
- data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
- data/test/MC/AArch64/neon-across.s.cs +0 -40
- data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
- data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
- data/test/MC/AArch64/neon-crypto.s.cs +0 -15
- data/test/MC/AArch64/neon-extract.s.cs +0 -3
- data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
- data/test/MC/AArch64/neon-max-min.s.cs +0 -37
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
- data/test/MC/AArch64/neon-mov.s.cs +0 -74
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
- data/test/MC/AArch64/neon-perm.s.cs +0 -43
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
- data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
- data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
- data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
- data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
- data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
- data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
- data/test/MC/AArch64/neon-shift.s.cs +0 -22
- data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
- data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
- data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
- data/test/MC/AArch64/neon-tbl.s.cs +0 -21
- data/test/MC/AArch64/trace-regs.s.cs +0 -383
- data/test/MC/ARM/arm-aliases.s.cs +0 -7
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
- data/test/MC/ARM/arm-it-block.s.cs +0 -2
- data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
- data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
- data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
- data/test/MC/ARM/arm_instructions.s.cs +0 -25
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
- data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
- data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
- data/test/MC/ARM/crc32-thumb.s.cs +0 -7
- data/test/MC/ARM/crc32.s.cs +0 -7
- data/test/MC/ARM/dot-req.s.cs +0 -3
- data/test/MC/ARM/fp-armv8.s.cs +0 -52
- data/test/MC/ARM/idiv-thumb.s.cs +0 -3
- data/test/MC/ARM/idiv.s.cs +0 -3
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
- data/test/MC/ARM/mode-switch.s.cs +0 -7
- data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
- data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
- data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
- data/test/MC/ARM/neon-crypto.s.cs +0 -16
- data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
- data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
- data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
- data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neon-v8.s.cs +0 -38
- data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
- data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
- data/test/MC/ARM/neon-vswp.s.cs +0 -3
- data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
- data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
- data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
- data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
- data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
- data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
- data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
- data/test/MC/ARM/thumb-hints.s.cs +0 -12
- data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
- data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
- data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
- data/test/MC/ARM/thumb.s.cs +0 -19
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
- data/test/MC/ARM/thumb2-branches.s.cs +0 -85
- data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
- data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
- data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
- data/test/MC/ARM/vfp4.s.cs +0 -13
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
- data/test/MC/ARM/vpush-vpop.s.cs +0 -9
- data/test/MC/Mips/hilo-addressing.s.cs +0 -4
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
- data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
- data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
- data/test/MC/Mips/micromips-expansions.s.cs +0 -20
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
- data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
- data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
- data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
- data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
- data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
- data/test/MC/Mips/mips-expansions.s.cs +0 -20
- data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
- data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
- data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
- data/test/MC/Mips/mips-register-names.s.cs +0 -33
- data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
- data/test/MC/Mips/mips64-instructions.s.cs +0 -3
- data/test/MC/Mips/mips64-register-names.s.cs +0 -33
- data/test/MC/Mips/mips_directives.s.cs +0 -12
- data/test/MC/Mips/nabi-regs.s.cs +0 -12
- data/test/MC/Mips/set-at-directive.s.cs +0 -6
- data/test/MC/Mips/test_2r.s.cs +0 -16
- data/test/MC/Mips/test_2rf.s.cs +0 -33
- data/test/MC/Mips/test_3r.s.cs +0 -243
- data/test/MC/Mips/test_3rf.s.cs +0 -83
- data/test/MC/Mips/test_bit.s.cs +0 -49
- data/test/MC/Mips/test_cbranch.s.cs +0 -11
- data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
- data/test/MC/Mips/test_elm.s.cs +0 -16
- data/test/MC/Mips/test_elm_insert.s.cs +0 -4
- data/test/MC/Mips/test_elm_insve.s.cs +0 -5
- data/test/MC/Mips/test_i10.s.cs +0 -5
- data/test/MC/Mips/test_i5.s.cs +0 -45
- data/test/MC/Mips/test_i8.s.cs +0 -11
- data/test/MC/Mips/test_lsa.s.cs +0 -5
- data/test/MC/Mips/test_mi10.s.cs +0 -24
- data/test/MC/Mips/test_vec.s.cs +0 -8
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
- data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
- data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
- data/test/MC/README +0 -6
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
- data/test/MC/Sparc/sparc-vis.s.cs +0 -2
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
- data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
- data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
- data/test/MC/SystemZ/insn-good.s.cs +0 -2265
- data/test/MC/SystemZ/regs-good.s.cs +0 -45
- data/test/MC/X86/3DNow.s.cs +0 -29
- data/test/MC/X86/address-size.s.cs +0 -5
- data/test/MC/X86/avx512-encodings.s.cs +0 -12
- data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
- data/test/MC/X86/x86-32-avx.s.cs +0 -833
- data/test/MC/X86/x86-32-fma3.s.cs +0 -169
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
- data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
- data/test/MC/X86/x86_64-encoding.s.cs +0 -59
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
- data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
- data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
- data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
- data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
- data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
- data/test/README +0 -6
- data/test/test.rb +0 -205
- data/test/test.rb.SPEC +0 -235
- data/test/test_arm.rb +0 -202
- data/test/test_arm.rb.SPEC +0 -275
- data/test/test_arm64.rb +0 -150
- data/test/test_arm64.rb.SPEC +0 -116
- data/test/test_detail.rb +0 -228
- data/test/test_detail.rb.SPEC +0 -322
- data/test/test_exhaustive.rb +0 -80
- data/test/test_mips.rb +0 -118
- data/test/test_mips.rb.SPEC +0 -91
- data/test/test_ppc.rb +0 -137
- data/test/test_ppc.rb.SPEC +0 -84
- data/test/test_sanity.rb +0 -83
- data/test/test_skipdata.rb +0 -111
- data/test/test_skipdata.rb.SPEC +0 -58
- data/test/test_sparc.rb +0 -113
- data/test/test_sparc.rb.SPEC +0 -116
- data/test/test_sysz.rb +0 -111
- data/test/test_sysz.rb.SPEC +0 -61
- data/test/test_x86.rb +0 -189
- data/test/test_x86.rb.SPEC +0 -579
- data/test/test_xcore.rb +0 -100
- data/test/test_xcore.rb.SPEC +0 -75
@@ -1,152 +0,0 @@
|
|
1
|
-
# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
|
2
|
-
0x8f,0xe9,0x78,0xe2,0x0c,0x01 = vphsubwd (%rcx, %rax), %xmm1
|
3
|
-
0x8f,0xe9,0x78,0xe2,0xc8 = vphsubwd %xmm0, %xmm1
|
4
|
-
0x8f,0xe9,0x78,0xe3,0x0c,0x01 = vphsubdq (%rcx, %rax), %xmm1
|
5
|
-
0x8f,0xe9,0x78,0xe3,0xc8 = vphsubdq %xmm0, %xmm1
|
6
|
-
0x8f,0xe9,0x78,0xe1,0x08 = vphsubbw (%rax), %xmm1
|
7
|
-
0x8f,0xe9,0x78,0xe1,0xca = vphsubbw %xmm2, %xmm1
|
8
|
-
0x8f,0xe9,0x78,0xc7,0x21 = vphaddwq (%rcx), %xmm4
|
9
|
-
0x8f,0xe9,0x78,0xc7,0xd6 = vphaddwq %xmm6, %xmm2
|
10
|
-
0x8f,0xe9,0x78,0xc6,0x3c,0x02 = vphaddwd (%rdx, %rax), %xmm7
|
11
|
-
0x8f,0xe9,0x78,0xc6,0xe3 = vphaddwd %xmm3, %xmm4
|
12
|
-
0x8f,0xe9,0x78,0xd7,0x34,0x01 = vphadduwq (%rcx, %rax), %xmm6
|
13
|
-
0x8f,0xe9,0x78,0xd7,0xc7 = vphadduwq %xmm7, %xmm0
|
14
|
-
0x8f,0xe9,0x78,0xd6,0x28 = vphadduwd (%rax), %xmm5
|
15
|
-
0x8f,0xe9,0x78,0xd6,0xca = vphadduwd %xmm2, %xmm1
|
16
|
-
0x8f,0xe9,0x78,0xdb,0x64,0x01,0x08 = vphaddudq 8(%rcx, %rax), %xmm4
|
17
|
-
0x8f,0xe9,0x78,0xdb,0xd6 = vphaddudq %xmm6, %xmm2
|
18
|
-
0x8f,0xe9,0x78,0xd1,0x19 = vphaddubw (%rcx), %xmm3
|
19
|
-
0x8f,0xe9,0x78,0xd1,0xc5 = vphaddubw %xmm5, %xmm0
|
20
|
-
0x8f,0xe9,0x78,0xd3,0x21 = vphaddubq (%rcx), %xmm4
|
21
|
-
0x8f,0xe9,0x78,0xd3,0xd2 = vphaddubq %xmm2, %xmm2
|
22
|
-
0x8f,0xe9,0x78,0xd2,0x28 = vphaddubd (%rax), %xmm5
|
23
|
-
0x8f,0xe9,0x78,0xd2,0xfd = vphaddubd %xmm5, %xmm7
|
24
|
-
0x8f,0xe9,0x78,0xcb,0x22 = vphadddq (%rdx), %xmm4
|
25
|
-
0x8f,0xe9,0x78,0xcb,0xec = vphadddq %xmm4, %xmm5
|
26
|
-
0x8f,0xe9,0x78,0xc1,0x0c,0x01 = vphaddbw (%rcx, %rax), %xmm1
|
27
|
-
0x8f,0xe9,0x78,0xc1,0xf5 = vphaddbw %xmm5, %xmm6
|
28
|
-
0x8f,0xe9,0x78,0xc3,0x0c,0x01 = vphaddbq (%rcx, %rax), %xmm1
|
29
|
-
0x8f,0xe9,0x78,0xc3,0xc2 = vphaddbq %xmm2, %xmm0
|
30
|
-
0x8f,0xe9,0x78,0xc2,0x0c,0x01 = vphaddbd (%rcx, %rax), %xmm1
|
31
|
-
0x8f,0xe9,0x78,0xc2,0xd9 = vphaddbd %xmm1, %xmm3
|
32
|
-
0x8f,0xe9,0x78,0x82,0x0c,0x01 = vfrczss (%rcx, %rax), %xmm1
|
33
|
-
0x8f,0xe9,0x78,0x82,0xfd = vfrczss %xmm5, %xmm7
|
34
|
-
0x8f,0xe9,0x78,0x83,0x0c,0x01 = vfrczsd (%rcx, %rax), %xmm1
|
35
|
-
0x8f,0xe9,0x78,0x83,0xc7 = vfrczsd %xmm7, %xmm0
|
36
|
-
0x8f,0xe9,0x78,0x80,0x58,0x04 = vfrczps 4(%rax), %xmm3
|
37
|
-
0x8f,0xe9,0x78,0x80,0xee = vfrczps %xmm6, %xmm5
|
38
|
-
0x8f,0xe9,0x78,0x80,0x09 = vfrczps (%rcx), %xmm1
|
39
|
-
0x8f,0xe9,0x7c,0x80,0xe2 = vfrczps %ymm2, %ymm4
|
40
|
-
0x8f,0xe9,0x78,0x81,0x0c,0x01 = vfrczpd (%rcx, %rax), %xmm1
|
41
|
-
0x8f,0xe9,0x78,0x81,0xc7 = vfrczpd %xmm7, %xmm0
|
42
|
-
0x8f,0xe9,0x7c,0x81,0x14,0x01 = vfrczpd (%rcx, %rax), %ymm2
|
43
|
-
0x8f,0xe9,0x7c,0x81,0xdd = vfrczpd %ymm5, %ymm3
|
44
|
-
0x8f,0xe9,0x78,0x95,0xd1 = vpshlw %xmm0, %xmm1, %xmm2
|
45
|
-
0x8f,0xe9,0xf0,0x95,0x10 = vpshlw (%rax), %xmm1, %xmm2
|
46
|
-
0x8f,0xe9,0x78,0x95,0x14,0x08 = vpshlw %xmm0, (%rax, %rcx), %xmm2
|
47
|
-
0x8f,0xe9,0x68,0x97,0xf4 = vpshlq %xmm2, %xmm4, %xmm6
|
48
|
-
0x8f,0xe9,0xe8,0x97,0x09 = vpshlq (%rcx), %xmm2, %xmm1
|
49
|
-
0x8f,0xe9,0x50,0x97,0x34,0x0a = vpshlq %xmm5, (%rdx, %rcx), %xmm6
|
50
|
-
0x8f,0xe9,0x40,0x96,0xdd = vpshld %xmm7, %xmm5, %xmm3
|
51
|
-
0x8f,0xe9,0xe0,0x96,0x58,0x04 = vpshld 4(%rax), %xmm3, %xmm3
|
52
|
-
0x8f,0xe9,0x70,0x96,0x2c,0x08 = vpshld %xmm1, (%rax, %rcx), %xmm5
|
53
|
-
0x8f,0xe9,0x70,0x94,0xda = vpshlb %xmm1, %xmm2, %xmm3
|
54
|
-
0x8f,0xe9,0xf8,0x94,0x39 = vpshlb (%rcx), %xmm0, %xmm7
|
55
|
-
0x8f,0xe9,0x68,0x94,0x1c,0x10 = vpshlb %xmm2, (%rax, %rdx), %xmm3
|
56
|
-
0x8f,0xe9,0x40,0x99,0xdd = vpshaw %xmm7, %xmm5, %xmm3
|
57
|
-
0x8f,0xe9,0xe8,0x99,0x08 = vpshaw (%rax), %xmm2, %xmm1
|
58
|
-
0x8f,0xe9,0x78,0x99,0x5c,0x08,0x08 = vpshaw %xmm0, 8(%rax, %rcx), %xmm3
|
59
|
-
0x8f,0xe9,0x58,0x9b,0xe4 = vpshaq %xmm4, %xmm4, %xmm4
|
60
|
-
0x8f,0xe9,0xe8,0x9b,0x01 = vpshaq (%rcx), %xmm2, %xmm0
|
61
|
-
0x8f,0xe9,0x48,0x9b,0x2c,0x08 = vpshaq %xmm6, (%rax, %rcx), %xmm5
|
62
|
-
0x8f,0xe9,0x50,0x9a,0xc4 = vpshad %xmm5, %xmm4, %xmm0
|
63
|
-
0x8f,0xe9,0xe8,0x9a,0x28 = vpshad (%rax), %xmm2, %xmm5
|
64
|
-
0x8f,0xe9,0x68,0x9a,0x28 = vpshad %xmm2, (%rax), %xmm5
|
65
|
-
0x8f,0xe9,0x70,0x98,0xc1 = vpshab %xmm1, %xmm1, %xmm0
|
66
|
-
0x8f,0xe9,0xd8,0x98,0x01 = vpshab (%rcx), %xmm4, %xmm0
|
67
|
-
0x8f,0xe9,0x50,0x98,0x19 = vpshab %xmm5, (%rcx), %xmm3
|
68
|
-
0x8f,0xe9,0xe0,0x91,0x30 = vprotw (%rax), %xmm3, %xmm6
|
69
|
-
0x8f,0xe9,0x50,0x91,0x0c,0x08 = vprotw %xmm5, (%rax, %rcx), %xmm1
|
70
|
-
0x8f,0xe9,0x78,0x91,0xd1 = vprotw %xmm0, %xmm1, %xmm2
|
71
|
-
0x8f,0xe8,0x78,0xc1,0x09,0x2a = vprotw $42, (%rcx), %xmm1
|
72
|
-
0x8f,0xe8,0x78,0xc1,0x20,0x29 = vprotw $41, (%rax), %xmm4
|
73
|
-
0x8f,0xe8,0x78,0xc1,0xd9,0x28 = vprotw $40, %xmm1, %xmm3
|
74
|
-
0x8f,0xe9,0xf0,0x93,0x10 = vprotq (%rax), %xmm1, %xmm2
|
75
|
-
0x8f,0xe9,0xf0,0x93,0x14,0x08 = vprotq (%rax, %rcx), %xmm1, %xmm2
|
76
|
-
0x8f,0xe9,0x78,0x93,0xd1 = vprotq %xmm0, %xmm1, %xmm2
|
77
|
-
0x8f,0xe8,0x78,0xc3,0x10,0x2a = vprotq $42, (%rax), %xmm2
|
78
|
-
0x8f,0xe8,0x78,0xc3,0x14,0x08,0x2a = vprotq $42, (%rax, %rcx), %xmm2
|
79
|
-
0x8f,0xe8,0x78,0xc3,0xd1,0x2a = vprotq $42, %xmm1, %xmm2
|
80
|
-
0x8f,0xe9,0xf8,0x92,0x18 = vprotd (%rax), %xmm0, %xmm3
|
81
|
-
0x8f,0xe9,0x68,0x92,0x24,0x08 = vprotd %xmm2, (%rax, %rcx), %xmm4
|
82
|
-
0x8f,0xe9,0x50,0x92,0xd3 = vprotd %xmm5, %xmm3, %xmm2
|
83
|
-
0x8f,0xe8,0x78,0xc2,0x31,0x2b = vprotd $43, (%rcx), %xmm6
|
84
|
-
0x8f,0xe8,0x78,0xc2,0x3c,0x08,0x2c = vprotd $44, (%rax, %rcx), %xmm7
|
85
|
-
0x8f,0xe8,0x78,0xc2,0xe4,0x2d = vprotd $45, %xmm4, %xmm4
|
86
|
-
0x8f,0xe9,0xe8,0x90,0x29 = vprotb (%rcx), %xmm2, %xmm5
|
87
|
-
0x8f,0xe9,0x50,0x90,0x24,0x08 = vprotb %xmm5, (%rax, %rcx), %xmm4
|
88
|
-
0x8f,0xe9,0x58,0x90,0xd3 = vprotb %xmm4, %xmm3, %xmm2
|
89
|
-
0x8f,0xe8,0x78,0xc0,0x18,0x2e = vprotb $46, (%rax), %xmm3
|
90
|
-
0x8f,0xe8,0x78,0xc0,0x3c,0x08,0x2f = vprotb $47, (%rax, %rcx), %xmm7
|
91
|
-
0x8f,0xe8,0x78,0xc0,0xed,0x30 = vprotb $48, %xmm5, %xmm5
|
92
|
-
0x8f,0xe8,0x60,0xb6,0xe2,0x10 = vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4
|
93
|
-
0x8f,0xe8,0x60,0xb6,0x20,0x10 = vpmadcswd %xmm1, (%rax), %xmm3, %xmm4
|
94
|
-
0x8f,0xe8,0x48,0xa6,0xe4,0x10 = vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4
|
95
|
-
0x8f,0xe8,0x60,0xa6,0x24,0x08,0x10 = vpmadcsswd %xmm1, (%rax, %rcx), %xmm3, %xmm4
|
96
|
-
0x8f,0xe8,0x50,0x95,0xe2,0x00 = vpmacsww %xmm0, %xmm2, %xmm5, %xmm4
|
97
|
-
0x8f,0xe8,0x48,0x95,0x20,0x10 = vpmacsww %xmm1, (%rax), %xmm6, %xmm4
|
98
|
-
0x8f,0xe8,0x48,0x96,0xfd,0x40 = vpmacswd %xmm4, %xmm5, %xmm6, %xmm7
|
99
|
-
0x8f,0xe8,0x70,0x96,0x10,0x00 = vpmacswd %xmm0, (%rax), %xmm1, %xmm2
|
100
|
-
0x8f,0xe8,0x68,0x85,0xcb,0x40 = vpmacssww %xmm4, %xmm3, %xmm2, %xmm1
|
101
|
-
0x8f,0xe8,0x40,0x85,0x39,0x60 = vpmacssww %xmm6, (%rcx), %xmm7, %xmm7
|
102
|
-
0x8f,0xe8,0x58,0x86,0xd2,0x40 = vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2
|
103
|
-
0x8f,0xe8,0x70,0x86,0x44,0x08,0x08,0x00 = vpmacsswd %xmm0, 8(%rax, %rcx), %xmm1, %xmm0
|
104
|
-
0x8f,0xe8,0x68,0x87,0xe1,0x10 = vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4
|
105
|
-
0x8f,0xe8,0x48,0x87,0x29,0x70 = vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5
|
106
|
-
0x8f,0xe8,0x78,0x8f,0xca,0x30 = vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1
|
107
|
-
0x8f,0xe8,0x68,0x8f,0x1c,0x08,0x70 = vpmacssdqh %xmm7, (%rax, %rcx), %xmm2, %xmm3
|
108
|
-
0x8f,0xe8,0x60,0x8e,0xea,0x20 = vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5
|
109
|
-
0x8f,0xe8,0x70,0x8e,0x10,0x40 = vpmacssdd %xmm4, (%rax), %xmm1, %xmm2
|
110
|
-
0x8f,0xe8,0x48,0x97,0xf8,0x30 = vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7
|
111
|
-
0x8f,0xe8,0x60,0x97,0x69,0x08,0x50 = vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5
|
112
|
-
0x8f,0xe8,0x60,0x9f,0xd5,0x70 = vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2
|
113
|
-
0x8f,0xe8,0x68,0x9f,0x40,0x04,0x50 = vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0
|
114
|
-
0x8f,0xe8,0x58,0x9e,0xd6,0x40 = vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2
|
115
|
-
0x8f,0xe8,0x58,0x9e,0x1c,0x08,0x40 = vpmacsdd %xmm4, (%rax, %rcx), %xmm4, %xmm3
|
116
|
-
0x8f,0xe8,0x60,0xcd,0xe2,0x2a = vpcomw $42, %xmm2, %xmm3, %xmm4
|
117
|
-
0x8f,0xe8,0x60,0xcd,0x20,0x2a = vpcomw $42, (%rax), %xmm3, %xmm4
|
118
|
-
0x8f,0xe8,0x60,0xed,0xe9,0x2b = vpcomuw $43, %xmm1, %xmm3, %xmm5
|
119
|
-
0x8f,0xe8,0x78,0xed,0x34,0x08,0x2c = vpcomuw $44, (%rax, %rcx), %xmm0, %xmm6
|
120
|
-
0x8f,0xe8,0x60,0xef,0xfb,0x2d = vpcomuq $45, %xmm3, %xmm3, %xmm7
|
121
|
-
0x8f,0xe8,0x60,0xef,0x08,0x2e = vpcomuq $46, (%rax), %xmm3, %xmm1
|
122
|
-
0x8f,0xe8,0x70,0xee,0xd0,0x2f = vpcomud $47, %xmm0, %xmm1, %xmm2
|
123
|
-
0x8f,0xe8,0x48,0xee,0x58,0x04,0x30 = vpcomud $48, 4(%rax), %xmm6, %xmm3
|
124
|
-
0x8f,0xe8,0x58,0xec,0xeb,0x31 = vpcomub $49, %xmm3, %xmm4, %xmm5
|
125
|
-
0x8f,0xe8,0x48,0xec,0x11,0x32 = vpcomub $50, (%rcx), %xmm6, %xmm2
|
126
|
-
0x8f,0xe8,0x78,0xcf,0xeb,0x33 = vpcomq $51, %xmm3, %xmm0, %xmm5
|
127
|
-
0x8f,0xe8,0x70,0xcf,0x38,0x34 = vpcomq $52, (%rax), %xmm1, %xmm7
|
128
|
-
0x8f,0xe8,0x60,0xce,0xc3,0x35 = vpcomd $53, %xmm3, %xmm3, %xmm0
|
129
|
-
0x8f,0xe8,0x68,0xce,0x11,0x36 = vpcomd $54, (%rcx), %xmm2, %xmm2
|
130
|
-
0x8f,0xe8,0x58,0xcc,0xd6,0x37 = vpcomb $55, %xmm6, %xmm4, %xmm2
|
131
|
-
0x8f,0xe8,0x60,0xcc,0x50,0x08,0x38 = vpcomb $56, 8(%rax), %xmm3, %xmm2
|
132
|
-
0x8f,0xe8,0x60,0xa3,0xe2,0x10 = vpperm %xmm1, %xmm2, %xmm3, %xmm4
|
133
|
-
0x8f,0xe8,0xe0,0xa3,0x20,0x20 = vpperm (%rax), %xmm2, %xmm3, %xmm4
|
134
|
-
0x8f,0xe8,0x60,0xa3,0x20,0x10 = vpperm %xmm1, (%rax), %xmm3, %xmm4
|
135
|
-
0x8f,0xe8,0x60,0xa2,0xe2,0x10 = vpcmov %xmm1, %xmm2, %xmm3, %xmm4
|
136
|
-
0x8f,0xe8,0xe0,0xa2,0x20,0x20 = vpcmov (%rax), %xmm2, %xmm3, %xmm4
|
137
|
-
0x8f,0xe8,0x60,0xa2,0x20,0x10 = vpcmov %xmm1, (%rax), %xmm3, %xmm4
|
138
|
-
0x8f,0xe8,0x64,0xa2,0xe2,0x10 = vpcmov %ymm1, %ymm2, %ymm3, %ymm4
|
139
|
-
0x8f,0xe8,0xe4,0xa2,0x20,0x20 = vpcmov (%rax), %ymm2, %ymm3, %ymm4
|
140
|
-
0x8f,0xe8,0x64,0xa2,0x20,0x10 = vpcmov %ymm1, (%rax), %ymm3, %ymm4
|
141
|
-
0xc4,0xe3,0x71,0x49,0xfa,0x51 = vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7
|
142
|
-
0xc4,0xe3,0xe1,0x49,0x20,0x32 = vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4
|
143
|
-
0xc4,0xe3,0xdd,0x49,0x70,0x08,0x03 = vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6
|
144
|
-
0xc4,0xe3,0x71,0x49,0x04,0x08,0x30 = vpermil2pd $0, %xmm3, (%rax, %rcx), %xmm1, %xmm0
|
145
|
-
0xc4,0xe3,0x65,0x49,0xe2,0x11 = vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4
|
146
|
-
0xc4,0xe3,0x65,0x49,0x20,0x12 = vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4
|
147
|
-
0xc4,0xe3,0x69,0x48,0xcb,0x40 = vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1
|
148
|
-
0xc4,0xe3,0xe1,0x48,0x40,0x04,0x21 = vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0
|
149
|
-
0xc4,0xe3,0xd5,0x48,0x30,0x12 = vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6
|
150
|
-
0xc4,0xe3,0x61,0x48,0x20,0x13 = vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4
|
151
|
-
0xc4,0xe3,0x6d,0x48,0xd4,0x40 = vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2
|
152
|
-
0xc4,0xe3,0x75,0x49,0x40,0x04,0x11 = vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0
|
data/test/README
DELETED
data/test/test.rb
DELETED
@@ -1,205 +0,0 @@
|
|
1
|
-
#!/usr/bin/env ruby
|
2
|
-
|
3
|
-
# Library by Nguyen Anh Quynh
|
4
|
-
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
5
|
-
# Additional binding work by Ben Nagy
|
6
|
-
# (c) 2013 COSEINC. All Rights Reserved.
|
7
|
-
|
8
|
-
require 'crabstone'
|
9
|
-
require 'stringio'
|
10
|
-
|
11
|
-
module Test
|
12
|
-
|
13
|
-
include Crabstone
|
14
|
-
|
15
|
-
X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
|
16
|
-
X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
|
17
|
-
X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00"
|
18
|
-
ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
|
19
|
-
ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
|
20
|
-
ARMV8 = "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
|
21
|
-
THUMB_MCLASS = "\xef\xf3\x02\x80"
|
22
|
-
THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
|
23
|
-
THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
|
24
|
-
MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
|
25
|
-
MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00"
|
26
|
-
MIPS_32R6M = "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
|
27
|
-
MIPS_32R6 = "\xec\x80\x00\x19\x7c\x43\x22\xa0"
|
28
|
-
ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
|
29
|
-
PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
|
30
|
-
SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
|
31
|
-
SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
|
32
|
-
SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
|
33
|
-
XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
|
34
|
-
|
35
|
-
@platforms = [
|
36
|
-
Hash[
|
37
|
-
'arch' => ARCH_X86,
|
38
|
-
'mode' => MODE_16,
|
39
|
-
'code' => X86_CODE16,
|
40
|
-
'comment' => "X86 16bit (Intel syntax)"
|
41
|
-
],
|
42
|
-
Hash[
|
43
|
-
'arch' => ARCH_X86,
|
44
|
-
'mode' => MODE_32,
|
45
|
-
'code' => X86_CODE32,
|
46
|
-
'comment' => "X86 32bit (ATT syntax)",
|
47
|
-
'syntax' => :att,
|
48
|
-
],
|
49
|
-
Hash[
|
50
|
-
'arch' => ARCH_X86,
|
51
|
-
'mode' => MODE_32,
|
52
|
-
'code' => X86_CODE32,
|
53
|
-
'comment' => "X86 32 (Intel syntax)"
|
54
|
-
],
|
55
|
-
Hash[
|
56
|
-
'arch' => ARCH_X86,
|
57
|
-
'mode' => MODE_64,
|
58
|
-
'code' => X86_CODE64,
|
59
|
-
'comment' => "X86 64 (Intel syntax)"
|
60
|
-
],
|
61
|
-
Hash[
|
62
|
-
'arch' => ARCH_ARM,
|
63
|
-
'mode' => MODE_ARM,
|
64
|
-
'code' => ARM_CODE,
|
65
|
-
'comment' => "ARM"
|
66
|
-
],
|
67
|
-
Hash[
|
68
|
-
'arch' => ARCH_ARM,
|
69
|
-
'mode' => MODE_THUMB,
|
70
|
-
'code' => THUMB_CODE2,
|
71
|
-
'comment' => "THUMB-2"
|
72
|
-
],
|
73
|
-
Hash[
|
74
|
-
'arch' => ARCH_ARM,
|
75
|
-
'mode' => MODE_ARM,
|
76
|
-
'code' => ARM_CODE2,
|
77
|
-
'comment' => "ARM: Cortex-A15 + NEON"
|
78
|
-
],
|
79
|
-
Hash[
|
80
|
-
'arch' => ARCH_ARM,
|
81
|
-
'mode' => MODE_THUMB,
|
82
|
-
'code' => THUMB_CODE,
|
83
|
-
'comment' => "THUMB"
|
84
|
-
],
|
85
|
-
Hash[
|
86
|
-
'arch' => ARCH_ARM,
|
87
|
-
'mode' => MODE_THUMB + MODE_MCLASS,
|
88
|
-
'code' => THUMB_MCLASS,
|
89
|
-
'comment' => "Thumb-MClass"
|
90
|
-
],
|
91
|
-
Hash[
|
92
|
-
'arch' => ARCH_ARM,
|
93
|
-
'mode' => MODE_ARM + MODE_V8,
|
94
|
-
'code' => ARMV8,
|
95
|
-
'comment' => "Arm-V8"
|
96
|
-
],
|
97
|
-
Hash[
|
98
|
-
'arch' => ARCH_MIPS,
|
99
|
-
'mode' => MODE_32 + MODE_BIG_ENDIAN,
|
100
|
-
'code' => MIPS_CODE,
|
101
|
-
'comment' => "MIPS-32 (Big-endian)"
|
102
|
-
],
|
103
|
-
Hash[
|
104
|
-
'arch' => ARCH_MIPS,
|
105
|
-
'mode' => MODE_64 + MODE_LITTLE_ENDIAN,
|
106
|
-
'code' => MIPS_CODE2,
|
107
|
-
'comment' => "MIPS-64-EL (Little-endian)"
|
108
|
-
],
|
109
|
-
Hash[
|
110
|
-
'arch' => ARCH_MIPS,
|
111
|
-
'mode' => MODE_MIPS32R6 + MODE_MICRO + MODE_BIG_ENDIAN,
|
112
|
-
'code' => MIPS_32R6M,
|
113
|
-
'comment' => "MIPS-32R6 | Micro (Big-endian)"
|
114
|
-
],
|
115
|
-
Hash[
|
116
|
-
'arch' => ARCH_MIPS,
|
117
|
-
'mode' => MODE_MIPS32R6 + MODE_BIG_ENDIAN,
|
118
|
-
'code' => MIPS_32R6,
|
119
|
-
'comment' => "MIPS-32R6 (Big-endian)"
|
120
|
-
],
|
121
|
-
Hash[
|
122
|
-
'arch' => ARCH_ARM64,
|
123
|
-
'mode' => MODE_ARM,
|
124
|
-
'code' => ARM64_CODE,
|
125
|
-
'comment' => "ARM-64"
|
126
|
-
],
|
127
|
-
Hash[
|
128
|
-
'arch' => ARCH_PPC,
|
129
|
-
'mode' => MODE_BIG_ENDIAN,
|
130
|
-
'code' => PPC_CODE,
|
131
|
-
'comment' => "PPC-64"
|
132
|
-
],
|
133
|
-
Hash[
|
134
|
-
'arch' => ARCH_PPC,
|
135
|
-
'mode' => MODE_BIG_ENDIAN,
|
136
|
-
'code' => PPC_CODE,
|
137
|
-
'syntax' => :no_regname,
|
138
|
-
'comment' => "PPC-64, print register with number only"
|
139
|
-
],
|
140
|
-
Hash[
|
141
|
-
'arch' => ARCH_SPARC,
|
142
|
-
'mode' => MODE_BIG_ENDIAN,
|
143
|
-
'code' => SPARC_CODE,
|
144
|
-
'comment' => "Sparc"
|
145
|
-
],
|
146
|
-
Hash[
|
147
|
-
'arch' => ARCH_SPARC,
|
148
|
-
'mode' => MODE_BIG_ENDIAN + MODE_V9,
|
149
|
-
'code' => SPARCV9_CODE,
|
150
|
-
'comment' => "SparcV9"
|
151
|
-
],
|
152
|
-
Hash[
|
153
|
-
'arch' => ARCH_SYSZ,
|
154
|
-
'mode' => MODE_BIG_ENDIAN,
|
155
|
-
'code' => SYSZ_CODE,
|
156
|
-
'comment' => "SystemZ"
|
157
|
-
],
|
158
|
-
Hash[
|
159
|
-
'arch' => ARCH_XCORE,
|
160
|
-
'mode' => MODE_BIG_ENDIAN,
|
161
|
-
'code' => XCORE_CODE,
|
162
|
-
'comment' => "XCore"
|
163
|
-
]
|
164
|
-
]
|
165
|
-
|
166
|
-
ours = StringIO.new
|
167
|
-
|
168
|
-
begin
|
169
|
-
cs = Disassembler.new(0,0)
|
170
|
-
puts "Capstone Diet Mode: #{DIET_MODE}"
|
171
|
-
print "Basic Test: Capstone v #{cs.version.join('.')} - "
|
172
|
-
ensure
|
173
|
-
cs.close rescue nil
|
174
|
-
end
|
175
|
-
|
176
|
-
#Test through all modes and architectures
|
177
|
-
@platforms.each do |p|
|
178
|
-
ours.puts "****************"
|
179
|
-
ours.puts "Platform: #{p['comment']}"
|
180
|
-
ours.puts "Code: #{p['code'].bytes.map {|b| "0x%.2x" % b}.join(' ')} "
|
181
|
-
ours.puts "Disasm:"
|
182
|
-
cs = Disassembler.new(p['arch'], p['mode'])
|
183
|
-
if p['syntax']
|
184
|
-
cs.syntax = p['syntax']
|
185
|
-
end
|
186
|
-
cache = nil
|
187
|
-
cs.disasm(p['code'], 0x1000).each {|insn|
|
188
|
-
ours.printf("0x%x:\t%s\t\t%s\n",insn.address, insn.mnemonic, insn.op_str)
|
189
|
-
cache = insn.address + insn.size
|
190
|
-
}
|
191
|
-
ours.printf("0x%x:\n", cache)
|
192
|
-
cs.close
|
193
|
-
ours.puts
|
194
|
-
end
|
195
|
-
|
196
|
-
ours.rewind
|
197
|
-
theirs = File.binread(__FILE__ + ".SPEC")
|
198
|
-
if ours.read == theirs
|
199
|
-
puts "#{__FILE__}: PASS"
|
200
|
-
else
|
201
|
-
ours.rewind
|
202
|
-
puts ours.read
|
203
|
-
puts "#{__FILE__}: FAIL"
|
204
|
-
end
|
205
|
-
end
|
data/test/test.rb.SPEC
DELETED
@@ -1,235 +0,0 @@
|
|
1
|
-
****************
|
2
|
-
Platform: X86 16bit (Intel syntax)
|
3
|
-
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00
|
4
|
-
Disasm:
|
5
|
-
0x1000: lea cx, word ptr [si + 0x32]
|
6
|
-
0x1003: or byte ptr [bx + di], al
|
7
|
-
0x1005: fadd dword ptr [bx + di + 0x34c6]
|
8
|
-
0x1009: adc al, byte ptr [bx + si]
|
9
|
-
0x100b:
|
10
|
-
|
11
|
-
****************
|
12
|
-
Platform: X86 32bit (ATT syntax)
|
13
|
-
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00
|
14
|
-
Disasm:
|
15
|
-
0x1000: leal 8(%edx, %esi), %ecx
|
16
|
-
0x1004: addl %ebx, %eax
|
17
|
-
0x1006: addl $0x1234, %esi
|
18
|
-
0x100c:
|
19
|
-
|
20
|
-
****************
|
21
|
-
Platform: X86 32 (Intel syntax)
|
22
|
-
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00
|
23
|
-
Disasm:
|
24
|
-
0x1000: lea ecx, dword ptr [edx + esi + 8]
|
25
|
-
0x1004: add eax, ebx
|
26
|
-
0x1006: add esi, 0x1234
|
27
|
-
0x100c:
|
28
|
-
|
29
|
-
****************
|
30
|
-
Platform: X86 64 (Intel syntax)
|
31
|
-
Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00
|
32
|
-
Disasm:
|
33
|
-
0x1000: push rbp
|
34
|
-
0x1001: mov rax, qword ptr [rip + 0x13b8]
|
35
|
-
0x1008:
|
36
|
-
|
37
|
-
****************
|
38
|
-
Platform: ARM
|
39
|
-
Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3
|
40
|
-
Disasm:
|
41
|
-
0x1000: bl #0xfbc
|
42
|
-
0x1004: str lr, [sp, #-4]!
|
43
|
-
0x1008: andeq r0, r0, r0
|
44
|
-
0x100c: str r8, [r2, #-0x3e0]!
|
45
|
-
0x1010: mcreq p2, #0, r0, c3, c1, #7
|
46
|
-
0x1014: mov r0, #0
|
47
|
-
0x1018: strb r3, [r1, r2]
|
48
|
-
0x101c: cmp r3, #0
|
49
|
-
0x1020:
|
50
|
-
|
51
|
-
****************
|
52
|
-
Platform: THUMB-2
|
53
|
-
Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0
|
54
|
-
Disasm:
|
55
|
-
0x1000: mov.w r1, #0
|
56
|
-
0x1004: pop.w {fp, pc}
|
57
|
-
0x1008: tbb [r1, r0]
|
58
|
-
0x100c:
|
59
|
-
|
60
|
-
****************
|
61
|
-
Platform: ARM: Cortex-A15 + NEON
|
62
|
-
Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3
|
63
|
-
Disasm:
|
64
|
-
0x1000: sdiv r0, r0, r1
|
65
|
-
0x1004: udiv r1, r1, r2
|
66
|
-
0x1008: vbit q5, q15, q6
|
67
|
-
0x100c: vcgt.f32 q10, q9, q12
|
68
|
-
0x1010:
|
69
|
-
|
70
|
-
****************
|
71
|
-
Platform: THUMB
|
72
|
-
Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68
|
73
|
-
Disasm:
|
74
|
-
0x1000: bx lr
|
75
|
-
0x1002: mov fp, sp
|
76
|
-
0x1004: sub sp, #0xc
|
77
|
-
0x1006: ldr r1, [r1, #0xc]
|
78
|
-
0x1008:
|
79
|
-
|
80
|
-
****************
|
81
|
-
Platform: Thumb-MClass
|
82
|
-
Code: 0xef 0xf3 0x02 0x80
|
83
|
-
Disasm:
|
84
|
-
0x1000: mrs r0, eapsr
|
85
|
-
0x1004:
|
86
|
-
|
87
|
-
****************
|
88
|
-
Platform: Arm-V8
|
89
|
-
Code: 0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5
|
90
|
-
Disasm:
|
91
|
-
0x1000: vcvtt.f64.f16 d3, s1
|
92
|
-
0x1004: crc32b r0, r1, r2
|
93
|
-
0x1008: dmb oshld
|
94
|
-
0x100c:
|
95
|
-
|
96
|
-
****************
|
97
|
-
Platform: MIPS-32 (Big-endian)
|
98
|
-
Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56
|
99
|
-
Disasm:
|
100
|
-
0x1000: jal 0x40025c
|
101
|
-
0x1004: nop
|
102
|
-
0x1008: addiu $v0, $zero, 0xc
|
103
|
-
0x100c: lw $v0, ($sp)
|
104
|
-
0x1010: ori $at, $at, 0x3456
|
105
|
-
0x1014:
|
106
|
-
|
107
|
-
****************
|
108
|
-
Platform: MIPS-64-EL (Little-endian)
|
109
|
-
Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00
|
110
|
-
Disasm:
|
111
|
-
0x1000: ori $at, $at, 0x3456
|
112
|
-
0x1004: srl $v0, $at, 0x1f
|
113
|
-
0x1008:
|
114
|
-
|
115
|
-
****************
|
116
|
-
Platform: MIPS-32R6 | Micro (Big-endian)
|
117
|
-
Code: 0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0
|
118
|
-
Disasm:
|
119
|
-
0x1000: break 7, 0
|
120
|
-
0x1004: wait 0x11
|
121
|
-
0x1008: syscall 0x18c
|
122
|
-
0x100c: rotrv $t1, $a2, $a3
|
123
|
-
0x1010:
|
124
|
-
|
125
|
-
****************
|
126
|
-
Platform: MIPS-32R6 (Big-endian)
|
127
|
-
Code: 0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0
|
128
|
-
Disasm:
|
129
|
-
0x1000: addiupc $a0, 0x64
|
130
|
-
0x1004: align $a0, $v0, $v1, 2
|
131
|
-
0x1008:
|
132
|
-
|
133
|
-
****************
|
134
|
-
Platform: ARM-64
|
135
|
-
Code: 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9
|
136
|
-
Disasm:
|
137
|
-
0x1000: mul x1, x1, x2
|
138
|
-
0x1004: lsr w1, w1, #0
|
139
|
-
0x1008: sub w0, w0, w1, uxtw
|
140
|
-
0x100c: ldr w1, [sp, #8]
|
141
|
-
0x1010:
|
142
|
-
|
143
|
-
****************
|
144
|
-
Platform: PPC-64
|
145
|
-
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21
|
146
|
-
Disasm:
|
147
|
-
0x1000: lwz r1, (0)
|
148
|
-
0x1004: lwz r1, (r31)
|
149
|
-
0x1008: vpkpx v2, v3, v4
|
150
|
-
0x100c: stfs f2, 0x80(r4)
|
151
|
-
0x1010: crand 2, 3, 4
|
152
|
-
0x1014: cmpwi cr2, r3, 0x80
|
153
|
-
0x1018: addc r2, r3, r4
|
154
|
-
0x101c: mulhd. r2, r3, r4
|
155
|
-
0x1020: bdnzlrl+
|
156
|
-
0x1024: bgelrl- cr2
|
157
|
-
0x1028:
|
158
|
-
|
159
|
-
****************
|
160
|
-
Platform: PPC-64, print register with number only
|
161
|
-
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21
|
162
|
-
Disasm:
|
163
|
-
0x1000: lwz 1, (0)
|
164
|
-
0x1004: lwz 1, (31)
|
165
|
-
0x1008: vpkpx 2, 3, 4
|
166
|
-
0x100c: stfs 2, 0x80(4)
|
167
|
-
0x1010: crand 2, 3, 4
|
168
|
-
0x1014: cmpwi 2, 3, 0x80
|
169
|
-
0x1018: addc 2, 3, 4
|
170
|
-
0x101c: mulhd. 2, 3, 4
|
171
|
-
0x1020: bdnzlrl+
|
172
|
-
0x1024: bgelrl- cr2
|
173
|
-
0x1028:
|
174
|
-
|
175
|
-
****************
|
176
|
-
Platform: Sparc
|
177
|
-
Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03
|
178
|
-
Disasm:
|
179
|
-
0x1000: cmp %g1, %g2
|
180
|
-
0x1004: jmpl %o1+8, %g2
|
181
|
-
0x1008: restore %g0, 1, %g2
|
182
|
-
0x100c: restore
|
183
|
-
0x1010: mov 1, %o0
|
184
|
-
0x1014: casx [%i0], %l6, %o2
|
185
|
-
0x1018: sethi 0xa, %l0
|
186
|
-
0x101c: add %g1, %g2, %g3
|
187
|
-
0x1020: nop
|
188
|
-
0x1024: bne 0x1020
|
189
|
-
0x1028: ba 0x1024
|
190
|
-
0x102c: add %o0, %o1, %l0
|
191
|
-
0x1030: fbg 0x102c
|
192
|
-
0x1034: st %o2, [%g1]
|
193
|
-
0x1038: ldsb [%i0+%l6], %o2
|
194
|
-
0x103c: brnz,a,pn %o2, 0x1048
|
195
|
-
0x1040:
|
196
|
-
|
197
|
-
****************
|
198
|
-
Platform: SparcV9
|
199
|
-
Code: 0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0
|
200
|
-
Disasm:
|
201
|
-
0x1000: fcmps %f0, %f4
|
202
|
-
0x1004: fstox %f0, %f4
|
203
|
-
0x1008: fqtoi %f0, %f4
|
204
|
-
0x100c: fnegq %f0, %f4
|
205
|
-
0x1010:
|
206
|
-
|
207
|
-
****************
|
208
|
-
Platform: SystemZ
|
209
|
-
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78
|
210
|
-
Disasm:
|
211
|
-
0x1000: adb %f0, 0
|
212
|
-
0x1006: a %r0, 0xfff(%r15, %r1)
|
213
|
-
0x100a: afi %r0, -0x80000000
|
214
|
-
0x1010: br %r7
|
215
|
-
0x1012: xiy 0x7ffff(%r15), 0x2a
|
216
|
-
0x1018: xy %r0, 0x7ffff(%r1, %r15)
|
217
|
-
0x101e: stmg %r0, %r0, 0(%r15)
|
218
|
-
0x1024: ear %r7, %a8
|
219
|
-
0x1028:
|
220
|
-
|
221
|
-
****************
|
222
|
-
Platform: XCore
|
223
|
-
Code: 0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10
|
224
|
-
Disasm:
|
225
|
-
0x1000: get r11, ed
|
226
|
-
0x1002: ldw et, sp[4]
|
227
|
-
0x1004: setd res[r3], r4
|
228
|
-
0x1006: init t[r2]:lr, r1
|
229
|
-
0x100a: divu r9, r1, r3
|
230
|
-
0x100e: lda16 r9, r3[-r11]
|
231
|
-
0x1012: ldw dp, dp[0x81c5]
|
232
|
-
0x1016: lmul r11, r0, r2, r5, r8, r10
|
233
|
-
0x101a: add r1, r2, r3
|
234
|
-
0x101c:
|
235
|
-
|