crabstone 3.0.3 → 4.0.0
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +5 -5
- data/CHANGES.md +45 -42
- data/README.md +16 -33
- data/lib/crabstone.rb +5 -557
- data/lib/crabstone/arch.rb +37 -0
- data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
- data/lib/crabstone/arch/3/arm64.rb +124 -0
- data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
- data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
- data/lib/crabstone/arch/3/mips.rb +57 -0
- data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
- data/lib/crabstone/arch/3/ppc.rb +73 -0
- data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
- data/lib/crabstone/arch/3/sparc.rb +60 -0
- data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
- data/lib/crabstone/arch/3/sysz.rb +67 -0
- data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
- data/lib/crabstone/arch/3/x86.rb +82 -0
- data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
- data/lib/crabstone/arch/3/xcore.rb +59 -0
- data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
- data/lib/crabstone/arch/4/arm.rb +110 -0
- data/lib/crabstone/arch/4/arm64.rb +125 -0
- data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
- data/lib/crabstone/arch/4/arm_const.rb +785 -0
- data/lib/crabstone/arch/4/evm.rb +20 -0
- data/lib/crabstone/arch/4/evm_const.rb +161 -0
- data/lib/crabstone/arch/4/m680x.rb +106 -0
- data/lib/crabstone/arch/4/m680x_const.rb +426 -0
- data/lib/crabstone/arch/4/m68k.rb +129 -0
- data/lib/crabstone/arch/4/m68k_const.rb +496 -0
- data/lib/crabstone/arch/4/mips.rb +57 -0
- data/lib/crabstone/arch/4/mips_const.rb +869 -0
- data/lib/crabstone/arch/4/ppc.rb +73 -0
- data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
- data/lib/crabstone/arch/4/sparc.rb +60 -0
- data/lib/crabstone/arch/4/sparc_const.rb +439 -0
- data/lib/crabstone/arch/4/sysz.rb +67 -0
- data/lib/crabstone/arch/4/sysz_const.rb +763 -0
- data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
- data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
- data/lib/crabstone/arch/4/x86.rb +91 -0
- data/lib/crabstone/arch/4/x86_const.rb +1972 -0
- data/lib/crabstone/arch/4/xcore.rb +59 -0
- data/lib/crabstone/arch/4/xcore_const.rb +171 -0
- data/lib/crabstone/arch/extension.rb +27 -0
- data/lib/crabstone/arch/register.rb +36 -0
- data/lib/crabstone/binding.rb +60 -0
- data/lib/crabstone/binding/3/detail.rb +36 -0
- data/lib/crabstone/binding/3/instruction.rb +23 -0
- data/lib/crabstone/binding/4/detail.rb +40 -0
- data/lib/crabstone/binding/4/instruction.rb +23 -0
- data/lib/crabstone/binding/structs.rb +32 -0
- data/lib/crabstone/constants.rb +110 -0
- data/lib/crabstone/cs_version.rb +49 -0
- data/lib/crabstone/disassembler.rb +153 -0
- data/lib/crabstone/error.rb +60 -0
- data/lib/crabstone/instruction.rb +183 -0
- data/lib/crabstone/version.rb +5 -0
- metadata +128 -324
- data/MANIFEST +0 -312
- data/Rakefile +0 -27
- data/bin/genconst +0 -66
- data/bin/genreg +0 -99
- data/crabstone.gemspec +0 -27
- data/examples/hello_world.rb +0 -43
- data/lib/arch/arm64.rb +0 -167
- data/lib/arch/arm64_registers.rb +0 -295
- data/lib/arch/arm_registers.rb +0 -149
- data/lib/arch/mips.rb +0 -78
- data/lib/arch/mips_registers.rb +0 -208
- data/lib/arch/ppc.rb +0 -90
- data/lib/arch/ppc_registers.rb +0 -209
- data/lib/arch/sparc.rb +0 -79
- data/lib/arch/sparc_registers.rb +0 -121
- data/lib/arch/systemz.rb +0 -79
- data/lib/arch/sysz_registers.rb +0 -66
- data/lib/arch/x86.rb +0 -107
- data/lib/arch/x86_registers.rb +0 -265
- data/lib/arch/xcore.rb +0 -78
- data/lib/arch/xcore_registers.rb +0 -57
- data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
- data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
- data/test/MC/AArch64/neon-2velem.s.cs +0 -113
- data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
- data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
- data/test/MC/AArch64/neon-across.s.cs +0 -40
- data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
- data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
- data/test/MC/AArch64/neon-crypto.s.cs +0 -15
- data/test/MC/AArch64/neon-extract.s.cs +0 -3
- data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
- data/test/MC/AArch64/neon-max-min.s.cs +0 -37
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
- data/test/MC/AArch64/neon-mov.s.cs +0 -74
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
- data/test/MC/AArch64/neon-perm.s.cs +0 -43
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
- data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
- data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
- data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
- data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
- data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
- data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
- data/test/MC/AArch64/neon-shift.s.cs +0 -22
- data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
- data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
- data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
- data/test/MC/AArch64/neon-tbl.s.cs +0 -21
- data/test/MC/AArch64/trace-regs.s.cs +0 -383
- data/test/MC/ARM/arm-aliases.s.cs +0 -7
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
- data/test/MC/ARM/arm-it-block.s.cs +0 -2
- data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
- data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
- data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
- data/test/MC/ARM/arm_instructions.s.cs +0 -25
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
- data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
- data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
- data/test/MC/ARM/crc32-thumb.s.cs +0 -7
- data/test/MC/ARM/crc32.s.cs +0 -7
- data/test/MC/ARM/dot-req.s.cs +0 -3
- data/test/MC/ARM/fp-armv8.s.cs +0 -52
- data/test/MC/ARM/idiv-thumb.s.cs +0 -3
- data/test/MC/ARM/idiv.s.cs +0 -3
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
- data/test/MC/ARM/mode-switch.s.cs +0 -7
- data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
- data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
- data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
- data/test/MC/ARM/neon-crypto.s.cs +0 -16
- data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
- data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
- data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
- data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neon-v8.s.cs +0 -38
- data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
- data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
- data/test/MC/ARM/neon-vswp.s.cs +0 -3
- data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
- data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
- data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
- data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
- data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
- data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
- data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
- data/test/MC/ARM/thumb-hints.s.cs +0 -12
- data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
- data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
- data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
- data/test/MC/ARM/thumb.s.cs +0 -19
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
- data/test/MC/ARM/thumb2-branches.s.cs +0 -85
- data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
- data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
- data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
- data/test/MC/ARM/vfp4.s.cs +0 -13
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
- data/test/MC/ARM/vpush-vpop.s.cs +0 -9
- data/test/MC/Mips/hilo-addressing.s.cs +0 -4
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
- data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
- data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
- data/test/MC/Mips/micromips-expansions.s.cs +0 -20
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
- data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
- data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
- data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
- data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
- data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
- data/test/MC/Mips/mips-expansions.s.cs +0 -20
- data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
- data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
- data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
- data/test/MC/Mips/mips-register-names.s.cs +0 -33
- data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
- data/test/MC/Mips/mips64-instructions.s.cs +0 -3
- data/test/MC/Mips/mips64-register-names.s.cs +0 -33
- data/test/MC/Mips/mips_directives.s.cs +0 -12
- data/test/MC/Mips/nabi-regs.s.cs +0 -12
- data/test/MC/Mips/set-at-directive.s.cs +0 -6
- data/test/MC/Mips/test_2r.s.cs +0 -16
- data/test/MC/Mips/test_2rf.s.cs +0 -33
- data/test/MC/Mips/test_3r.s.cs +0 -243
- data/test/MC/Mips/test_3rf.s.cs +0 -83
- data/test/MC/Mips/test_bit.s.cs +0 -49
- data/test/MC/Mips/test_cbranch.s.cs +0 -11
- data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
- data/test/MC/Mips/test_elm.s.cs +0 -16
- data/test/MC/Mips/test_elm_insert.s.cs +0 -4
- data/test/MC/Mips/test_elm_insve.s.cs +0 -5
- data/test/MC/Mips/test_i10.s.cs +0 -5
- data/test/MC/Mips/test_i5.s.cs +0 -45
- data/test/MC/Mips/test_i8.s.cs +0 -11
- data/test/MC/Mips/test_lsa.s.cs +0 -5
- data/test/MC/Mips/test_mi10.s.cs +0 -24
- data/test/MC/Mips/test_vec.s.cs +0 -8
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
- data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
- data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
- data/test/MC/README +0 -6
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
- data/test/MC/Sparc/sparc-vis.s.cs +0 -2
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
- data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
- data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
- data/test/MC/SystemZ/insn-good.s.cs +0 -2265
- data/test/MC/SystemZ/regs-good.s.cs +0 -45
- data/test/MC/X86/3DNow.s.cs +0 -29
- data/test/MC/X86/address-size.s.cs +0 -5
- data/test/MC/X86/avx512-encodings.s.cs +0 -12
- data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
- data/test/MC/X86/x86-32-avx.s.cs +0 -833
- data/test/MC/X86/x86-32-fma3.s.cs +0 -169
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
- data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
- data/test/MC/X86/x86_64-encoding.s.cs +0 -59
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
- data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
- data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
- data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
- data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
- data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
- data/test/README +0 -6
- data/test/test.rb +0 -205
- data/test/test.rb.SPEC +0 -235
- data/test/test_arm.rb +0 -202
- data/test/test_arm.rb.SPEC +0 -275
- data/test/test_arm64.rb +0 -150
- data/test/test_arm64.rb.SPEC +0 -116
- data/test/test_detail.rb +0 -228
- data/test/test_detail.rb.SPEC +0 -322
- data/test/test_exhaustive.rb +0 -80
- data/test/test_mips.rb +0 -118
- data/test/test_mips.rb.SPEC +0 -91
- data/test/test_ppc.rb +0 -137
- data/test/test_ppc.rb.SPEC +0 -84
- data/test/test_sanity.rb +0 -83
- data/test/test_skipdata.rb +0 -111
- data/test/test_skipdata.rb.SPEC +0 -58
- data/test/test_sparc.rb +0 -113
- data/test/test_sparc.rb.SPEC +0 -116
- data/test/test_sysz.rb +0 -111
- data/test/test_sysz.rb.SPEC +0 -61
- data/test/test_x86.rb +0 -189
- data/test/test_x86.rb.SPEC +0 -579
- data/test/test_xcore.rb +0 -100
- data/test/test_xcore.rb.SPEC +0 -75
@@ -1,43 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x18,0x02,0x0e = uzp1 v0.8b, v1.8b, v2.8b
|
3
|
-
0x20,0x18,0x02,0x4e = uzp1 v0.16b, v1.16b, v2.16b
|
4
|
-
0x20,0x18,0x42,0x0e = uzp1 v0.4h, v1.4h, v2.4h
|
5
|
-
0x20,0x18,0x42,0x4e = uzp1 v0.8h, v1.8h, v2.8h
|
6
|
-
0x20,0x18,0x82,0x0e = uzp1 v0.2s, v1.2s, v2.2s
|
7
|
-
0x20,0x18,0x82,0x4e = uzp1 v0.4s, v1.4s, v2.4s
|
8
|
-
0x20,0x18,0xc2,0x4e = uzp1 v0.2d, v1.2d, v2.2d
|
9
|
-
0x20,0x28,0x02,0x0e = trn1 v0.8b, v1.8b, v2.8b
|
10
|
-
0x20,0x28,0x02,0x4e = trn1 v0.16b, v1.16b, v2.16b
|
11
|
-
0x20,0x28,0x42,0x0e = trn1 v0.4h, v1.4h, v2.4h
|
12
|
-
0x20,0x28,0x42,0x4e = trn1 v0.8h, v1.8h, v2.8h
|
13
|
-
0x20,0x28,0x82,0x0e = trn1 v0.2s, v1.2s, v2.2s
|
14
|
-
0x20,0x28,0x82,0x4e = trn1 v0.4s, v1.4s, v2.4s
|
15
|
-
0x20,0x28,0xc2,0x4e = trn1 v0.2d, v1.2d, v2.2d
|
16
|
-
0x20,0x38,0x02,0x0e = zip1 v0.8b, v1.8b, v2.8b
|
17
|
-
0x20,0x38,0x02,0x4e = zip1 v0.16b, v1.16b, v2.16b
|
18
|
-
0x20,0x38,0x42,0x0e = zip1 v0.4h, v1.4h, v2.4h
|
19
|
-
0x20,0x38,0x42,0x4e = zip1 v0.8h, v1.8h, v2.8h
|
20
|
-
0x20,0x38,0x82,0x0e = zip1 v0.2s, v1.2s, v2.2s
|
21
|
-
0x20,0x38,0x82,0x4e = zip1 v0.4s, v1.4s, v2.4s
|
22
|
-
0x20,0x38,0xc2,0x4e = zip1 v0.2d, v1.2d, v2.2d
|
23
|
-
0x20,0x58,0x02,0x0e = uzp2 v0.8b, v1.8b, v2.8b
|
24
|
-
0x20,0x58,0x02,0x4e = uzp2 v0.16b, v1.16b, v2.16b
|
25
|
-
0x20,0x58,0x42,0x0e = uzp2 v0.4h, v1.4h, v2.4h
|
26
|
-
0x20,0x58,0x42,0x4e = uzp2 v0.8h, v1.8h, v2.8h
|
27
|
-
0x20,0x58,0x82,0x0e = uzp2 v0.2s, v1.2s, v2.2s
|
28
|
-
0x20,0x58,0x82,0x4e = uzp2 v0.4s, v1.4s, v2.4s
|
29
|
-
0x20,0x58,0xc2,0x4e = uzp2 v0.2d, v1.2d, v2.2d
|
30
|
-
0x20,0x68,0x02,0x0e = trn2 v0.8b, v1.8b, v2.8b
|
31
|
-
0x20,0x68,0x02,0x4e = trn2 v0.16b, v1.16b, v2.16b
|
32
|
-
0x20,0x68,0x42,0x0e = trn2 v0.4h, v1.4h, v2.4h
|
33
|
-
0x20,0x68,0x42,0x4e = trn2 v0.8h, v1.8h, v2.8h
|
34
|
-
0x20,0x68,0x82,0x0e = trn2 v0.2s, v1.2s, v2.2s
|
35
|
-
0x20,0x68,0x82,0x4e = trn2 v0.4s, v1.4s, v2.4s
|
36
|
-
0x20,0x68,0xc2,0x4e = trn2 v0.2d, v1.2d, v2.2d
|
37
|
-
0x20,0x78,0x02,0x0e = zip2 v0.8b, v1.8b, v2.8b
|
38
|
-
0x20,0x78,0x02,0x4e = zip2 v0.16b, v1.16b, v2.16b
|
39
|
-
0x20,0x78,0x42,0x0e = zip2 v0.4h, v1.4h, v2.4h
|
40
|
-
0x20,0x78,0x42,0x4e = zip2 v0.8h, v1.8h, v2.8h
|
41
|
-
0x20,0x78,0x82,0x0e = zip2 v0.2s, v1.2s, v2.2s
|
42
|
-
0x20,0x78,0x82,0x4e = zip2 v0.4s, v1.4s, v2.4s
|
43
|
-
0x20,0x78,0xc2,0x4e = zip2 v0.2d, v1.2d, v2.2d
|
@@ -1,13 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x14,0x22,0x0e = srhadd v0.8b, v1.8b, v2.8b
|
3
|
-
0x20,0x14,0x22,0x4e = srhadd v0.16b, v1.16b, v2.16b
|
4
|
-
0x20,0x14,0x62,0x0e = srhadd v0.4h, v1.4h, v2.4h
|
5
|
-
0x20,0x14,0x62,0x4e = srhadd v0.8h, v1.8h, v2.8h
|
6
|
-
0x20,0x14,0xa2,0x0e = srhadd v0.2s, v1.2s, v2.2s
|
7
|
-
0x20,0x14,0xa2,0x4e = srhadd v0.4s, v1.4s, v2.4s
|
8
|
-
0x20,0x14,0x22,0x2e = urhadd v0.8b, v1.8b, v2.8b
|
9
|
-
0x20,0x14,0x22,0x6e = urhadd v0.16b, v1.16b, v2.16b
|
10
|
-
0x20,0x14,0x62,0x2e = urhadd v0.4h, v1.4h, v2.4h
|
11
|
-
0x20,0x14,0x62,0x6e = urhadd v0.8h, v1.8h, v2.8h
|
12
|
-
0x20,0x14,0xa2,0x2e = urhadd v0.2s, v1.2s, v2.2s
|
13
|
-
0x20,0x14,0xa2,0x6e = urhadd v0.4s, v1.4s, v2.4s
|
@@ -1,15 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x54,0x22,0x0e = srshl v0.8b, v1.8b, v2.8b
|
3
|
-
0x20,0x54,0x22,0x4e = srshl v0.16b, v1.16b, v2.16b
|
4
|
-
0x20,0x54,0x62,0x0e = srshl v0.4h, v1.4h, v2.4h
|
5
|
-
0x20,0x54,0x62,0x4e = srshl v0.8h, v1.8h, v2.8h
|
6
|
-
0x20,0x54,0xa2,0x0e = srshl v0.2s, v1.2s, v2.2s
|
7
|
-
0x20,0x54,0xa2,0x4e = srshl v0.4s, v1.4s, v2.4s
|
8
|
-
0x20,0x54,0xe2,0x4e = srshl v0.2d, v1.2d, v2.2d
|
9
|
-
0x20,0x54,0x22,0x2e = urshl v0.8b, v1.8b, v2.8b
|
10
|
-
0x20,0x54,0x22,0x6e = urshl v0.16b, v1.16b, v2.16b
|
11
|
-
0x20,0x54,0x62,0x2e = urshl v0.4h, v1.4h, v2.4h
|
12
|
-
0x20,0x54,0x62,0x6e = urshl v0.8h, v1.8h, v2.8h
|
13
|
-
0x20,0x54,0xa2,0x2e = urshl v0.2s, v1.2s, v2.2s
|
14
|
-
0x20,0x54,0xa2,0x6e = urshl v0.4s, v1.4s, v2.4s
|
15
|
-
0x20,0x54,0xe2,0x6e = urshl v0.2d, v1.2d, v2.2d
|
@@ -1,29 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x0c,0x22,0x0e = sqadd v0.8b, v1.8b, v2.8b
|
3
|
-
0x20,0x0c,0x22,0x4e = sqadd v0.16b, v1.16b, v2.16b
|
4
|
-
0x20,0x0c,0x62,0x0e = sqadd v0.4h, v1.4h, v2.4h
|
5
|
-
0x20,0x0c,0x62,0x4e = sqadd v0.8h, v1.8h, v2.8h
|
6
|
-
0x20,0x0c,0xa2,0x0e = sqadd v0.2s, v1.2s, v2.2s
|
7
|
-
0x20,0x0c,0xa2,0x4e = sqadd v0.4s, v1.4s, v2.4s
|
8
|
-
0x20,0x0c,0xe2,0x4e = sqadd v0.2d, v1.2d, v2.2d
|
9
|
-
0x20,0x0c,0x22,0x2e = uqadd v0.8b, v1.8b, v2.8b
|
10
|
-
0x20,0x0c,0x22,0x6e = uqadd v0.16b, v1.16b, v2.16b
|
11
|
-
0x20,0x0c,0x62,0x2e = uqadd v0.4h, v1.4h, v2.4h
|
12
|
-
0x20,0x0c,0x62,0x6e = uqadd v0.8h, v1.8h, v2.8h
|
13
|
-
0x20,0x0c,0xa2,0x2e = uqadd v0.2s, v1.2s, v2.2s
|
14
|
-
0x20,0x0c,0xa2,0x6e = uqadd v0.4s, v1.4s, v2.4s
|
15
|
-
0x20,0x0c,0xe2,0x6e = uqadd v0.2d, v1.2d, v2.2d
|
16
|
-
0x20,0x2c,0x22,0x0e = sqsub v0.8b, v1.8b, v2.8b
|
17
|
-
0x20,0x2c,0x22,0x4e = sqsub v0.16b, v1.16b, v2.16b
|
18
|
-
0x20,0x2c,0x62,0x0e = sqsub v0.4h, v1.4h, v2.4h
|
19
|
-
0x20,0x2c,0x62,0x4e = sqsub v0.8h, v1.8h, v2.8h
|
20
|
-
0x20,0x2c,0xa2,0x0e = sqsub v0.2s, v1.2s, v2.2s
|
21
|
-
0x20,0x2c,0xa2,0x4e = sqsub v0.4s, v1.4s, v2.4s
|
22
|
-
0x20,0x2c,0xe2,0x4e = sqsub v0.2d, v1.2d, v2.2d
|
23
|
-
0x20,0x2c,0x22,0x2e = uqsub v0.8b, v1.8b, v2.8b
|
24
|
-
0x20,0x2c,0x22,0x6e = uqsub v0.16b, v1.16b, v2.16b
|
25
|
-
0x20,0x2c,0x62,0x2e = uqsub v0.4h, v1.4h, v2.4h
|
26
|
-
0x20,0x2c,0x62,0x6e = uqsub v0.8h, v1.8h, v2.8h
|
27
|
-
0x20,0x2c,0xa2,0x2e = uqsub v0.2s, v1.2s, v2.2s
|
28
|
-
0x20,0x2c,0xa2,0x6e = uqsub v0.4s, v1.4s, v2.4s
|
29
|
-
0x20,0x2c,0xe2,0x6e = uqsub v0.2d, v1.2d, v2.2d
|
@@ -1,15 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x5c,0x22,0x0e = sqrshl v0.8b, v1.8b, v2.8b
|
3
|
-
0x20,0x5c,0x22,0x4e = sqrshl v0.16b, v1.16b, v2.16b
|
4
|
-
0x20,0x5c,0x62,0x0e = sqrshl v0.4h, v1.4h, v2.4h
|
5
|
-
0x20,0x5c,0x62,0x4e = sqrshl v0.8h, v1.8h, v2.8h
|
6
|
-
0x20,0x5c,0xa2,0x0e = sqrshl v0.2s, v1.2s, v2.2s
|
7
|
-
0x20,0x5c,0xa2,0x4e = sqrshl v0.4s, v1.4s, v2.4s
|
8
|
-
0x20,0x5c,0xe2,0x4e = sqrshl v0.2d, v1.2d, v2.2d
|
9
|
-
0x20,0x5c,0x22,0x2e = uqrshl v0.8b, v1.8b, v2.8b
|
10
|
-
0x20,0x5c,0x22,0x6e = uqrshl v0.16b, v1.16b, v2.16b
|
11
|
-
0x20,0x5c,0x62,0x2e = uqrshl v0.4h, v1.4h, v2.4h
|
12
|
-
0x20,0x5c,0x62,0x6e = uqrshl v0.8h, v1.8h, v2.8h
|
13
|
-
0x20,0x5c,0xa2,0x2e = uqrshl v0.2s, v1.2s, v2.2s
|
14
|
-
0x20,0x5c,0xa2,0x6e = uqrshl v0.4s, v1.4s, v2.4s
|
15
|
-
0x20,0x5c,0xe2,0x6e = uqrshl v0.2d, v1.2d, v2.2d
|
@@ -1,15 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x4c,0x22,0x0e = sqshl v0.8b, v1.8b, v2.8b
|
3
|
-
0x20,0x4c,0x22,0x4e = sqshl v0.16b, v1.16b, v2.16b
|
4
|
-
0x20,0x4c,0x62,0x0e = sqshl v0.4h, v1.4h, v2.4h
|
5
|
-
0x20,0x4c,0x62,0x4e = sqshl v0.8h, v1.8h, v2.8h
|
6
|
-
0x20,0x4c,0xa2,0x0e = sqshl v0.2s, v1.2s, v2.2s
|
7
|
-
0x20,0x4c,0xa2,0x4e = sqshl v0.4s, v1.4s, v2.4s
|
8
|
-
0x20,0x4c,0xe2,0x4e = sqshl v0.2d, v1.2d, v2.2d
|
9
|
-
0x20,0x4c,0x22,0x2e = uqshl v0.8b, v1.8b, v2.8b
|
10
|
-
0x20,0x4c,0x22,0x6e = uqshl v0.16b, v1.16b, v2.16b
|
11
|
-
0x20,0x4c,0x62,0x2e = uqshl v0.4h, v1.4h, v2.4h
|
12
|
-
0x20,0x4c,0x62,0x6e = uqshl v0.8h, v1.8h, v2.8h
|
13
|
-
0x20,0x4c,0xa2,0x2e = uqshl v0.2s, v1.2s, v2.2s
|
14
|
-
0x20,0x4c,0xa2,0x6e = uqshl v0.4s, v1.4s, v2.4s
|
15
|
-
0x20,0x4c,0xe2,0x6e = uqshl v0.2d, v1.2d, v2.2d
|
@@ -1,8 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x1d,0xbb,0xe0,0x5e = abs d29, d24
|
3
|
-
0x1d,0xd7,0xb4,0x7e = fabd s29, s24, s20
|
4
|
-
0x1d,0xd7,0xf4,0x7e = fabd d29, d24, d20
|
5
|
-
0xd3,0x79,0x20,0x5e = sqabs b19, b14
|
6
|
-
0xf5,0x79,0x60,0x5e = sqabs h21, h15
|
7
|
-
0x94,0x79,0xa0,0x5e = sqabs s20, s12
|
8
|
-
0x92,0x79,0xe0,0x5e = sqabs d18, d12
|
@@ -1,13 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x10,0x81,0x5f = fmla s0, s1, v1.s[0]
|
3
|
-
0x7e,0x11,0xa1,0x5f = fmla s30, s11, v1.s[1]
|
4
|
-
0xa4,0x18,0x87,0x5f = fmla s4, s5, v7.s[2]
|
5
|
-
0xd0,0x1a,0xb0,0x5f = fmla s16, s22, v16.s[3]
|
6
|
-
0x20,0x10,0xc1,0x5f = fmla d0, d1, v1.d[0]
|
7
|
-
0x7e,0x19,0xc1,0x5f = fmla d30, d11, v1.d[1]
|
8
|
-
0x62,0x50,0x84,0x5f = fmls s2, s3, v4.s[0]
|
9
|
-
0x5d,0x51,0xbc,0x5f = fmls s29, s10, v28.s[1]
|
10
|
-
0x85,0x59,0x97,0x5f = fmls s5, s12, v23.s[2]
|
11
|
-
0x27,0x5a,0xba,0x5f = fmls s7, s17, v26.s[3]
|
12
|
-
0x20,0x50,0xc1,0x5f = fmls d0, d1, v1.d[0]
|
13
|
-
0x7e,0x59,0xc1,0x5f = fmls d30, d11, v1.d[1]
|
@@ -1,13 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x90,0x81,0x5f = fmul s0, s1, v1.s[0]
|
3
|
-
0x7e,0x91,0xa1,0x5f = fmul s30, s11, v1.s[1]
|
4
|
-
0xa4,0x98,0x87,0x5f = fmul s4, s5, v7.s[2]
|
5
|
-
0xd0,0x9a,0xb0,0x5f = fmul s16, s22, v16.s[3]
|
6
|
-
0x20,0x90,0xc1,0x5f = fmul d0, d1, v1.d[0]
|
7
|
-
0x7e,0x99,0xc1,0x5f = fmul d30, d11, v1.d[1]
|
8
|
-
0x46,0x90,0x88,0x7f = fmulx s6, s2, v8.s[0]
|
9
|
-
0x67,0x90,0xad,0x7f = fmulx s7, s3, v13.s[1]
|
10
|
-
0xe9,0x98,0x89,0x7f = fmulx s9, s7, v9.s[2]
|
11
|
-
0xad,0x9a,0xaa,0x7f = fmulx s13, s21, v10.s[3]
|
12
|
-
0x2f,0x91,0xc7,0x7f = fmulx d15, d9, v7.d[0]
|
13
|
-
0x8d,0x99,0xcb,0x7f = fmulx d13, d12, v11.d[1]
|
@@ -1,15 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x00,0x30,0x40,0x5f = sqdmlal s0, h0, v0.h[0]
|
3
|
-
0x27,0x30,0x74,0x5f = sqdmlal s7, h1, v4.h[3]
|
4
|
-
0x0b,0x3a,0x48,0x5f = sqdmlal s11, h16, v8.h[4]
|
5
|
-
0xde,0x3b,0x7f,0x5f = sqdmlal s30, h30, v15.h[7]
|
6
|
-
0x00,0x30,0x83,0x5f = sqdmlal d0, s0, v3.s[0]
|
7
|
-
0xde,0x3b,0xbe,0x5f = sqdmlal d30, s30, v30.s[3]
|
8
|
-
0x28,0x31,0xae,0x5f = sqdmlal d8, s9, v14.s[1]
|
9
|
-
0x21,0x70,0x41,0x5f = sqdmlsl s1, h1, v1.h[0]
|
10
|
-
0x48,0x70,0x55,0x5f = sqdmlsl s8, h2, v5.h[1]
|
11
|
-
0xac,0x71,0x6e,0x5f = sqdmlsl s12, h13, v14.h[2]
|
12
|
-
0x9d,0x7b,0x7b,0x5f = sqdmlsl s29, h28, v11.h[7]
|
13
|
-
0x21,0x70,0x8d,0x5f = sqdmlsl d1, s1, v13.s[0]
|
14
|
-
0xff,0x7b,0x9f,0x5f = sqdmlsl d31, s31, v31.s[2]
|
15
|
-
0x50,0x7a,0xbc,0x5f = sqdmlsl d16, s18, v28.s[3]
|
@@ -1,18 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x21,0xb0,0x51,0x5f = sqdmull s1, h1, v1.h[1]
|
3
|
-
0x48,0xb0,0x65,0x5f = sqdmull s8, h2, v5.h[2]
|
4
|
-
0x2c,0xb2,0x79,0x5f = sqdmull s12, h17, v9.h[3]
|
5
|
-
0xff,0xbb,0x7f,0x5f = sqdmull s31, h31, v15.h[7]
|
6
|
-
0x21,0xb0,0x84,0x5f = sqdmull d1, s1, v4.s[0]
|
7
|
-
0xff,0xbb,0xbf,0x5f = sqdmull d31, s31, v31.s[3]
|
8
|
-
0x49,0xb1,0x8f,0x5f = sqdmull d9, s10, v15.s[0]
|
9
|
-
0x20,0xc0,0x40,0x5f = sqdmulh h0, h1, v0.h[0]
|
10
|
-
0x6a,0xc9,0x4a,0x5f = sqdmulh h10, h11, v10.h[4]
|
11
|
-
0xb4,0xca,0x7f,0x5f = sqdmulh h20, h21, v15.h[7]
|
12
|
-
0x59,0xcb,0xbb,0x5f = sqdmulh s25, s26, v27.s[3]
|
13
|
-
0xc2,0xc0,0x87,0x5f = sqdmulh s2, s6, v7.s[0]
|
14
|
-
0xdf,0xd3,0x6e,0x5f = sqrdmulh h31, h30, v14.h[2]
|
15
|
-
0x21,0xd8,0x41,0x5f = sqrdmulh h1, h1, v1.h[4]
|
16
|
-
0xd5,0xda,0x7f,0x5f = sqrdmulh h21, h22, v15.h[7]
|
17
|
-
0xc5,0xd8,0x87,0x5f = sqrdmulh s5, s6, v7.s[2]
|
18
|
-
0x54,0xd3,0xbb,0x5f = sqrdmulh s20, s26, v27.s[1]
|
@@ -1,12 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0xb4,0x8e,0xf6,0x7e = cmeq d20, d21, d22
|
3
|
-
0xb4,0x9a,0xe0,0x5e = cmeq d20, d21, #0x0
|
4
|
-
0xb4,0x3e,0xf6,0x7e = cmhs d20, d21, d22
|
5
|
-
0xb4,0x3e,0xf6,0x5e = cmge d20, d21, d22
|
6
|
-
0xb4,0x8a,0xe0,0x7e = cmge d20, d21, #0x0
|
7
|
-
0xb4,0x36,0xf6,0x7e = cmhi d20, d21, d22
|
8
|
-
0xb4,0x36,0xf6,0x5e = cmgt d20, d21, d22
|
9
|
-
0xb4,0x8a,0xe0,0x5e = cmgt d20, d21, #0x0
|
10
|
-
0xb4,0x9a,0xe0,0x7e = cmle d20, d21, #0x0
|
11
|
-
0xb4,0xaa,0xe0,0x5e = cmlt d20, d21, #0x0
|
12
|
-
0xb4,0x8e,0xf6,0x5e = cmtst d20, d21, d22
|
@@ -1,34 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0xb6,0xd9,0x21,0x5e = scvtf s22, s13
|
3
|
-
0x95,0xd9,0x61,0x5e = scvtf d21, d12
|
4
|
-
0xb6,0xd9,0x21,0x7e = ucvtf s22, s13
|
5
|
-
0xd5,0xd9,0x61,0x7e = ucvtf d21, d14
|
6
|
-
0xb6,0xe5,0x20,0x5f = scvtf s22, s13, #32
|
7
|
-
0x95,0xe5,0x40,0x5f = scvtf d21, d12, #64
|
8
|
-
0xb6,0xe5,0x20,0x7f = ucvtf s22, s13, #32
|
9
|
-
0xd5,0xe5,0x40,0x7f = ucvtf d21, d14, #64
|
10
|
-
0x95,0xfd,0x3f,0x5f = fcvtzs s21, s12, #1
|
11
|
-
0x95,0xfd,0x7f,0x5f = fcvtzs d21, d12, #1
|
12
|
-
0x95,0xfd,0x3f,0x7f = fcvtzu s21, s12, #1
|
13
|
-
0x95,0xfd,0x7f,0x7f = fcvtzu d21, d12, #1
|
14
|
-
0xb6,0x69,0x61,0x7e = fcvtxn s22, d13
|
15
|
-
0xac,0xc9,0x21,0x5e = fcvtas s12, s13
|
16
|
-
0xd5,0xc9,0x61,0x5e = fcvtas d21, d14
|
17
|
-
0xac,0xc9,0x21,0x7e = fcvtau s12, s13
|
18
|
-
0xd5,0xc9,0x61,0x7e = fcvtau d21, d14
|
19
|
-
0xb6,0xb9,0x21,0x5e = fcvtms s22, s13
|
20
|
-
0xd5,0xb9,0x61,0x5e = fcvtms d21, d14
|
21
|
-
0xac,0xb9,0x21,0x7e = fcvtmu s12, s13
|
22
|
-
0xd5,0xb9,0x61,0x7e = fcvtmu d21, d14
|
23
|
-
0xb6,0xa9,0x21,0x5e = fcvtns s22, s13
|
24
|
-
0xd5,0xa9,0x61,0x5e = fcvtns d21, d14
|
25
|
-
0xac,0xa9,0x21,0x7e = fcvtnu s12, s13
|
26
|
-
0xd5,0xa9,0x61,0x7e = fcvtnu d21, d14
|
27
|
-
0xb6,0xa9,0xa1,0x5e = fcvtps s22, s13
|
28
|
-
0xd5,0xa9,0xe1,0x5e = fcvtps d21, d14
|
29
|
-
0xac,0xa9,0xa1,0x7e = fcvtpu s12, s13
|
30
|
-
0xd5,0xa9,0xe1,0x7e = fcvtpu d21, d14
|
31
|
-
0xac,0xb9,0xa1,0x5e = fcvtzs s12, s13
|
32
|
-
0xd5,0xb9,0xe1,0x5e = fcvtzs d21, d14
|
33
|
-
0xac,0xb9,0xa1,0x7e = fcvtzu s12, s13
|
34
|
-
0xd5,0xb9,0xe1,0x7e = fcvtzu d21, d14
|
@@ -1,23 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x00,0x04,0x1f,0x5e = dup b0, v0.b[15]
|
3
|
-
0x01,0x04,0x0f,0x5e = dup b1, v0.b[7]
|
4
|
-
0x11,0x04,0x01,0x5e = dup b17, v0.b[0]
|
5
|
-
0xe5,0x07,0x1e,0x5e = dup h5, v31.h[7]
|
6
|
-
0x29,0x04,0x12,0x5e = dup h9, v1.h[4]
|
7
|
-
0x2b,0x06,0x02,0x5e = dup h11, v17.h[0]
|
8
|
-
0x42,0x04,0x1c,0x5e = dup s2, v2.s[3]
|
9
|
-
0xa4,0x06,0x04,0x5e = dup s4, v21.s[0]
|
10
|
-
0xbf,0x06,0x14,0x5e = dup s31, v21.s[2]
|
11
|
-
0xa3,0x04,0x08,0x5e = dup d3, v5.d[0]
|
12
|
-
0xa6,0x04,0x18,0x5e = dup d6, v5.d[1]
|
13
|
-
0x00,0x04,0x1f,0x5e = dup b0, v0.b[15]
|
14
|
-
0x01,0x04,0x0f,0x5e = dup b1, v0.b[7]
|
15
|
-
0x11,0x04,0x01,0x5e = dup b17, v0.b[0]
|
16
|
-
0xe5,0x07,0x1e,0x5e = dup h5, v31.h[7]
|
17
|
-
0x29,0x04,0x12,0x5e = dup h9, v1.h[4]
|
18
|
-
0x2b,0x06,0x02,0x5e = dup h11, v17.h[0]
|
19
|
-
0x42,0x04,0x1c,0x5e = dup s2, v2.s[3]
|
20
|
-
0xa4,0x06,0x04,0x5e = dup s4, v21.s[0]
|
21
|
-
0xbf,0x06,0x14,0x5e = dup s31, v21.s[2]
|
22
|
-
0xa3,0x04,0x08,0x5e = dup d3, v5.d[0]
|
23
|
-
0xa6,0x04,0x18,0x5e = dup d6, v5.d[1]
|
@@ -1,10 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0xd3,0x29,0x21,0x7e = sqxtun b19, h14
|
3
|
-
0xf5,0x29,0x61,0x7e = sqxtun h21, s15
|
4
|
-
0x94,0x29,0xa1,0x7e = sqxtun s20, d12
|
5
|
-
0x52,0x4a,0x21,0x5e = sqxtn b18, h18
|
6
|
-
0x34,0x4a,0x61,0x5e = sqxtn h20, s17
|
7
|
-
0xd3,0x49,0xa1,0x5e = sqxtn s19, d14
|
8
|
-
0x52,0x4a,0x21,0x7e = uqxtn b18, h18
|
9
|
-
0x34,0x4a,0x61,0x7e = uqxtn h20, s17
|
10
|
-
0xd3,0x49,0xa1,0x7e = uqxtn s19, d14
|
@@ -1,21 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x6a,0xe5,0x2c,0x5e = fcmeq s10, s11, s12
|
3
|
-
0xb4,0xe6,0x76,0x5e = fcmeq d20, d21, d22
|
4
|
-
0x6a,0xd9,0xa0,0x5e = fcmeq s10, s11, #0.0
|
5
|
-
0xb4,0xda,0xe0,0x5e = fcmeq d20, d21, #0.0
|
6
|
-
0x6a,0xe5,0x2c,0x7e = fcmge s10, s11, s12
|
7
|
-
0xb4,0xe6,0x76,0x7e = fcmge d20, d21, d22
|
8
|
-
0x6a,0xc9,0xa0,0x7e = fcmge s10, s11, #0.0
|
9
|
-
0xb4,0xca,0xe0,0x7e = fcmge d20, d21, #0.0
|
10
|
-
0x6a,0xe5,0xac,0x7e = fcmgt s10, s11, s12
|
11
|
-
0xb4,0xe6,0xf6,0x7e = fcmgt d20, d21, d22
|
12
|
-
0x6a,0xc9,0xa0,0x5e = fcmgt s10, s11, #0.0
|
13
|
-
0xb4,0xca,0xe0,0x5e = fcmgt d20, d21, #0.0
|
14
|
-
0x6a,0xd9,0xa0,0x7e = fcmle s10, s11, #0.0
|
15
|
-
0xb4,0xda,0xe0,0x7e = fcmle d20, d21, #0.0
|
16
|
-
0x6a,0xe9,0xa0,0x5e = fcmlt s10, s11, #0.0
|
17
|
-
0xb4,0xea,0xe0,0x5e = fcmlt d20, d21, #0.0
|
18
|
-
0x6a,0xed,0x2c,0x7e = facge s10, s11, s12
|
19
|
-
0xb4,0xee,0x76,0x7e = facge d20, d21, d22
|
20
|
-
0x6a,0xed,0xac,0x7e = facgt s10, s11, s12
|
21
|
-
0xb4,0xee,0xf6,0x7e = facgt d20, d21, d22
|
@@ -1,13 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x6a,0xb5,0x6c,0x5e = sqdmulh h10, h11, h12
|
3
|
-
0xb4,0xb6,0xa2,0x5e = sqdmulh s20, s21, s2
|
4
|
-
0x6a,0xb5,0x6c,0x7e = sqrdmulh h10, h11, h12
|
5
|
-
0xb4,0xb6,0xa2,0x7e = sqrdmulh s20, s21, s2
|
6
|
-
0xd4,0xde,0x2f,0x5e = fmulx s20, s22, s15
|
7
|
-
0x77,0xdd,0x61,0x5e = fmulx d23, d11, d1
|
8
|
-
0x71,0x93,0x6c,0x5e = sqdmlal s17, h27, h12
|
9
|
-
0x13,0x93,0xac,0x5e = sqdmlal d19, s24, s12
|
10
|
-
0x8e,0xb1,0x79,0x5e = sqdmlsl s14, h12, h25
|
11
|
-
0xec,0xb2,0xad,0x5e = sqdmlsl d12, s23, s13
|
12
|
-
0xcc,0xd2,0x6c,0x5e = sqdmull s12, h22, h12
|
13
|
-
0xcf,0xd2,0xac,0x5e = sqdmull d15, s22, s12
|
@@ -1,11 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x15,0xfe,0x2d,0x5e = frecps s21, s16, s13
|
3
|
-
0xd6,0xff,0x75,0x5e = frecps d22, d30, d21
|
4
|
-
0xb5,0xfc,0xac,0x5e = frsqrts s21, s5, s12
|
5
|
-
0xc8,0xfe,0xf2,0x5e = frsqrts d8, d22, d18
|
6
|
-
0xd3,0xd9,0xa1,0x5e = frecpe s19, s14
|
7
|
-
0xad,0xd9,0xe1,0x5e = frecpe d13, d13
|
8
|
-
0x52,0xf9,0xa1,0x5e = frecpx s18, s10
|
9
|
-
0x70,0xfa,0xe1,0x5e = frecpx d16, d19
|
10
|
-
0xb6,0xd9,0xa1,0x7e = frsqrte s22, s13
|
11
|
-
0x95,0xd9,0xe1,0x7e = frsqrte d21, d12
|
@@ -1,25 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x0c,0x22,0x5e = sqadd b0, b1, b2
|
3
|
-
0x6a,0x0d,0x6c,0x5e = sqadd h10, h11, h12
|
4
|
-
0xb4,0x0e,0xa2,0x5e = sqadd s20, s21, s2
|
5
|
-
0xf1,0x0f,0xe8,0x5e = sqadd d17, d31, d8
|
6
|
-
0x20,0x0c,0x22,0x7e = uqadd b0, b1, b2
|
7
|
-
0x6a,0x0d,0x6c,0x7e = uqadd h10, h11, h12
|
8
|
-
0xb4,0x0e,0xa2,0x7e = uqadd s20, s21, s2
|
9
|
-
0xf1,0x0f,0xe8,0x7e = uqadd d17, d31, d8
|
10
|
-
0x20,0x2c,0x22,0x5e = sqsub b0, b1, b2
|
11
|
-
0x6a,0x2d,0x6c,0x5e = sqsub h10, h11, h12
|
12
|
-
0xb4,0x2e,0xa2,0x5e = sqsub s20, s21, s2
|
13
|
-
0xf1,0x2f,0xe8,0x5e = sqsub d17, d31, d8
|
14
|
-
0x20,0x2c,0x22,0x7e = uqsub b0, b1, b2
|
15
|
-
0x6a,0x2d,0x6c,0x7e = uqsub h10, h11, h12
|
16
|
-
0xb4,0x2e,0xa2,0x7e = uqsub s20, s21, s2
|
17
|
-
0xf1,0x2f,0xe8,0x7e = uqsub d17, d31, d8
|
18
|
-
0xd3,0x39,0x20,0x5e = suqadd b19, b14
|
19
|
-
0xf4,0x39,0x60,0x5e = suqadd h20, h15
|
20
|
-
0x95,0x39,0xa0,0x5e = suqadd s21, s12
|
21
|
-
0xd2,0x3a,0xe0,0x5e = suqadd d18, d22
|
22
|
-
0xd3,0x39,0x20,0x7e = usqadd b19, b14
|
23
|
-
0xf4,0x39,0x60,0x7e = usqadd h20, h15
|
24
|
-
0x95,0x39,0xa0,0x7e = usqadd s21, s12
|
25
|
-
0xd2,0x3a,0xe0,0x7e = usqadd d18, d22
|
@@ -1,9 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x5c,0x22,0x5e = sqrshl b0, b1, b2
|
3
|
-
0x6a,0x5d,0x6c,0x5e = sqrshl h10, h11, h12
|
4
|
-
0xb4,0x5e,0xa2,0x5e = sqrshl s20, s21, s2
|
5
|
-
0xf1,0x5f,0xe8,0x5e = sqrshl d17, d31, d8
|
6
|
-
0x20,0x5c,0x22,0x7e = uqrshl b0, b1, b2
|
7
|
-
0x6a,0x5d,0x6c,0x7e = uqrshl h10, h11, h12
|
8
|
-
0xb4,0x5e,0xa2,0x7e = uqrshl s20, s21, s2
|
9
|
-
0xf1,0x5f,0xe8,0x7e = uqrshl d17, d31, d8
|
@@ -1,9 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x20,0x4c,0x22,0x5e = sqshl b0, b1, b2
|
3
|
-
0x6a,0x4d,0x6c,0x5e = sqshl h10, h11, h12
|
4
|
-
0xb4,0x4e,0xa2,0x5e = sqshl s20, s21, s2
|
5
|
-
0xf1,0x4f,0xe8,0x5e = sqshl d17, d31, d8
|
6
|
-
0x20,0x4c,0x22,0x7e = uqshl b0, b1, b2
|
7
|
-
0x6a,0x4d,0x6c,0x7e = uqshl h10, h11, h12
|
8
|
-
0xb4,0x4e,0xa2,0x7e = uqshl s20, s21, s2
|
9
|
-
0xf1,0x4f,0xe8,0x7e = uqshl d17, d31, d8
|
@@ -1,42 +0,0 @@
|
|
1
|
-
# CS_ARCH_ARM64, 0, None
|
2
|
-
0x0f,0x06,0x74,0x5f = sshr d15, d16, #12
|
3
|
-
0x2a,0x06,0x6e,0x7f = ushr d10, d17, #18
|
4
|
-
0x53,0x26,0x79,0x5f = srshr d19, d18, #7
|
5
|
-
0xf4,0x26,0x61,0x7f = urshr d20, d23, #31
|
6
|
-
0x92,0x15,0x6b,0x5f = ssra d18, d12, #21
|
7
|
-
0xb4,0x15,0x43,0x7f = usra d20, d13, #61
|
8
|
-
0x6f,0x35,0x6d,0x5f = srsra d15, d11, #19
|
9
|
-
0x52,0x35,0x73,0x7f = ursra d18, d10, #13
|
10
|
-
0x47,0x55,0x4c,0x5f = shl d7, d10, #12
|
11
|
-
0x6b,0x76,0x0f,0x5f = sqshl b11, b19, #7
|
12
|
-
0x4d,0x76,0x1b,0x5f = sqshl h13, h18, #11
|
13
|
-
0x2e,0x76,0x36,0x5f = sqshl s14, s17, #22
|
14
|
-
0x0f,0x76,0x73,0x5f = sqshl d15, d16, #51
|
15
|
-
0xf2,0x75,0x0e,0x7f = uqshl b18, b15, #6
|
16
|
-
0x4b,0x76,0x17,0x7f = uqshl h11, h18, #7
|
17
|
-
0x6e,0x76,0x32,0x7f = uqshl s14, s19, #18
|
18
|
-
0x8f,0x75,0x53,0x7f = uqshl d15, d12, #19
|
19
|
-
0x4f,0x66,0x0e,0x7f = sqshlu b15, b18, #6
|
20
|
-
0x33,0x66,0x16,0x7f = sqshlu h19, h17, #6
|
21
|
-
0xd0,0x65,0x39,0x7f = sqshlu s16, s14, #25
|
22
|
-
0xab,0x65,0x60,0x7f = sqshlu d11, d13, #32
|
23
|
-
0x8a,0x45,0x72,0x7f = sri d10, d12, #14
|
24
|
-
0xca,0x55,0x4c,0x7f = sli d10, d14, #12
|
25
|
-
0xea,0x95,0x0b,0x5f = sqshrn b10, h15, #5
|
26
|
-
0x51,0x95,0x1c,0x5f = sqshrn h17, s10, #4
|
27
|
-
0x52,0x95,0x21,0x5f = sqshrn s18, d10, #31
|
28
|
-
0x4c,0x95,0x09,0x7f = uqshrn b12, h10, #7
|
29
|
-
0xca,0x95,0x1b,0x7f = uqshrn h10, s14, #5
|
30
|
-
0x8a,0x95,0x33,0x7f = uqshrn s10, d12, #13
|
31
|
-
0xaa,0x9d,0x0e,0x5f = sqrshrn b10, h13, #2
|
32
|
-
0x4f,0x9d,0x1a,0x5f = sqrshrn h15, s10, #6
|
33
|
-
0x8f,0x9d,0x37,0x5f = sqrshrn s15, d12, #9
|
34
|
-
0x8a,0x9d,0x0b,0x7f = uqrshrn b10, h12, #5
|
35
|
-
0x4c,0x9d,0x12,0x7f = uqrshrn h12, s10, #14
|
36
|
-
0x4a,0x9d,0x27,0x7f = uqrshrn s10, d10, #25
|
37
|
-
0x4f,0x85,0x09,0x7f = sqshrun b15, h10, #7
|
38
|
-
0xd4,0x85,0x1d,0x7f = sqshrun h20, s14, #3
|
39
|
-
0xea,0x85,0x31,0x7f = sqshrun s10, d15, #15
|
40
|
-
0x51,0x8d,0x0a,0x7f = sqrshrun b17, h10, #6
|
41
|
-
0xaa,0x8d,0x11,0x7f = sqrshrun h10, s13, #15
|
42
|
-
0x16,0x8e,0x21,0x7f = sqrshrun s22, d16, #31
|