crabstone 3.0.3 → 4.0.0
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- checksums.yaml +5 -5
- data/CHANGES.md +45 -42
- data/README.md +16 -33
- data/lib/crabstone.rb +5 -557
- data/lib/crabstone/arch.rb +37 -0
- data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
- data/lib/crabstone/arch/3/arm64.rb +124 -0
- data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
- data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
- data/lib/crabstone/arch/3/mips.rb +57 -0
- data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
- data/lib/crabstone/arch/3/ppc.rb +73 -0
- data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
- data/lib/crabstone/arch/3/sparc.rb +60 -0
- data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
- data/lib/crabstone/arch/3/sysz.rb +67 -0
- data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
- data/lib/crabstone/arch/3/x86.rb +82 -0
- data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
- data/lib/crabstone/arch/3/xcore.rb +59 -0
- data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
- data/lib/crabstone/arch/4/arm.rb +110 -0
- data/lib/crabstone/arch/4/arm64.rb +125 -0
- data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
- data/lib/crabstone/arch/4/arm_const.rb +785 -0
- data/lib/crabstone/arch/4/evm.rb +20 -0
- data/lib/crabstone/arch/4/evm_const.rb +161 -0
- data/lib/crabstone/arch/4/m680x.rb +106 -0
- data/lib/crabstone/arch/4/m680x_const.rb +426 -0
- data/lib/crabstone/arch/4/m68k.rb +129 -0
- data/lib/crabstone/arch/4/m68k_const.rb +496 -0
- data/lib/crabstone/arch/4/mips.rb +57 -0
- data/lib/crabstone/arch/4/mips_const.rb +869 -0
- data/lib/crabstone/arch/4/ppc.rb +73 -0
- data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
- data/lib/crabstone/arch/4/sparc.rb +60 -0
- data/lib/crabstone/arch/4/sparc_const.rb +439 -0
- data/lib/crabstone/arch/4/sysz.rb +67 -0
- data/lib/crabstone/arch/4/sysz_const.rb +763 -0
- data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
- data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
- data/lib/crabstone/arch/4/x86.rb +91 -0
- data/lib/crabstone/arch/4/x86_const.rb +1972 -0
- data/lib/crabstone/arch/4/xcore.rb +59 -0
- data/lib/crabstone/arch/4/xcore_const.rb +171 -0
- data/lib/crabstone/arch/extension.rb +27 -0
- data/lib/crabstone/arch/register.rb +36 -0
- data/lib/crabstone/binding.rb +60 -0
- data/lib/crabstone/binding/3/detail.rb +36 -0
- data/lib/crabstone/binding/3/instruction.rb +23 -0
- data/lib/crabstone/binding/4/detail.rb +40 -0
- data/lib/crabstone/binding/4/instruction.rb +23 -0
- data/lib/crabstone/binding/structs.rb +32 -0
- data/lib/crabstone/constants.rb +110 -0
- data/lib/crabstone/cs_version.rb +49 -0
- data/lib/crabstone/disassembler.rb +153 -0
- data/lib/crabstone/error.rb +60 -0
- data/lib/crabstone/instruction.rb +183 -0
- data/lib/crabstone/version.rb +5 -0
- metadata +128 -324
- data/MANIFEST +0 -312
- data/Rakefile +0 -27
- data/bin/genconst +0 -66
- data/bin/genreg +0 -99
- data/crabstone.gemspec +0 -27
- data/examples/hello_world.rb +0 -43
- data/lib/arch/arm64.rb +0 -167
- data/lib/arch/arm64_registers.rb +0 -295
- data/lib/arch/arm_registers.rb +0 -149
- data/lib/arch/mips.rb +0 -78
- data/lib/arch/mips_registers.rb +0 -208
- data/lib/arch/ppc.rb +0 -90
- data/lib/arch/ppc_registers.rb +0 -209
- data/lib/arch/sparc.rb +0 -79
- data/lib/arch/sparc_registers.rb +0 -121
- data/lib/arch/systemz.rb +0 -79
- data/lib/arch/sysz_registers.rb +0 -66
- data/lib/arch/x86.rb +0 -107
- data/lib/arch/x86_registers.rb +0 -265
- data/lib/arch/xcore.rb +0 -78
- data/lib/arch/xcore_registers.rb +0 -57
- data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
- data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
- data/test/MC/AArch64/neon-2velem.s.cs +0 -113
- data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
- data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
- data/test/MC/AArch64/neon-across.s.cs +0 -40
- data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
- data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
- data/test/MC/AArch64/neon-crypto.s.cs +0 -15
- data/test/MC/AArch64/neon-extract.s.cs +0 -3
- data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
- data/test/MC/AArch64/neon-max-min.s.cs +0 -37
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
- data/test/MC/AArch64/neon-mov.s.cs +0 -74
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
- data/test/MC/AArch64/neon-perm.s.cs +0 -43
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
- data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
- data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
- data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
- data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
- data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
- data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
- data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
- data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
- data/test/MC/AArch64/neon-shift.s.cs +0 -22
- data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
- data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
- data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
- data/test/MC/AArch64/neon-tbl.s.cs +0 -21
- data/test/MC/AArch64/trace-regs.s.cs +0 -383
- data/test/MC/ARM/arm-aliases.s.cs +0 -7
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
- data/test/MC/ARM/arm-it-block.s.cs +0 -2
- data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
- data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm-trustzone.s.cs +0 -3
- data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
- data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
- data/test/MC/ARM/arm_instructions.s.cs +0 -25
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
- data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
- data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
- data/test/MC/ARM/crc32-thumb.s.cs +0 -7
- data/test/MC/ARM/crc32.s.cs +0 -7
- data/test/MC/ARM/dot-req.s.cs +0 -3
- data/test/MC/ARM/fp-armv8.s.cs +0 -52
- data/test/MC/ARM/idiv-thumb.s.cs +0 -3
- data/test/MC/ARM/idiv.s.cs +0 -3
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
- data/test/MC/ARM/mode-switch.s.cs +0 -7
- data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
- data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
- data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
- data/test/MC/ARM/neon-crypto.s.cs +0 -16
- data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
- data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
- data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
- data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
- data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neon-v8.s.cs +0 -38
- data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
- data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
- data/test/MC/ARM/neon-vswp.s.cs +0 -3
- data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
- data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
- data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
- data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
- data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
- data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
- data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
- data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
- data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
- data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
- data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
- data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
- data/test/MC/ARM/thumb-hints.s.cs +0 -12
- data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
- data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
- data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
- data/test/MC/ARM/thumb.s.cs +0 -19
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
- data/test/MC/ARM/thumb2-branches.s.cs +0 -85
- data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
- data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
- data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
- data/test/MC/ARM/vfp4.s.cs +0 -13
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
- data/test/MC/ARM/vpush-vpop.s.cs +0 -9
- data/test/MC/Mips/hilo-addressing.s.cs +0 -4
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
- data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
- data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
- data/test/MC/Mips/micromips-expansions.s.cs +0 -20
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
- data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
- data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
- data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
- data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
- data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
- data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
- data/test/MC/Mips/mips-expansions.s.cs +0 -20
- data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
- data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
- data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
- data/test/MC/Mips/mips-register-names.s.cs +0 -33
- data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
- data/test/MC/Mips/mips64-instructions.s.cs +0 -3
- data/test/MC/Mips/mips64-register-names.s.cs +0 -33
- data/test/MC/Mips/mips_directives.s.cs +0 -12
- data/test/MC/Mips/nabi-regs.s.cs +0 -12
- data/test/MC/Mips/set-at-directive.s.cs +0 -6
- data/test/MC/Mips/test_2r.s.cs +0 -16
- data/test/MC/Mips/test_2rf.s.cs +0 -33
- data/test/MC/Mips/test_3r.s.cs +0 -243
- data/test/MC/Mips/test_3rf.s.cs +0 -83
- data/test/MC/Mips/test_bit.s.cs +0 -49
- data/test/MC/Mips/test_cbranch.s.cs +0 -11
- data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
- data/test/MC/Mips/test_elm.s.cs +0 -16
- data/test/MC/Mips/test_elm_insert.s.cs +0 -4
- data/test/MC/Mips/test_elm_insve.s.cs +0 -5
- data/test/MC/Mips/test_i10.s.cs +0 -5
- data/test/MC/Mips/test_i5.s.cs +0 -45
- data/test/MC/Mips/test_i8.s.cs +0 -11
- data/test/MC/Mips/test_lsa.s.cs +0 -5
- data/test/MC/Mips/test_mi10.s.cs +0 -24
- data/test/MC/Mips/test_vec.s.cs +0 -8
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
- data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
- data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
- data/test/MC/README +0 -6
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
- data/test/MC/Sparc/sparc-vis.s.cs +0 -2
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
- data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
- data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
- data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
- data/test/MC/SystemZ/insn-good.s.cs +0 -2265
- data/test/MC/SystemZ/regs-good.s.cs +0 -45
- data/test/MC/X86/3DNow.s.cs +0 -29
- data/test/MC/X86/address-size.s.cs +0 -5
- data/test/MC/X86/avx512-encodings.s.cs +0 -12
- data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
- data/test/MC/X86/x86-32-avx.s.cs +0 -833
- data/test/MC/X86/x86-32-fma3.s.cs +0 -169
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
- data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
- data/test/MC/X86/x86_64-encoding.s.cs +0 -59
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
- data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
- data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
- data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
- data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
- data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
- data/test/README +0 -6
- data/test/test.rb +0 -205
- data/test/test.rb.SPEC +0 -235
- data/test/test_arm.rb +0 -202
- data/test/test_arm.rb.SPEC +0 -275
- data/test/test_arm64.rb +0 -150
- data/test/test_arm64.rb.SPEC +0 -116
- data/test/test_detail.rb +0 -228
- data/test/test_detail.rb.SPEC +0 -322
- data/test/test_exhaustive.rb +0 -80
- data/test/test_mips.rb +0 -118
- data/test/test_mips.rb.SPEC +0 -91
- data/test/test_ppc.rb +0 -137
- data/test/test_ppc.rb.SPEC +0 -84
- data/test/test_sanity.rb +0 -83
- data/test/test_skipdata.rb +0 -111
- data/test/test_skipdata.rb.SPEC +0 -58
- data/test/test_sparc.rb +0 -113
- data/test/test_sparc.rb.SPEC +0 -116
- data/test/test_sysz.rb +0 -111
- data/test/test_sysz.rb.SPEC +0 -61
- data/test/test_x86.rb +0 -189
- data/test/test_x86.rb.SPEC +0 -579
- data/test/test_xcore.rb +0 -100
- data/test/test_xcore.rb.SPEC +0 -75
@@ -0,0 +1,60 @@
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# frozen_string_literal: true
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# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
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require 'ffi'
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require 'crabstone/arch/extension'
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require_relative 'sparc_const'
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module Crabstone
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module Sparc
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class OperandMemory < FFI::Struct
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layout(
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:base, :uint8,
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:index, :uint8,
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:disp, :int
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)
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end
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class OperandValue < FFI::Union
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layout(
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:reg, :uint,
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:imm, :long,
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:mem, OperandMemory
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)
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end
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class Operand < FFI::Struct
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layout(
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:type, :uint,
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:value, OperandValue
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)
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include Crabstone::Extension::Operand
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def reg?
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self[:type] == OP_REG
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end
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def imm?
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self[:type] == OP_IMM
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end
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def mem?
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self[:type] == OP_MEM
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end
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end
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class Instruction < FFI::Struct
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layout(
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:cc, :uint,
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:hint, :uint,
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:op_count, :uint8,
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:operands, [Operand, 4]
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)
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include Crabstone::Extension::Instruction
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end
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end
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end
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# frozen_string_literal: true
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# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
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require 'crabstone/arch/register'
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module Crabstone
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module Sparc
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CC_INVALID = 0
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CC_ICC_A = 8 + 256
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CC_ICC_N = 0 + 256
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CC_ICC_NE = 9 + 256
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CC_ICC_E = 1 + 256
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CC_ICC_G = 10 + 256
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CC_ICC_LE = 2 + 256
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CC_ICC_GE = 11 + 256
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CC_ICC_L = 3 + 256
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CC_ICC_GU = 12 + 256
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CC_ICC_LEU = 4 + 256
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CC_ICC_CC = 13 + 256
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CC_ICC_CS = 5 + 256
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CC_ICC_POS = 14 + 256
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CC_ICC_NEG = 6 + 256
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CC_ICC_VC = 15 + 256
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CC_ICC_VS = 7 + 256
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CC_FCC_A = 8 + 16 + 256
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CC_FCC_N = 0 + 16 + 256
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CC_FCC_U = 7 + 16 + 256
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CC_FCC_G = 6 + 16 + 256
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CC_FCC_UG = 5 + 16 + 256
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CC_FCC_L = 4 + 16 + 256
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CC_FCC_UL = 3 + 16 + 256
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CC_FCC_LG = 2 + 16 + 256
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CC_FCC_NE = 1 + 16 + 256
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CC_FCC_E = 9 + 16 + 256
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CC_FCC_UE = 10 + 16 + 256
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CC_FCC_GE = 11 + 16 + 256
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CC_FCC_UGE = 12 + 16 + 256
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CC_FCC_LE = 13 + 16 + 256
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CC_FCC_ULE = 14 + 16 + 256
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CC_FCC_O = 15 + 16 + 256
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+
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HINT_INVALID = 0
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HINT_A = 1 << 0
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HINT_PT = 1 << 1
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HINT_PN = 1 << 2
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OP_INVALID = 0
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OP_REG = 1
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OP_IMM = 2
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OP_MEM = 3
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+
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REG_INVALID = 0
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REG_F0 = 1
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REG_F1 = 2
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REG_F2 = 3
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REG_F3 = 4
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REG_F4 = 5
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REG_F5 = 6
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REG_F6 = 7
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REG_F7 = 8
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REG_F8 = 9
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REG_F9 = 10
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REG_F10 = 11
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REG_F11 = 12
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REG_F12 = 13
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REG_F13 = 14
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REG_F14 = 15
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REG_F15 = 16
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REG_F16 = 17
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REG_F17 = 18
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REG_F18 = 19
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REG_F19 = 20
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REG_F20 = 21
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REG_F21 = 22
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REG_F22 = 23
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REG_F23 = 24
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REG_F24 = 25
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REG_F25 = 26
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REG_F26 = 27
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REG_F27 = 28
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REG_F28 = 29
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REG_F29 = 30
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REG_F30 = 31
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REG_F31 = 32
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REG_F32 = 33
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REG_F34 = 34
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REG_F36 = 35
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REG_F38 = 36
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REG_F40 = 37
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REG_F42 = 38
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REG_F44 = 39
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REG_F46 = 40
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REG_F48 = 41
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REG_F50 = 42
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REG_F52 = 43
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REG_F54 = 44
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REG_F56 = 45
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REG_F58 = 46
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REG_F60 = 47
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101
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REG_F62 = 48
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REG_FCC0 = 49
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REG_FCC1 = 50
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REG_FCC2 = 51
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REG_FCC3 = 52
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REG_FP = 53
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REG_G0 = 54
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REG_G1 = 55
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REG_G2 = 56
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REG_G3 = 57
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111
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REG_G4 = 58
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REG_G5 = 59
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REG_G6 = 60
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114
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REG_G7 = 61
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115
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REG_I0 = 62
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116
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REG_I1 = 63
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REG_I2 = 64
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118
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REG_I3 = 65
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REG_I4 = 66
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120
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REG_I5 = 67
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121
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REG_I7 = 68
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122
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REG_ICC = 69
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123
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REG_L0 = 70
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REG_L1 = 71
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125
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REG_L2 = 72
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126
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REG_L3 = 73
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127
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REG_L4 = 74
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128
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REG_L5 = 75
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129
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REG_L6 = 76
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REG_L7 = 77
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REG_O0 = 78
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REG_O1 = 79
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REG_O2 = 80
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REG_O3 = 81
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REG_O4 = 82
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REG_O5 = 83
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REG_O7 = 84
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REG_SP = 85
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REG_Y = 86
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REG_XCC = 87
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141
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REG_ENDING = 88
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REG_O6 = REG_SP
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REG_I6 = REG_FP
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144
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INS_INVALID = 0
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INS_ADDCC = 1
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147
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INS_ADDX = 2
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INS_ADDXCC = 3
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INS_ADDXC = 4
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INS_ADDXCCC = 5
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INS_ADD = 6
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INS_ALIGNADDR = 7
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INS_ALIGNADDRL = 8
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INS_ANDCC = 9
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INS_ANDNCC = 10
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INS_ANDN = 11
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INS_AND = 12
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INS_ARRAY16 = 13
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INS_ARRAY32 = 14
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160
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INS_ARRAY8 = 15
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INS_B = 16
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162
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INS_JMP = 17
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INS_BMASK = 18
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164
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INS_FB = 19
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INS_BRGEZ = 20
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INS_BRGZ = 21
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INS_BRLEZ = 22
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INS_BRLZ = 23
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INS_BRNZ = 24
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INS_BRZ = 25
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INS_BSHUFFLE = 26
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INS_CALL = 27
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INS_CASX = 28
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INS_CAS = 29
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INS_CMASK16 = 30
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INS_CMASK32 = 31
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INS_CMASK8 = 32
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INS_CMP = 33
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INS_EDGE16 = 34
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INS_EDGE16L = 35
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INS_EDGE16LN = 36
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INS_EDGE16N = 37
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INS_EDGE32 = 38
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INS_EDGE32L = 39
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INS_EDGE32LN = 40
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INS_EDGE32N = 41
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INS_EDGE8 = 42
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INS_EDGE8L = 43
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INS_EDGE8LN = 44
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INS_EDGE8N = 45
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INS_FABSD = 46
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INS_FABSQ = 47
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INS_FABSS = 48
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INS_FADDD = 49
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INS_FADDQ = 50
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INS_FADDS = 51
|
197
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+
INS_FALIGNDATA = 52
|
198
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INS_FAND = 53
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+
INS_FANDNOT1 = 54
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200
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INS_FANDNOT1S = 55
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201
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+
INS_FANDNOT2 = 56
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202
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INS_FANDNOT2S = 57
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203
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+
INS_FANDS = 58
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204
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INS_FCHKSM16 = 59
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205
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+
INS_FCMPD = 60
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206
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+
INS_FCMPEQ16 = 61
|
207
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+
INS_FCMPEQ32 = 62
|
208
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+
INS_FCMPGT16 = 63
|
209
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+
INS_FCMPGT32 = 64
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210
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+
INS_FCMPLE16 = 65
|
211
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+
INS_FCMPLE32 = 66
|
212
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+
INS_FCMPNE16 = 67
|
213
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+
INS_FCMPNE32 = 68
|
214
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+
INS_FCMPQ = 69
|
215
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+
INS_FCMPS = 70
|
216
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+
INS_FDIVD = 71
|
217
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+
INS_FDIVQ = 72
|
218
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+
INS_FDIVS = 73
|
219
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+
INS_FDMULQ = 74
|
220
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+
INS_FDTOI = 75
|
221
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+
INS_FDTOQ = 76
|
222
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+
INS_FDTOS = 77
|
223
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+
INS_FDTOX = 78
|
224
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+
INS_FEXPAND = 79
|
225
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+
INS_FHADDD = 80
|
226
|
+
INS_FHADDS = 81
|
227
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+
INS_FHSUBD = 82
|
228
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+
INS_FHSUBS = 83
|
229
|
+
INS_FITOD = 84
|
230
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+
INS_FITOQ = 85
|
231
|
+
INS_FITOS = 86
|
232
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+
INS_FLCMPD = 87
|
233
|
+
INS_FLCMPS = 88
|
234
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+
INS_FLUSHW = 89
|
235
|
+
INS_FMEAN16 = 90
|
236
|
+
INS_FMOVD = 91
|
237
|
+
INS_FMOVQ = 92
|
238
|
+
INS_FMOVRDGEZ = 93
|
239
|
+
INS_FMOVRQGEZ = 94
|
240
|
+
INS_FMOVRSGEZ = 95
|
241
|
+
INS_FMOVRDGZ = 96
|
242
|
+
INS_FMOVRQGZ = 97
|
243
|
+
INS_FMOVRSGZ = 98
|
244
|
+
INS_FMOVRDLEZ = 99
|
245
|
+
INS_FMOVRQLEZ = 100
|
246
|
+
INS_FMOVRSLEZ = 101
|
247
|
+
INS_FMOVRDLZ = 102
|
248
|
+
INS_FMOVRQLZ = 103
|
249
|
+
INS_FMOVRSLZ = 104
|
250
|
+
INS_FMOVRDNZ = 105
|
251
|
+
INS_FMOVRQNZ = 106
|
252
|
+
INS_FMOVRSNZ = 107
|
253
|
+
INS_FMOVRDZ = 108
|
254
|
+
INS_FMOVRQZ = 109
|
255
|
+
INS_FMOVRSZ = 110
|
256
|
+
INS_FMOVS = 111
|
257
|
+
INS_FMUL8SUX16 = 112
|
258
|
+
INS_FMUL8ULX16 = 113
|
259
|
+
INS_FMUL8X16 = 114
|
260
|
+
INS_FMUL8X16AL = 115
|
261
|
+
INS_FMUL8X16AU = 116
|
262
|
+
INS_FMULD = 117
|
263
|
+
INS_FMULD8SUX16 = 118
|
264
|
+
INS_FMULD8ULX16 = 119
|
265
|
+
INS_FMULQ = 120
|
266
|
+
INS_FMULS = 121
|
267
|
+
INS_FNADDD = 122
|
268
|
+
INS_FNADDS = 123
|
269
|
+
INS_FNAND = 124
|
270
|
+
INS_FNANDS = 125
|
271
|
+
INS_FNEGD = 126
|
272
|
+
INS_FNEGQ = 127
|
273
|
+
INS_FNEGS = 128
|
274
|
+
INS_FNHADDD = 129
|
275
|
+
INS_FNHADDS = 130
|
276
|
+
INS_FNOR = 131
|
277
|
+
INS_FNORS = 132
|
278
|
+
INS_FNOT1 = 133
|
279
|
+
INS_FNOT1S = 134
|
280
|
+
INS_FNOT2 = 135
|
281
|
+
INS_FNOT2S = 136
|
282
|
+
INS_FONE = 137
|
283
|
+
INS_FONES = 138
|
284
|
+
INS_FOR = 139
|
285
|
+
INS_FORNOT1 = 140
|
286
|
+
INS_FORNOT1S = 141
|
287
|
+
INS_FORNOT2 = 142
|
288
|
+
INS_FORNOT2S = 143
|
289
|
+
INS_FORS = 144
|
290
|
+
INS_FPACK16 = 145
|
291
|
+
INS_FPACK32 = 146
|
292
|
+
INS_FPACKFIX = 147
|
293
|
+
INS_FPADD16 = 148
|
294
|
+
INS_FPADD16S = 149
|
295
|
+
INS_FPADD32 = 150
|
296
|
+
INS_FPADD32S = 151
|
297
|
+
INS_FPADD64 = 152
|
298
|
+
INS_FPMERGE = 153
|
299
|
+
INS_FPSUB16 = 154
|
300
|
+
INS_FPSUB16S = 155
|
301
|
+
INS_FPSUB32 = 156
|
302
|
+
INS_FPSUB32S = 157
|
303
|
+
INS_FQTOD = 158
|
304
|
+
INS_FQTOI = 159
|
305
|
+
INS_FQTOS = 160
|
306
|
+
INS_FQTOX = 161
|
307
|
+
INS_FSLAS16 = 162
|
308
|
+
INS_FSLAS32 = 163
|
309
|
+
INS_FSLL16 = 164
|
310
|
+
INS_FSLL32 = 165
|
311
|
+
INS_FSMULD = 166
|
312
|
+
INS_FSQRTD = 167
|
313
|
+
INS_FSQRTQ = 168
|
314
|
+
INS_FSQRTS = 169
|
315
|
+
INS_FSRA16 = 170
|
316
|
+
INS_FSRA32 = 171
|
317
|
+
INS_FSRC1 = 172
|
318
|
+
INS_FSRC1S = 173
|
319
|
+
INS_FSRC2 = 174
|
320
|
+
INS_FSRC2S = 175
|
321
|
+
INS_FSRL16 = 176
|
322
|
+
INS_FSRL32 = 177
|
323
|
+
INS_FSTOD = 178
|
324
|
+
INS_FSTOI = 179
|
325
|
+
INS_FSTOQ = 180
|
326
|
+
INS_FSTOX = 181
|
327
|
+
INS_FSUBD = 182
|
328
|
+
INS_FSUBQ = 183
|
329
|
+
INS_FSUBS = 184
|
330
|
+
INS_FXNOR = 185
|
331
|
+
INS_FXNORS = 186
|
332
|
+
INS_FXOR = 187
|
333
|
+
INS_FXORS = 188
|
334
|
+
INS_FXTOD = 189
|
335
|
+
INS_FXTOQ = 190
|
336
|
+
INS_FXTOS = 191
|
337
|
+
INS_FZERO = 192
|
338
|
+
INS_FZEROS = 193
|
339
|
+
INS_JMPL = 194
|
340
|
+
INS_LDD = 195
|
341
|
+
INS_LD = 196
|
342
|
+
INS_LDQ = 197
|
343
|
+
INS_LDSB = 198
|
344
|
+
INS_LDSH = 199
|
345
|
+
INS_LDSW = 200
|
346
|
+
INS_LDUB = 201
|
347
|
+
INS_LDUH = 202
|
348
|
+
INS_LDX = 203
|
349
|
+
INS_LZCNT = 204
|
350
|
+
INS_MEMBAR = 205
|
351
|
+
INS_MOVDTOX = 206
|
352
|
+
INS_MOV = 207
|
353
|
+
INS_MOVRGEZ = 208
|
354
|
+
INS_MOVRGZ = 209
|
355
|
+
INS_MOVRLEZ = 210
|
356
|
+
INS_MOVRLZ = 211
|
357
|
+
INS_MOVRNZ = 212
|
358
|
+
INS_MOVRZ = 213
|
359
|
+
INS_MOVSTOSW = 214
|
360
|
+
INS_MOVSTOUW = 215
|
361
|
+
INS_MULX = 216
|
362
|
+
INS_NOP = 217
|
363
|
+
INS_ORCC = 218
|
364
|
+
INS_ORNCC = 219
|
365
|
+
INS_ORN = 220
|
366
|
+
INS_OR = 221
|
367
|
+
INS_PDIST = 222
|
368
|
+
INS_PDISTN = 223
|
369
|
+
INS_POPC = 224
|
370
|
+
INS_RD = 225
|
371
|
+
INS_RESTORE = 226
|
372
|
+
INS_RETT = 227
|
373
|
+
INS_SAVE = 228
|
374
|
+
INS_SDIVCC = 229
|
375
|
+
INS_SDIVX = 230
|
376
|
+
INS_SDIV = 231
|
377
|
+
INS_SETHI = 232
|
378
|
+
INS_SHUTDOWN = 233
|
379
|
+
INS_SIAM = 234
|
380
|
+
INS_SLLX = 235
|
381
|
+
INS_SLL = 236
|
382
|
+
INS_SMULCC = 237
|
383
|
+
INS_SMUL = 238
|
384
|
+
INS_SRAX = 239
|
385
|
+
INS_SRA = 240
|
386
|
+
INS_SRLX = 241
|
387
|
+
INS_SRL = 242
|
388
|
+
INS_STBAR = 243
|
389
|
+
INS_STB = 244
|
390
|
+
INS_STD = 245
|
391
|
+
INS_ST = 246
|
392
|
+
INS_STH = 247
|
393
|
+
INS_STQ = 248
|
394
|
+
INS_STX = 249
|
395
|
+
INS_SUBCC = 250
|
396
|
+
INS_SUBX = 251
|
397
|
+
INS_SUBXCC = 252
|
398
|
+
INS_SUB = 253
|
399
|
+
INS_SWAP = 254
|
400
|
+
INS_TADDCCTV = 255
|
401
|
+
INS_TADDCC = 256
|
402
|
+
INS_T = 257
|
403
|
+
INS_TSUBCCTV = 258
|
404
|
+
INS_TSUBCC = 259
|
405
|
+
INS_UDIVCC = 260
|
406
|
+
INS_UDIVX = 261
|
407
|
+
INS_UDIV = 262
|
408
|
+
INS_UMULCC = 263
|
409
|
+
INS_UMULXHI = 264
|
410
|
+
INS_UMUL = 265
|
411
|
+
INS_UNIMP = 266
|
412
|
+
INS_FCMPED = 267
|
413
|
+
INS_FCMPEQ = 268
|
414
|
+
INS_FCMPES = 269
|
415
|
+
INS_WR = 270
|
416
|
+
INS_XMULX = 271
|
417
|
+
INS_XMULXHI = 272
|
418
|
+
INS_XNORCC = 273
|
419
|
+
INS_XNOR = 274
|
420
|
+
INS_XORCC = 275
|
421
|
+
INS_XOR = 276
|
422
|
+
INS_RET = 277
|
423
|
+
INS_RETL = 278
|
424
|
+
INS_ENDING = 279
|
425
|
+
|
426
|
+
GRP_INVALID = 0
|
427
|
+
GRP_JUMP = 1
|
428
|
+
GRP_HARDQUAD = 128
|
429
|
+
GRP_V9 = 129
|
430
|
+
GRP_VIS = 130
|
431
|
+
GRP_VIS2 = 131
|
432
|
+
GRP_VIS3 = 132
|
433
|
+
GRP_32BIT = 133
|
434
|
+
GRP_64BIT = 134
|
435
|
+
GRP_ENDING = 135
|
436
|
+
|
437
|
+
extend Register
|
438
|
+
end
|
439
|
+
end
|