crabstone 3.0.3 → 4.0.0

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Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +45 -42
  3. data/README.md +16 -33
  4. data/lib/crabstone.rb +5 -557
  5. data/lib/crabstone/arch.rb +37 -0
  6. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  7. data/lib/crabstone/arch/3/arm64.rb +124 -0
  8. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  9. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  10. data/lib/crabstone/arch/3/mips.rb +57 -0
  11. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  12. data/lib/crabstone/arch/3/ppc.rb +73 -0
  13. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  14. data/lib/crabstone/arch/3/sparc.rb +60 -0
  15. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  16. data/lib/crabstone/arch/3/sysz.rb +67 -0
  17. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  18. data/lib/crabstone/arch/3/x86.rb +82 -0
  19. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  20. data/lib/crabstone/arch/3/xcore.rb +59 -0
  21. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  22. data/lib/crabstone/arch/4/arm.rb +110 -0
  23. data/lib/crabstone/arch/4/arm64.rb +125 -0
  24. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  25. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  26. data/lib/crabstone/arch/4/evm.rb +20 -0
  27. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  28. data/lib/crabstone/arch/4/m680x.rb +106 -0
  29. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  30. data/lib/crabstone/arch/4/m68k.rb +129 -0
  31. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  32. data/lib/crabstone/arch/4/mips.rb +57 -0
  33. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  34. data/lib/crabstone/arch/4/ppc.rb +73 -0
  35. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  36. data/lib/crabstone/arch/4/sparc.rb +60 -0
  37. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  38. data/lib/crabstone/arch/4/sysz.rb +67 -0
  39. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  40. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  41. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  42. data/lib/crabstone/arch/4/x86.rb +91 -0
  43. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  44. data/lib/crabstone/arch/4/xcore.rb +59 -0
  45. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  46. data/lib/crabstone/arch/extension.rb +27 -0
  47. data/lib/crabstone/arch/register.rb +36 -0
  48. data/lib/crabstone/binding.rb +60 -0
  49. data/lib/crabstone/binding/3/detail.rb +36 -0
  50. data/lib/crabstone/binding/3/instruction.rb +23 -0
  51. data/lib/crabstone/binding/4/detail.rb +40 -0
  52. data/lib/crabstone/binding/4/instruction.rb +23 -0
  53. data/lib/crabstone/binding/structs.rb +32 -0
  54. data/lib/crabstone/constants.rb +110 -0
  55. data/lib/crabstone/cs_version.rb +49 -0
  56. data/lib/crabstone/disassembler.rb +153 -0
  57. data/lib/crabstone/error.rb +60 -0
  58. data/lib/crabstone/instruction.rb +183 -0
  59. data/lib/crabstone/version.rb +5 -0
  60. metadata +128 -324
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
data/test/MC/ARM/neon-cmp-encoding.s.cs DELETED
@@ -1,88 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17
3
- 0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17
4
- 0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17
5
- 0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17
6
- 0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9
7
- 0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9
8
- 0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9
9
- 0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9
10
- 0xb1,0x03,0x40,0xf2 = vcge.s8 d16, d16, d17
11
- 0xb1,0x03,0x50,0xf2 = vcge.s16 d16, d16, d17
12
- 0xb1,0x03,0x60,0xf2 = vcge.s32 d16, d16, d17
13
- 0xb1,0x03,0x40,0xf3 = vcge.u8 d16, d16, d17
14
- 0xb1,0x03,0x50,0xf3 = vcge.u16 d16, d16, d17
15
- 0xb1,0x03,0x60,0xf3 = vcge.u32 d16, d16, d17
16
- 0xa1,0x0e,0x40,0xf3 = vcge.f32 d16, d16, d17
17
- 0xf2,0x03,0x40,0xf2 = vcge.s8 q8, q8, q9
18
- 0xf2,0x03,0x50,0xf2 = vcge.s16 q8, q8, q9
19
- 0xf2,0x03,0x60,0xf2 = vcge.s32 q8, q8, q9
20
- 0xf2,0x03,0x40,0xf3 = vcge.u8 q8, q8, q9
21
- 0xf2,0x03,0x50,0xf3 = vcge.u16 q8, q8, q9
22
- 0xf2,0x03,0x60,0xf3 = vcge.u32 q8, q8, q9
23
- 0xe2,0x0e,0x40,0xf3 = vcge.f32 q8, q8, q9
24
- 0xb1,0x0e,0x40,0xf3 = vacge.f32 d16, d16, d17
25
- 0xf2,0x0e,0x40,0xf3 = vacge.f32 q8, q8, q9
26
- 0xa1,0x03,0x40,0xf2 = vcgt.s8 d16, d16, d17
27
- 0xa1,0x03,0x50,0xf2 = vcgt.s16 d16, d16, d17
28
- 0xa1,0x03,0x60,0xf2 = vcgt.s32 d16, d16, d17
29
- 0xa1,0x03,0x40,0xf3 = vcgt.u8 d16, d16, d17
30
- 0xa1,0x03,0x50,0xf3 = vcgt.u16 d16, d16, d17
31
- 0xa1,0x03,0x60,0xf3 = vcgt.u32 d16, d16, d17
32
- 0xa1,0x0e,0x60,0xf3 = vcgt.f32 d16, d16, d17
33
- 0xe2,0x03,0x40,0xf2 = vcgt.s8 q8, q8, q9
34
- 0xe2,0x03,0x50,0xf2 = vcgt.s16 q8, q8, q9
35
- 0xe2,0x03,0x60,0xf2 = vcgt.s32 q8, q8, q9
36
- 0xe2,0x03,0x40,0xf3 = vcgt.u8 q8, q8, q9
37
- 0xe2,0x03,0x50,0xf3 = vcgt.u16 q8, q8, q9
38
- 0xe2,0x03,0x60,0xf3 = vcgt.u32 q8, q8, q9
39
- 0xe2,0x0e,0x60,0xf3 = vcgt.f32 q8, q8, q9
40
- 0xb1,0x0e,0x60,0xf3 = vacgt.f32 d16, d16, d17
41
- 0xf2,0x0e,0x60,0xf3 = vacgt.f32 q8, q8, q9
42
- 0xb1,0x08,0x40,0xf2 = vtst.8 d16, d16, d17
43
- 0xb1,0x08,0x50,0xf2 = vtst.16 d16, d16, d17
44
- 0xb1,0x08,0x60,0xf2 = vtst.32 d16, d16, d17
45
- 0xf2,0x08,0x40,0xf2 = vtst.8 q8, q8, q9
46
- 0xf2,0x08,0x50,0xf2 = vtst.16 q8, q8, q9
47
- 0xf2,0x08,0x60,0xf2 = vtst.32 q8, q8, q9
48
- 0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0
49
- 0xa0,0x00,0xf1,0xf3 = vcge.s8 d16, d16, #0
50
- 0xa0,0x01,0xf1,0xf3 = vcle.s8 d16, d16, #0
51
- 0x20,0x00,0xf1,0xf3 = vcgt.s8 d16, d16, #0
52
- 0x20,0x02,0xf1,0xf3 = vclt.s8 d16, d16, #0
53
- 0x6a,0x83,0x46,0xf2 = vcgt.s8 q12, q3, q13
54
- 0x6a,0x83,0x56,0xf2 = vcgt.s16 q12, q3, q13
55
- 0x6a,0x83,0x66,0xf2 = vcgt.s32 q12, q3, q13
56
- 0x6a,0x83,0x46,0xf3 = vcgt.u8 q12, q3, q13
57
- 0x6a,0x83,0x56,0xf3 = vcgt.u16 q12, q3, q13
58
- 0x6a,0x83,0x66,0xf3 = vcgt.u32 q12, q3, q13
59
- 0x6a,0x8e,0x66,0xf3 = vcgt.f32 q12, q3, q13
60
- 0x0d,0xc3,0x03,0xf2 = vcgt.s8 d12, d3, d13
61
- 0x0d,0xc3,0x13,0xf2 = vcgt.s16 d12, d3, d13
62
- 0x0d,0xc3,0x23,0xf2 = vcgt.s32 d12, d3, d13
63
- 0x0d,0xc3,0x03,0xf3 = vcgt.u8 d12, d3, d13
64
- 0x0d,0xc3,0x13,0xf3 = vcgt.u16 d12, d3, d13
65
- 0x0d,0xc3,0x23,0xf3 = vcgt.u32 d12, d3, d13
66
- 0x0d,0xce,0x23,0xf3 = vcgt.f32 d12, d3, d13
67
- 0xb0,0x03,0x41,0xf2 = vcge.s8 d16, d17, d16
68
- 0xb0,0x03,0x51,0xf2 = vcge.s16 d16, d17, d16
69
- 0xb0,0x03,0x61,0xf2 = vcge.s32 d16, d17, d16
70
- 0xb0,0x03,0x41,0xf3 = vcge.u8 d16, d17, d16
71
- 0xb0,0x03,0x51,0xf3 = vcge.u16 d16, d17, d16
72
- 0xb0,0x03,0x61,0xf3 = vcge.u32 d16, d17, d16
73
- 0xa0,0x0e,0x41,0xf3 = vcge.f32 d16, d17, d16
74
- 0xf0,0x03,0x42,0xf2 = vcge.s8 q8, q9, q8
75
- 0xf0,0x03,0x52,0xf2 = vcge.s16 q8, q9, q8
76
- 0xf0,0x03,0x62,0xf2 = vcge.s32 q8, q9, q8
77
- 0xf0,0x03,0x42,0xf3 = vcge.u8 q8, q9, q8
78
- 0xf0,0x03,0x52,0xf3 = vcge.u16 q8, q9, q8
79
- 0xf0,0x03,0x62,0xf3 = vcge.u32 q8, q9, q8
80
- 0xe0,0x0e,0x42,0xf3 = vcge.f32 q8, q9, q8
81
- 0xf6,0x2e,0x68,0xf3 = vacgt.f32 q9, q12, q11
82
- 0x1b,0x9e,0x2c,0xf3 = vacgt.f32 d9, d12, d11
83
- 0xf6,0x6e,0x68,0xf3 = vacgt.f32 q11, q12, q11
84
- 0x1b,0xbe,0x2c,0xf3 = vacgt.f32 d11, d12, d11
85
- 0xf6,0x2e,0x48,0xf3 = vacge.f32 q9, q12, q11
86
- 0x1b,0x9e,0x0c,0xf3 = vacge.f32 d9, d12, d11
87
- 0xf6,0x6e,0x48,0xf3 = vacge.f32 q11, q12, q11
88
- 0x1b,0xbe,0x0c,0xf3 = vacge.f32 d11, d12, d11
data/test/MC/ARM/neon-convert-encoding.s.cs DELETED
@@ -1,27 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16
3
- 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16
4
- 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16
5
- 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16
6
- 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8
7
- 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8
8
- 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8
9
- 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8
10
- 0x30,0x0f,0xff,0xf2 = vcvt.s32.f32 d16, d16, #1
11
- 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16
12
- 0x30,0x0f,0xff,0xf3 = vcvt.u32.f32 d16, d16, #1
13
- 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16
14
- 0x30,0x0e,0xff,0xf2 = vcvt.f32.s32 d16, d16, #1
15
- 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16
16
- 0x30,0x0e,0xff,0xf3 = vcvt.f32.u32 d16, d16, #1
17
- 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16
18
- 0x70,0x0f,0xff,0xf2 = vcvt.s32.f32 q8, q8, #1
19
- 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8
20
- 0x70,0x0f,0xff,0xf3 = vcvt.u32.f32 q8, q8, #1
21
- 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8
22
- 0x70,0x0e,0xff,0xf2 = vcvt.f32.s32 q8, q8, #1
23
- 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8
24
- 0x70,0x0e,0xff,0xf3 = vcvt.f32.u32 q8, q8, #1
25
- 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8
26
- 0x20,0x07,0xf6,0xf3 = vcvt.f32.f16 q8, d16
27
- 0x20,0x06,0xf6,0xf3 = vcvt.f16.f32 d16, q8
data/test/MC/ARM/neon-crypto.s.cs DELETED
@@ -1,16 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
2
- 0x42,0x03,0xb0,0xf3 = aesd.8 q0, q1
3
- 0x02,0x03,0xb0,0xf3 = aese.8 q0, q1
4
- 0xc2,0x03,0xb0,0xf3 = aesimc.8 q0, q1
5
- 0x82,0x03,0xb0,0xf3 = aesmc.8 q0, q1
6
- 0xc2,0x02,0xb9,0xf3 = sha1h.32 q0, q1
7
- 0x82,0x03,0xba,0xf3 = sha1su1.32 q0, q1
8
- 0xc2,0x03,0xba,0xf3 = sha256su0.32 q0, q1
9
- 0x44,0x0c,0x02,0xf2 = sha1c.32 q0, q1, q2
10
- 0x44,0x0c,0x22,0xf2 = sha1m.32 q0, q1, q2
11
- 0x44,0x0c,0x12,0xf2 = sha1p.32 q0, q1, q2
12
- 0x44,0x0c,0x32,0xf2 = sha1su0.32 q0, q1, q2
13
- 0x44,0x0c,0x02,0xf3 = sha256h.32 q0, q1, q2
14
- 0x44,0x0c,0x12,0xf3 = sha256h2.32 q0, q1, q2
15
- 0x44,0x0c,0x22,0xf3 = sha256su1.32 q0, q1, q2
16
- 0xa1,0x0e,0xe0,0xf2 = vmull.p64 q8, d16, d17
data/test/MC/ARM/neon-dup-encoding.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x90,0x0b,0xc0,0xee = vdup.8 d16, r0
3
- 0xb0,0x0b,0x80,0xee = vdup.16 d16, r0
4
- 0x90,0x0b,0x80,0xee = vdup.32 d16, r0
5
- 0x90,0x0b,0xe0,0xee = vdup.8 q8, r0
6
- 0xb0,0x0b,0xa0,0xee = vdup.16 q8, r0
7
- 0x90,0x0b,0xa0,0xee = vdup.32 q8, r0
8
- 0x20,0x0c,0xf3,0xf3 = vdup.8 d16, d16[1]
9
- 0x20,0x0c,0xf6,0xf3 = vdup.16 d16, d16[1]
10
- 0x20,0x0c,0xfc,0xf3 = vdup.32 d16, d16[1]
11
- 0x60,0x0c,0xf3,0xf3 = vdup.8 q8, d16[1]
12
- 0x60,0x0c,0xf6,0xf3 = vdup.16 q8, d16[1]
13
- 0x60,0x0c,0xfc,0xf3 = vdup.32 q8, d16[1]
data/test/MC/ARM/neon-minmax-encoding.s.cs DELETED
@@ -1,57 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x03,0x16,0x02,0xf2 = vmax.s8 d1, d2, d3
3
- 0x06,0x46,0x15,0xf2 = vmax.s16 d4, d5, d6
4
- 0x09,0x76,0x28,0xf2 = vmax.s32 d7, d8, d9
5
- 0x0c,0xa6,0x0b,0xf3 = vmax.u8 d10, d11, d12
6
- 0x0f,0xd6,0x1e,0xf3 = vmax.u16 d13, d14, d15
7
- 0xa2,0x06,0x61,0xf3 = vmax.u32 d16, d17, d18
8
- 0xa5,0x3f,0x44,0xf2 = vmax.f32 d19, d20, d21
9
- 0x03,0x26,0x02,0xf2 = vmax.s8 d2, d2, d3
10
- 0x06,0x56,0x15,0xf2 = vmax.s16 d5, d5, d6
11
- 0x09,0x86,0x28,0xf2 = vmax.s32 d8, d8, d9
12
- 0x0c,0xb6,0x0b,0xf3 = vmax.u8 d11, d11, d12
13
- 0x0f,0xe6,0x1e,0xf3 = vmax.u16 d14, d14, d15
14
- 0xa2,0x16,0x61,0xf3 = vmax.u32 d17, d17, d18
15
- 0xa5,0x4f,0x44,0xf2 = vmax.f32 d20, d20, d21
16
- 0x46,0x26,0x04,0xf2 = vmax.s8 q1, q2, q3
17
- 0x4c,0x86,0x1a,0xf2 = vmax.s16 q4, q5, q6
18
- 0xe2,0xe6,0x20,0xf2 = vmax.s32 q7, q8, q9
19
- 0xe8,0x46,0x46,0xf3 = vmax.u8 q10, q11, q12
20
- 0xee,0xa6,0x5c,0xf3 = vmax.u16 q13, q14, q15
21
- 0x60,0xc6,0x2e,0xf3 = vmax.u32 q6, q7, q8
22
- 0x42,0x2f,0x4a,0xf2 = vmax.f32 q9, q5, q1
23
- 0x46,0x46,0x04,0xf2 = vmax.s8 q2, q2, q3
24
- 0x4c,0xa6,0x1a,0xf2 = vmax.s16 q5, q5, q6
25
- 0xe2,0x06,0x60,0xf2 = vmax.s32 q8, q8, q9
26
- 0xc4,0x66,0x46,0xf3 = vmax.u8 q11, q11, q2
27
- 0x4a,0x86,0x18,0xf3 = vmax.u16 q4, q4, q5
28
- 0x60,0xe6,0x2e,0xf3 = vmax.u32 q7, q7, q8
29
- 0x42,0x4f,0x04,0xf2 = vmax.f32 q2, q2, q1
30
- 0x13,0x16,0x02,0xf2 = vmin.s8 d1, d2, d3
31
- 0x16,0x46,0x15,0xf2 = vmin.s16 d4, d5, d6
32
- 0x19,0x76,0x28,0xf2 = vmin.s32 d7, d8, d9
33
- 0x1c,0xa6,0x0b,0xf3 = vmin.u8 d10, d11, d12
34
- 0x1f,0xd6,0x1e,0xf3 = vmin.u16 d13, d14, d15
35
- 0xb2,0x06,0x61,0xf3 = vmin.u32 d16, d17, d18
36
- 0xa5,0x3f,0x64,0xf2 = vmin.f32 d19, d20, d21
37
- 0x13,0x26,0x02,0xf2 = vmin.s8 d2, d2, d3
38
- 0x16,0x56,0x15,0xf2 = vmin.s16 d5, d5, d6
39
- 0x19,0x86,0x28,0xf2 = vmin.s32 d8, d8, d9
40
- 0x1c,0xb6,0x0b,0xf3 = vmin.u8 d11, d11, d12
41
- 0x1f,0xe6,0x1e,0xf3 = vmin.u16 d14, d14, d15
42
- 0xb2,0x16,0x61,0xf3 = vmin.u32 d17, d17, d18
43
- 0xa5,0x4f,0x64,0xf2 = vmin.f32 d20, d20, d21
44
- 0x56,0x26,0x04,0xf2 = vmin.s8 q1, q2, q3
45
- 0x5c,0x86,0x1a,0xf2 = vmin.s16 q4, q5, q6
46
- 0xf2,0xe6,0x20,0xf2 = vmin.s32 q7, q8, q9
47
- 0xf8,0x46,0x46,0xf3 = vmin.u8 q10, q11, q12
48
- 0xfe,0xa6,0x5c,0xf3 = vmin.u16 q13, q14, q15
49
- 0x70,0xc6,0x2e,0xf3 = vmin.u32 q6, q7, q8
50
- 0x42,0x2f,0x6a,0xf2 = vmin.f32 q9, q5, q1
51
- 0x56,0x46,0x04,0xf2 = vmin.s8 q2, q2, q3
52
- 0x5c,0xa6,0x1a,0xf2 = vmin.s16 q5, q5, q6
53
- 0xf2,0x06,0x60,0xf2 = vmin.s32 q8, q8, q9
54
- 0xd4,0x66,0x46,0xf3 = vmin.u8 q11, q11, q2
55
- 0x5a,0x86,0x18,0xf3 = vmin.u16 q4, q4, q5
56
- 0x70,0xe6,0x2e,0xf3 = vmin.u32 q7, q7, q8
57
- 0x42,0x4f,0x24,0xf2 = vmin.f32 q2, q2, q1
data/test/MC/ARM/neon-mov-encoding.s.cs DELETED
@@ -1,76 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x18,0x0e,0xc0,0xf2 = vmov.i8 d16, #0x8
3
- 0x10,0x08,0xc1,0xf2 = vmov.i16 d16, #0x10
4
- 0x10,0x0a,0xc1,0xf2 = vmov.i16 d16, #0x1000
5
- 0x10,0x00,0xc2,0xf2 = vmov.i32 d16, #0x20
6
- 0x10,0x02,0xc2,0xf2 = vmov.i32 d16, #0x2000
7
- 0x10,0x04,0xc2,0xf2 = vmov.i32 d16, #0x200000
8
- 0x10,0x06,0xc2,0xf2 = vmov.i32 d16, #0x20000000
9
- 0x10,0x0c,0xc2,0xf2 = vmov.i32 d16, #0x20ff
10
- 0x10,0x0d,0xc2,0xf2 = vmov.i32 d16, #0x20ffff
11
- 0x33,0x0e,0xc1,0xf3 = vmov.i64 d16, #0xff0000ff0000ffff
12
- 0x58,0x0e,0xc0,0xf2 = vmov.i8 q8, #0x8
13
- 0x50,0x08,0xc1,0xf2 = vmov.i16 q8, #0x10
14
- 0x50,0x0a,0xc1,0xf2 = vmov.i16 q8, #0x1000
15
- 0x50,0x00,0xc2,0xf2 = vmov.i32 q8, #0x20
16
- 0x50,0x02,0xc2,0xf2 = vmov.i32 q8, #0x2000
17
- 0x50,0x04,0xc2,0xf2 = vmov.i32 q8, #0x200000
18
- 0x50,0x06,0xc2,0xf2 = vmov.i32 q8, #0x20000000
19
- 0x50,0x0c,0xc2,0xf2 = vmov.i32 q8, #0x20ff
20
- 0x50,0x0d,0xc2,0xf2 = vmov.i32 q8, #0x20ffff
21
- 0x73,0x0e,0xc1,0xf3 = vmov.i64 q8, #0xff0000ff0000ffff
22
- 0x30,0x08,0xc1,0xf2 = vmvn.i16 d16, #0x10
23
- 0x30,0x0a,0xc1,0xf2 = vmvn.i16 d16, #0x1000
24
- 0x30,0x00,0xc2,0xf2 = vmvn.i32 d16, #0x20
25
- 0x30,0x02,0xc2,0xf2 = vmvn.i32 d16, #0x2000
26
- 0x30,0x04,0xc2,0xf2 = vmvn.i32 d16, #0x200000
27
- 0x30,0x06,0xc2,0xf2 = vmvn.i32 d16, #0x20000000
28
- 0x30,0x0c,0xc2,0xf2 = vmvn.i32 d16, #0x20ff
29
- 0x30,0x0d,0xc2,0xf2 = vmvn.i32 d16, #0x20ffff
30
- 0x30,0x0a,0xc8,0xf2 = vmovl.s8 q8, d16
31
- 0x30,0x0a,0xd0,0xf2 = vmovl.s16 q8, d16
32
- 0x30,0x0a,0xe0,0xf2 = vmovl.s32 q8, d16
33
- 0x30,0x0a,0xc8,0xf3 = vmovl.u8 q8, d16
34
- 0x30,0x0a,0xd0,0xf3 = vmovl.u16 q8, d16
35
- 0x30,0x0a,0xe0,0xf3 = vmovl.u32 q8, d16
36
- 0x20,0x02,0xf2,0xf3 = vmovn.i16 d16, q8
37
- 0x20,0x02,0xf6,0xf3 = vmovn.i32 d16, q8
38
- 0x20,0x02,0xfa,0xf3 = vmovn.i64 d16, q8
39
- 0xa0,0x02,0xf2,0xf3 = vqmovn.s16 d16, q8
40
- 0xa0,0x02,0xf6,0xf3 = vqmovn.s32 d16, q8
41
- 0xa0,0x02,0xfa,0xf3 = vqmovn.s64 d16, q8
42
- 0xe0,0x02,0xf2,0xf3 = vqmovn.u16 d16, q8
43
- 0xe0,0x02,0xf6,0xf3 = vqmovn.u32 d16, q8
44
- 0xe0,0x02,0xfa,0xf3 = vqmovn.u64 d16, q8
45
- 0x60,0x02,0xf2,0xf3 = vqmovun.s16 d16, q8
46
- 0x60,0x02,0xf6,0xf3 = vqmovun.s32 d16, q8
47
- 0x60,0x02,0xfa,0xf3 = vqmovun.s64 d16, q8
48
- 0xb0,0x0b,0x50,0xee = vmov.s8 r0, d16[1]
49
- 0xf0,0x0b,0x10,0xee = vmov.s16 r0, d16[1]
50
- 0xb0,0x0b,0xd0,0xee = vmov.u8 r0, d16[1]
51
- 0xf0,0x0b,0x90,0xee = vmov.u16 r0, d16[1]
52
- 0x90,0x0b,0x30,0xee = vmov.32 r0, d16[1]
53
- 0xb0,0x1b,0x40,0xee = vmov.8 d16[1], r1
54
- 0xf0,0x1b,0x00,0xee = vmov.16 d16[1], r1
55
- 0x90,0x1b,0x20,0xee = vmov.32 d16[1], r1
56
- 0xb0,0x1b,0x42,0xee = vmov.8 d18[1], r1
57
- 0xf0,0x1b,0x02,0xee = vmov.16 d18[1], r1
58
- 0x90,0x1b,0x22,0xee = vmov.32 d18[1], r1
59
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
60
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
61
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
62
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
63
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
64
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
65
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
66
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
67
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
68
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
69
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
70
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
71
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
72
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
73
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
74
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
75
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
76
- 0x82,0x15,0xb0,0xf3 = vmvn d1, d2
data/test/MC/ARM/neon-mul-accum-encoding.s.cs DELETED
@@ -1,39 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xa1,0x09,0x42,0xf2 = vmla.i8 d16, d18, d17
3
- 0xa1,0x09,0x52,0xf2 = vmla.i16 d16, d18, d17
4
- 0xa1,0x09,0x62,0xf2 = vmla.i32 d16, d18, d17
5
- 0xb1,0x0d,0x42,0xf2 = vmla.f32 d16, d18, d17
6
- 0xe4,0x29,0x40,0xf2 = vmla.i8 q9, q8, q10
7
- 0xe4,0x29,0x50,0xf2 = vmla.i16 q9, q8, q10
8
- 0xe4,0x29,0x60,0xf2 = vmla.i32 q9, q8, q10
9
- 0xf4,0x2d,0x40,0xf2 = vmla.f32 q9, q8, q10
10
- 0xc3,0x80,0xe0,0xf3 = vmla.i32 q12, q8, d3[0]
11
- 0xa2,0x08,0xc3,0xf2 = vmlal.s8 q8, d19, d18
12
- 0xa2,0x08,0xd3,0xf2 = vmlal.s16 q8, d19, d18
13
- 0xa2,0x08,0xe3,0xf2 = vmlal.s32 q8, d19, d18
14
- 0xa2,0x08,0xc3,0xf3 = vmlal.u8 q8, d19, d18
15
- 0xa2,0x08,0xd3,0xf3 = vmlal.u16 q8, d19, d18
16
- 0xa2,0x08,0xe3,0xf3 = vmlal.u32 q8, d19, d18
17
- 0xa2,0x09,0xd3,0xf2 = vqdmlal.s16 q8, d19, d18
18
- 0xa2,0x09,0xe3,0xf2 = vqdmlal.s32 q8, d19, d18
19
- 0x47,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[0]
20
- 0x4f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[1]
21
- 0x67,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[2]
22
- 0x6f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[3]
23
- 0xa1,0x09,0x42,0xf3 = vmls.i8 d16, d18, d17
24
- 0xa1,0x09,0x52,0xf3 = vmls.i16 d16, d18, d17
25
- 0xa1,0x09,0x62,0xf3 = vmls.i32 d16, d18, d17
26
- 0xb1,0x0d,0x62,0xf2 = vmls.f32 d16, d18, d17
27
- 0xe4,0x29,0x40,0xf3 = vmls.i8 q9, q8, q10
28
- 0xe4,0x29,0x50,0xf3 = vmls.i16 q9, q8, q10
29
- 0xe4,0x29,0x60,0xf3 = vmls.i32 q9, q8, q10
30
- 0xf4,0x2d,0x60,0xf2 = vmls.f32 q9, q8, q10
31
- 0xe6,0x84,0x98,0xf3 = vmls.i16 q4, q12, d6[2]
32
- 0xa2,0x0a,0xc3,0xf2 = vmlsl.s8 q8, d19, d18
33
- 0xa2,0x0a,0xd3,0xf2 = vmlsl.s16 q8, d19, d18
34
- 0xa2,0x0a,0xe3,0xf2 = vmlsl.s32 q8, d19, d18
35
- 0xa2,0x0a,0xc3,0xf3 = vmlsl.u8 q8, d19, d18
36
- 0xa2,0x0a,0xd3,0xf3 = vmlsl.u16 q8, d19, d18
37
- 0xa2,0x0a,0xe3,0xf3 = vmlsl.u32 q8, d19, d18
38
- 0xa2,0x0b,0xd3,0xf2 = vqdmlsl.s16 q8, d19, d18
39
- 0xa2,0x0b,0xe3,0xf2 = vqdmlsl.s32 q8, d19, d18
data/test/MC/ARM/neon-mul-encoding.s.cs DELETED
@@ -1,72 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17
3
- 0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17
4
- 0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17
5
- 0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17
6
- 0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9
7
- 0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9
8
- 0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9
9
- 0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9
10
- 0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17
11
- 0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9
12
- 0x68,0x28,0xd8,0xf2 = vmul.i16 d18, d8, d0[3]
13
- 0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17
14
- 0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17
15
- 0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17
16
- 0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17
17
- 0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9
18
- 0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9
19
- 0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9
20
- 0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9
21
- 0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17
22
- 0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9
23
- 0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17
24
- 0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17
25
- 0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9
26
- 0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9
27
- 0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17
28
- 0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17
29
- 0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9
30
- 0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9
31
- 0x43,0xbc,0x92,0xf2 = vqdmulh.s16 d11, d2, d3[0]
32
- 0xa1,0x0b,0x50,0xf3 = vqrdmulh.s16 d16, d16, d17
33
- 0xa1,0x0b,0x60,0xf3 = vqrdmulh.s32 d16, d16, d17
34
- 0xe2,0x0b,0x50,0xf3 = vqrdmulh.s16 q8, q8, q9
35
- 0xe2,0x0b,0x60,0xf3 = vqrdmulh.s32 q8, q8, q9
36
- 0xa1,0x0c,0xc0,0xf2 = vmull.s8 q8, d16, d17
37
- 0xa1,0x0c,0xd0,0xf2 = vmull.s16 q8, d16, d17
38
- 0xa1,0x0c,0xe0,0xf2 = vmull.s32 q8, d16, d17
39
- 0xa1,0x0c,0xc0,0xf3 = vmull.u8 q8, d16, d17
40
- 0xa1,0x0c,0xd0,0xf3 = vmull.u16 q8, d16, d17
41
- 0xa1,0x0c,0xe0,0xf3 = vmull.u32 q8, d16, d17
42
- 0xa1,0x0e,0xc0,0xf2 = vmull.p8 q8, d16, d17
43
- 0xa1,0x0d,0xd0,0xf2 = vqdmull.s16 q8, d16, d17
44
- 0xa1,0x0d,0xe0,0xf2 = vqdmull.s32 q8, d16, d17
45
- 0x64,0x08,0x90,0xf2 = vmul.i16 d0, d0, d4[2]
46
- 0x6f,0x18,0x91,0xf2 = vmul.i16 d1, d1, d7[3]
47
- 0x49,0x28,0x92,0xf2 = vmul.i16 d2, d2, d1[1]
48
- 0x42,0x38,0xa3,0xf2 = vmul.i32 d3, d3, d2[0]
49
- 0x63,0x48,0xa4,0xf2 = vmul.i32 d4, d4, d3[1]
50
- 0x44,0x58,0xa5,0xf2 = vmul.i32 d5, d5, d4[0]
51
- 0x65,0x69,0xa6,0xf2 = vmul.f32 d6, d6, d5[1]
52
- 0x64,0x08,0x90,0xf3 = vmul.i16 q0, q0, d4[2]
53
- 0x6f,0x28,0x92,0xf3 = vmul.i16 q1, q1, d7[3]
54
- 0x49,0x48,0x94,0xf3 = vmul.i16 q2, q2, d1[1]
55
- 0x42,0x68,0xa6,0xf3 = vmul.i32 q3, q3, d2[0]
56
- 0x63,0x88,0xa8,0xf3 = vmul.i32 q4, q4, d3[1]
57
- 0x44,0xa8,0xaa,0xf3 = vmul.i32 q5, q5, d4[0]
58
- 0x65,0xc9,0xac,0xf3 = vmul.f32 q6, q6, d5[1]
59
- 0x64,0x98,0x90,0xf2 = vmul.i16 d9, d0, d4[2]
60
- 0x6f,0x88,0x91,0xf2 = vmul.i16 d8, d1, d7[3]
61
- 0x49,0x78,0x92,0xf2 = vmul.i16 d7, d2, d1[1]
62
- 0x42,0x68,0xa3,0xf2 = vmul.i32 d6, d3, d2[0]
63
- 0x63,0x58,0xa4,0xf2 = vmul.i32 d5, d4, d3[1]
64
- 0x44,0x48,0xa5,0xf2 = vmul.i32 d4, d5, d4[0]
65
- 0x65,0x39,0xa6,0xf2 = vmul.f32 d3, d6, d5[1]
66
- 0x64,0x28,0xd0,0xf3 = vmul.i16 q9, q0, d4[2]
67
- 0x6f,0x08,0xd2,0xf3 = vmul.i16 q8, q1, d7[3]
68
- 0x49,0xe8,0x94,0xf3 = vmul.i16 q7, q2, d1[1]
69
- 0x42,0xc8,0xa6,0xf3 = vmul.i32 q6, q3, d2[0]
70
- 0x63,0xa8,0xa8,0xf3 = vmul.i32 q5, q4, d3[1]
71
- 0x44,0x88,0xaa,0xf3 = vmul.i32 q4, q5, d4[0]
72
- 0x65,0x69,0xac,0xf3 = vmul.f32 q3, q6, d5[1]
data/test/MC/ARM/neon-neg-encoding.s.cs DELETED
@@ -1,15 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xa0,0x03,0xf1,0xf3 = vneg.s8 d16, d16
3
- 0xa0,0x03,0xf5,0xf3 = vneg.s16 d16, d16
4
- 0xa0,0x03,0xf9,0xf3 = vneg.s32 d16, d16
5
- 0xa0,0x07,0xf9,0xf3 = vneg.f32 d16, d16
6
- 0xe0,0x03,0xf1,0xf3 = vneg.s8 q8, q8
7
- 0xe0,0x03,0xf5,0xf3 = vneg.s16 q8, q8
8
- 0xe0,0x03,0xf9,0xf3 = vneg.s32 q8, q8
9
- 0xe0,0x07,0xf9,0xf3 = vneg.f32 q8, q8
10
- 0xa0,0x07,0xf0,0xf3 = vqneg.s8 d16, d16
11
- 0xa0,0x07,0xf4,0xf3 = vqneg.s16 d16, d16
12
- 0xa0,0x07,0xf8,0xf3 = vqneg.s32 d16, d16
13
- 0xe0,0x07,0xf0,0xf3 = vqneg.s8 q8, q8
14
- 0xe0,0x07,0xf4,0xf3 = vqneg.s16 q8, q8
15
- 0xe0,0x07,0xf8,0xf3 = vqneg.s32 q8, q8
data/test/MC/ARM/neon-pairwise-encoding.s.cs DELETED
@@ -1,47 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xb0,0x0b,0x41,0xf2 = vpadd.i8 d16, d17, d16
3
- 0xb0,0x0b,0x51,0xf2 = vpadd.i16 d16, d17, d16
4
- 0xb0,0x0b,0x61,0xf2 = vpadd.i32 d16, d17, d16
5
- 0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17
6
- 0xb0,0x1b,0x41,0xf2 = vpadd.i8 d17, d17, d16
7
- 0xb0,0x1b,0x51,0xf2 = vpadd.i16 d17, d17, d16
8
- 0xb0,0x1b,0x61,0xf2 = vpadd.i32 d17, d17, d16
9
- 0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17
10
- 0x20,0x02,0xf0,0xf3 = vpaddl.s8 d16, d16
11
- 0x20,0x02,0xf4,0xf3 = vpaddl.s16 d16, d16
12
- 0x20,0x02,0xf8,0xf3 = vpaddl.s32 d16, d16
13
- 0xa0,0x02,0xf0,0xf3 = vpaddl.u8 d16, d16
14
- 0xa0,0x02,0xf4,0xf3 = vpaddl.u16 d16, d16
15
- 0xa0,0x02,0xf8,0xf3 = vpaddl.u32 d16, d16
16
- 0x60,0x02,0xf0,0xf3 = vpaddl.s8 q8, q8
17
- 0x60,0x02,0xf4,0xf3 = vpaddl.s16 q8, q8
18
- 0x60,0x02,0xf8,0xf3 = vpaddl.s32 q8, q8
19
- 0xe0,0x02,0xf0,0xf3 = vpaddl.u8 q8, q8
20
- 0xe0,0x02,0xf4,0xf3 = vpaddl.u16 q8, q8
21
- 0xe0,0x02,0xf8,0xf3 = vpaddl.u32 q8, q8
22
- 0x21,0x06,0xf0,0xf3 = vpadal.s8 d16, d17
23
- 0x21,0x06,0xf4,0xf3 = vpadal.s16 d16, d17
24
- 0x21,0x06,0xf8,0xf3 = vpadal.s32 d16, d17
25
- 0xa1,0x06,0xf0,0xf3 = vpadal.u8 d16, d17
26
- 0xa1,0x06,0xf4,0xf3 = vpadal.u16 d16, d17
27
- 0xa1,0x06,0xf8,0xf3 = vpadal.u32 d16, d17
28
- 0x60,0x26,0xf0,0xf3 = vpadal.s8 q9, q8
29
- 0x60,0x26,0xf4,0xf3 = vpadal.s16 q9, q8
30
- 0x60,0x26,0xf8,0xf3 = vpadal.s32 q9, q8
31
- 0xe0,0x26,0xf0,0xf3 = vpadal.u8 q9, q8
32
- 0xe0,0x26,0xf4,0xf3 = vpadal.u16 q9, q8
33
- 0xe0,0x26,0xf8,0xf3 = vpadal.u32 q9, q8
34
- 0xb1,0x0a,0x40,0xf2 = vpmin.s8 d16, d16, d17
35
- 0xb1,0x0a,0x50,0xf2 = vpmin.s16 d16, d16, d17
36
- 0xb1,0x0a,0x60,0xf2 = vpmin.s32 d16, d16, d17
37
- 0xb1,0x0a,0x40,0xf3 = vpmin.u8 d16, d16, d17
38
- 0xb1,0x0a,0x50,0xf3 = vpmin.u16 d16, d16, d17
39
- 0xb1,0x0a,0x60,0xf3 = vpmin.u32 d16, d16, d17
40
- 0xa1,0x0f,0x60,0xf3 = vpmin.f32 d16, d16, d17
41
- 0xa1,0x0a,0x40,0xf2 = vpmax.s8 d16, d16, d17
42
- 0xa1,0x0a,0x50,0xf2 = vpmax.s16 d16, d16, d17
43
- 0xa1,0x0a,0x60,0xf2 = vpmax.s32 d16, d16, d17
44
- 0xa1,0x0a,0x40,0xf3 = vpmax.u8 d16, d16, d17
45
- 0xa1,0x0a,0x50,0xf3 = vpmax.u16 d16, d16, d17
46
- 0xa1,0x0a,0x60,0xf3 = vpmax.u32 d16, d16, d17
47
- 0xa1,0x0f,0x40,0xf3 = vpmax.f32 d16, d16, d17