crabstone 3.0.3 → 4.0.0

data/test/test_xcore.rb

@@ -1,100 +0,0 @@
-#!/usr/bin/env ruby
-
-# Library by Nguyen Anh Quynh
-# Original binding by Nguyen Anh Quynh and Tan Sheng Di
-# Additional binding work by Ben Nagy
-# (c) 2013 COSEINC. All Rights Reserved.
-
-require 'crabstone'
-require 'stringio'
-
-module TestXCore
-
-  XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7"
-
-  include Crabstone
-  include Crabstone::XCore
-
-  @platforms = [
-    Hash[
-      'arch' => ARCH_XCORE,
-      'mode' => MODE_BIG_ENDIAN,
-      'code' => XCORE_CODE,
-      'comment' => "XCore"
-    ],
-  ]
-
-  def self.uint32 i
-    Integer(i) & 0xffffffff
-  end
-
-  def self.print_detail cs, insn, sio
-    if insn.op_count > 0
-      sio.puts "\top_count: #{insn.op_count}"
-      insn.operands.each_with_index do |op,idx|
-        case op[:type]
-        when OP_REG
-          sio.puts "\t\toperands[#{idx}].type: REG = #{cs.reg_name(op.value)}"
-        when OP_IMM
-          sio.puts "\t\toperands[#{idx}].type: IMM = 0x#{self.uint32(op.value).to_s(16)}"
-        when OP_MEM
-          sio.puts "\t\toperands[#{idx}].type: MEM"
-          if op.value[:base].nonzero?
-            sio.puts "\t\t\toperands[#{idx}].mem.base: REG = %s" % cs.reg_name(op.value[:base])
-          end
-          if op.value[:index].nonzero?
-            sio.puts "\t\t\toperands[#{idx}].mem.index: REG = %s" % cs.reg_name(op.value[:index])
-          end
-          if op.value[:disp].nonzero?
-            sio.puts "\t\t\toperands[#{idx}].mem.disp: 0x%x" % (self.uint32(op.value[:disp]))
-          end
-          if op.value[:direct] != 1
-            sio.puts "\t\t\toperands[#{idx}].mem.direct: -1"
-          end
-        end
-      end
-    end
-    sio.puts
-  end
-
-  ours = StringIO.new
-
-  begin
-    cs    = Disassembler.new(0,0)
-    print "XCore Test: Capstone v #{cs.version.join('.')} - "
-  ensure
-    cs.close
-  end
-
-  #Test through all modes and architectures
-  @platforms.each do |p|
-    ours.puts "****************"
-    ours.puts "Platform: #{p['comment']}"
-    ours.puts "Code:#{p['code'].bytes.map {|b| "0x%.2x" % b}.join(' ')} "
-    ours.puts "Disasm:"
-
-    cs    = Disassembler.new(p['arch'], p['mode'])
-    cs.decomposer = true
-    cache = nil
-
-    cs.disasm(p['code'], 0x1000).each {|insn|
-      ours.puts "0x#{insn.address.to_s(16)}:\t#{insn.mnemonic}\t#{insn.op_str}"
-      self.print_detail(cs, insn, ours)
-      cache = insn.address + insn.size
-    }
-
-    cs.close
-    ours.printf("0x%x:\n", cache)
-    ours.puts
-  end
-
-  ours.rewind
-  theirs = File.binread(__FILE__ + ".SPEC")
-  if ours.read == theirs
-    puts "#{__FILE__}: PASS"
-  else
-    ours.rewind
-    puts ours.read
-    puts "#{__FILE__}: FAIL"
-  end
-end

data/test/test_xcore.rb.SPEC

@@ -1,75 +0,0 @@
-****************
-Platform: XCore
-Code:0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 0x09 0xfd 0xec 0xa7 
-Disasm:
-0x1000:	get	r11, ed
-	op_count: 2
-		operands[0].type: REG = r11
-		operands[1].type: REG = ed
-
-0x1002:	ldw	et, sp[4]
-	op_count: 2
-		operands[0].type: REG = et
-		operands[1].type: MEM
-			operands[1].mem.base: REG = sp
-			operands[1].mem.disp: 0x4
-
-0x1004:	setd	res[r3], r4
-	op_count: 2
-		operands[0].type: MEM
-			operands[0].mem.base: REG = r3
-		operands[1].type: REG = r4
-
-0x1006:	init	t[r2]:lr, r1
-	op_count: 2
-		operands[0].type: MEM
-			operands[0].mem.base: REG = r2
-			operands[0].mem.index: REG = lr
-		operands[1].type: REG = r1
-
-0x100a:	divu	r9, r1, r3
-	op_count: 3
-		operands[0].type: REG = r9
-		operands[1].type: REG = r1
-		operands[2].type: REG = r3
-
-0x100e:	lda16	r9, r3[-r11]
-	op_count: 2
-		operands[0].type: REG = r9
-		operands[1].type: MEM
-			operands[1].mem.base: REG = r3
-			operands[1].mem.index: REG = r11
-			operands[1].mem.direct: -1
-
-0x1012:	ldw	dp, dp[0x81c5]
-	op_count: 2
-		operands[0].type: REG = dp
-		operands[1].type: MEM
-			operands[1].mem.base: REG = dp
-			operands[1].mem.disp: 0x81c5
-
-0x1016:	lmul	r11, r0, r2, r5, r8, r10
-	op_count: 6
-		operands[0].type: REG = r11
-		operands[1].type: REG = r0
-		operands[2].type: REG = r2
-		operands[3].type: REG = r5
-		operands[4].type: REG = r8
-		operands[5].type: REG = r10
-
-0x101a:	add	r1, r2, r3
-	op_count: 3
-		operands[0].type: REG = r1
-		operands[1].type: REG = r2
-		operands[2].type: REG = r3
-
-0x101c:	ldaw	r8, r2[-9]
-	op_count: 2
-		operands[0].type: REG = r8
-		operands[1].type: MEM
-			operands[1].mem.base: REG = r2
-			operands[1].mem.disp: 0x9
-			operands[1].mem.direct: -1
-
-0x1020:
-