crabstone 3.0.3 → 4.0.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +45 -42
  3. data/README.md +16 -33
  4. data/lib/crabstone.rb +5 -557
  5. data/lib/crabstone/arch.rb +37 -0
  6. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  7. data/lib/crabstone/arch/3/arm64.rb +124 -0
  8. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  9. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  10. data/lib/crabstone/arch/3/mips.rb +57 -0
  11. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  12. data/lib/crabstone/arch/3/ppc.rb +73 -0
  13. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  14. data/lib/crabstone/arch/3/sparc.rb +60 -0
  15. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  16. data/lib/crabstone/arch/3/sysz.rb +67 -0
  17. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  18. data/lib/crabstone/arch/3/x86.rb +82 -0
  19. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  20. data/lib/crabstone/arch/3/xcore.rb +59 -0
  21. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  22. data/lib/crabstone/arch/4/arm.rb +110 -0
  23. data/lib/crabstone/arch/4/arm64.rb +125 -0
  24. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  25. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  26. data/lib/crabstone/arch/4/evm.rb +20 -0
  27. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  28. data/lib/crabstone/arch/4/m680x.rb +106 -0
  29. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  30. data/lib/crabstone/arch/4/m68k.rb +129 -0
  31. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  32. data/lib/crabstone/arch/4/mips.rb +57 -0
  33. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  34. data/lib/crabstone/arch/4/ppc.rb +73 -0
  35. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  36. data/lib/crabstone/arch/4/sparc.rb +60 -0
  37. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  38. data/lib/crabstone/arch/4/sysz.rb +67 -0
  39. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  40. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  41. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  42. data/lib/crabstone/arch/4/x86.rb +91 -0
  43. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  44. data/lib/crabstone/arch/4/xcore.rb +59 -0
  45. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  46. data/lib/crabstone/arch/extension.rb +27 -0
  47. data/lib/crabstone/arch/register.rb +36 -0
  48. data/lib/crabstone/binding.rb +60 -0
  49. data/lib/crabstone/binding/3/detail.rb +36 -0
  50. data/lib/crabstone/binding/3/instruction.rb +23 -0
  51. data/lib/crabstone/binding/4/detail.rb +40 -0
  52. data/lib/crabstone/binding/4/instruction.rb +23 -0
  53. data/lib/crabstone/binding/structs.rb +32 -0
  54. data/lib/crabstone/constants.rb +110 -0
  55. data/lib/crabstone/cs_version.rb +49 -0
  56. data/lib/crabstone/disassembler.rb +153 -0
  57. data/lib/crabstone/error.rb +60 -0
  58. data/lib/crabstone/instruction.rb +183 -0
  59. data/lib/crabstone/version.rb +5 -0
  60. metadata +128 -324
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
@@ -0,0 +1,59 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch/extension'
8
+ require_relative 'xcore_const'
9
+
10
+ module Crabstone
11
+ module XCore
12
+ class OperandMemory < FFI::Struct
13
+ layout(
14
+ :base, :uint8,
15
+ :index, :uint8,
16
+ :disp, :int,
17
+ :direct, :int
18
+ )
19
+ end
20
+
21
+ class OperandValue < FFI::Union
22
+ layout(
23
+ :reg, :uint,
24
+ :imm, :int,
25
+ :mem, OperandMemory
26
+ )
27
+ end
28
+
29
+ class Operand < FFI::Struct
30
+ layout(
31
+ :type, :uint,
32
+ :value, OperandValue
33
+ )
34
+
35
+ include Crabstone::Extension::Operand
36
+
37
+ def reg?
38
+ self[:type] == OP_REG
39
+ end
40
+
41
+ def imm?
42
+ self[:type] == OP_IMM
43
+ end
44
+
45
+ def mem?
46
+ self[:type] == OP_MEM
47
+ end
48
+ end
49
+
50
+ class Instruction < FFI::Struct
51
+ layout(
52
+ :op_count, :uint8,
53
+ :operands, [Operand, 8]
54
+ )
55
+
56
+ include Crabstone::Extension::Instruction
57
+ end
58
+ end
59
+ end
@@ -1,24 +1,16 @@
1
- # Library by Nguyen Anh Quynh
2
- # Original binding by Nguyen Anh Quynh and Tan Sheng Di
3
- # Additional binding work by Ben Nagy
4
- # (c) 2013 COSEINC. All Rights Reserved.
1
+ # frozen_string_literal: true
5
2
 
6
3
  # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
7
- # Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
8
- # 2015-05-02T13:24:01+12:00
4
+
5
+ require 'crabstone/arch/register'
9
6
 
10
7
  module Crabstone
11
8
  module XCore
12
-
13
- # Operand type for instruction's operands
14
-
15
9
  OP_INVALID = 0
16
10
  OP_REG = 1
17
11
  OP_IMM = 2
18
12
  OP_MEM = 3
19
-
20
- # XCore registers
21
-
13
+
22
14
  REG_INVALID = 0
23
15
  REG_CP = 1
24
16
  REG_DP = 2
@@ -36,8 +28,7 @@ module Crabstone
36
28
  REG_R9 = 14
37
29
  REG_R10 = 15
38
30
  REG_R11 = 16
39
-
40
- # pseudo registers
31
+
41
32
  REG_PC = 17
42
33
  REG_SCP = 18
43
34
  REG_SSR = 19
@@ -48,9 +39,7 @@ module Crabstone
48
39
  REG_KSP = 24
49
40
  REG_ID = 25
50
41
  REG_ENDING = 26
51
-
52
- # XCore instruction
53
-
42
+
54
43
  INS_INVALID = 0
55
44
  INS_ADD = 1
56
45
  INS_ANDNOT = 2
@@ -173,13 +162,12 @@ module Crabstone
173
162
  INS_XOR = 119
174
163
  INS_ZEXT = 120
175
164
  INS_ENDING = 121
176
-
177
- # Group of XCore instructions
178
-
165
+
179
166
  GRP_INVALID = 0
180
-
181
- # Generic groups
167
+
182
168
  GRP_JUMP = 1
183
169
  GRP_ENDING = 2
170
+
171
+ extend Register
184
172
  end
185
173
  end
@@ -0,0 +1,110 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch/extension'
8
+ require_relative 'arm_const'
9
+
10
+ module Crabstone
11
+ module ARM
12
+ class OperandShift < FFI::Struct
13
+ layout(
14
+ :type, :uint,
15
+ :value, :uint
16
+ )
17
+ end
18
+
19
+ class OperandMemory < FFI::Struct
20
+ layout(
21
+ :base, :uint,
22
+ :index, :uint,
23
+ :scale, :int,
24
+ :disp, :int,
25
+ :lshift, :int
26
+ )
27
+ end
28
+
29
+ class OperandValue < FFI::Union
30
+ layout(
31
+ :reg, :uint,
32
+ :imm, :int,
33
+ :fp, :double,
34
+ :mem, OperandMemory,
35
+ :setend, :int
36
+ )
37
+ end
38
+
39
+ class Operand < FFI::Struct
40
+ layout(
41
+ :vector_index, :int,
42
+ :shift, OperandShift,
43
+ :type, :uint,
44
+ :value, OperandValue,
45
+ :subtracted, :bool,
46
+ :access, :uint8,
47
+ :neon_lane, :int8
48
+ )
49
+
50
+ include Crabstone::Extension::Operand
51
+
52
+ def reg?
53
+ [
54
+ OP_REG,
55
+ OP_SYSREG
56
+ ].include?(self[:type])
57
+ end
58
+
59
+ def imm?
60
+ [
61
+ OP_IMM,
62
+ OP_CIMM,
63
+ OP_PIMM
64
+ ].include?(self[:type])
65
+ end
66
+
67
+ def mem?
68
+ self[:type] == OP_MEM
69
+ end
70
+
71
+ def fp?
72
+ self[:type] == OP_FP
73
+ end
74
+
75
+ def cimm?
76
+ self[:type] == OP_CIMM
77
+ end
78
+
79
+ def pimm?
80
+ self[:type] == OP_PIMM
81
+ end
82
+
83
+ def setend?
84
+ self[:type] == OP_SETEND
85
+ end
86
+
87
+ def sysreg?
88
+ self[:type] == OP_SYSREG
89
+ end
90
+ end
91
+
92
+ class Instruction < FFI::Struct
93
+ layout(
94
+ :usermode, :bool,
95
+ :vector_size, :int,
96
+ :vector_data, :int,
97
+ :cps_mode, :int,
98
+ :cps_flag, :int,
99
+ :cc, :uint,
100
+ :update_flags, :bool,
101
+ :writeback, :bool,
102
+ :mem_barrier, :int,
103
+ :op_count, :uint8,
104
+ :operands, [Operand, 36]
105
+ )
106
+
107
+ include Crabstone::Extension::Instruction
108
+ end
109
+ end
110
+ end
@@ -0,0 +1,125 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'ffi'
6
+
7
+ require 'crabstone/arch/extension'
8
+ require_relative 'arm64_const'
9
+
10
+ module Crabstone
11
+ module ARM64
12
+ class OperandShift < FFI::Struct
13
+ layout(
14
+ :type, :uint,
15
+ :value, :uint
16
+ )
17
+ end
18
+
19
+ class OperandMemory < FFI::Struct
20
+ layout(
21
+ :base, :uint,
22
+ :index, :uint,
23
+ :disp, :int
24
+ )
25
+ end
26
+
27
+ class OperandValue < FFI::Union
28
+ layout(
29
+ :reg, :uint,
30
+ :imm, :long,
31
+ :fp, :double,
32
+ :mem, OperandMemory,
33
+ :pstate, :int,
34
+ :sys, :uint,
35
+ :prefetch, :int,
36
+ :barrier, :int
37
+ )
38
+ end
39
+
40
+ class Operand < FFI::Struct
41
+ layout(
42
+ :vector_index, :int,
43
+ :vas, :int,
44
+ :vess, :int,
45
+ :shift, OperandShift,
46
+ :ext, :uint,
47
+ :type, :uint,
48
+ :value, OperandValue,
49
+ :access, :uint8
50
+ )
51
+ def shift?
52
+ self[:shift][:type] != SFT_INVALID
53
+ end
54
+
55
+ def ext?
56
+ self[:ext] != EXT_INVALID
57
+ end
58
+
59
+ include Crabstone::Extension::Operand
60
+
61
+ def reg?
62
+ [
63
+ OP_REG,
64
+ OP_REG_MRS,
65
+ OP_REG_MSR
66
+ ].include?(self[:type])
67
+ end
68
+
69
+ def imm?
70
+ [
71
+ OP_IMM,
72
+ OP_CIMM
73
+ ].include?(self[:type])
74
+ end
75
+
76
+ def mem?
77
+ self[:type] == OP_MEM
78
+ end
79
+
80
+ def fp?
81
+ self[:type] == OP_FP
82
+ end
83
+
84
+ def cimm?
85
+ self[:type] == OP_CIMM
86
+ end
87
+
88
+ def reg_mrs?
89
+ self[:type] == OP_REG_MRS
90
+ end
91
+
92
+ def reg_msr?
93
+ self[:type] == OP_REG_MSR
94
+ end
95
+
96
+ def pstate?
97
+ self[:type] == OP_PSTATE
98
+ end
99
+
100
+ def sys?
101
+ self[:type] == OP_SYS
102
+ end
103
+
104
+ def prefetch?
105
+ self[:type] == OP_PREFETCH
106
+ end
107
+
108
+ def barrier?
109
+ self[:type] == OP_BARRIER
110
+ end
111
+ end
112
+
113
+ class Instruction < FFI::Struct
114
+ layout(
115
+ :cc, :uint,
116
+ :update_flags, :bool,
117
+ :writeback, :bool,
118
+ :op_count, :uint8,
119
+ :operands, [Operand, 8]
120
+ )
121
+
122
+ include Crabstone::Extension::Instruction
123
+ end
124
+ end
125
+ end
@@ -0,0 +1,1016 @@
1
+ # frozen_string_literal: true
2
+
3
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
4
+
5
+ require 'crabstone/arch/register'
6
+
7
+ module Crabstone
8
+ module ARM64
9
+ SFT_INVALID = 0
10
+ SFT_LSL = 1
11
+ SFT_MSL = 2
12
+ SFT_LSR = 3
13
+ SFT_ASR = 4
14
+ SFT_ROR = 5
15
+
16
+ EXT_INVALID = 0
17
+ EXT_UXTB = 1
18
+ EXT_UXTH = 2
19
+ EXT_UXTW = 3
20
+ EXT_UXTX = 4
21
+ EXT_SXTB = 5
22
+ EXT_SXTH = 6
23
+ EXT_SXTW = 7
24
+ EXT_SXTX = 8
25
+
26
+ CC_INVALID = 0
27
+ CC_EQ = 1
28
+ CC_NE = 2
29
+ CC_HS = 3
30
+ CC_LO = 4
31
+ CC_MI = 5
32
+ CC_PL = 6
33
+ CC_VS = 7
34
+ CC_VC = 8
35
+ CC_HI = 9
36
+ CC_LS = 10
37
+ CC_GE = 11
38
+ CC_LT = 12
39
+ CC_GT = 13
40
+ CC_LE = 14
41
+ CC_AL = 15
42
+ CC_NV = 16
43
+
44
+ SYSREG_INVALID = 0
45
+ SYSREG_MDCCSR_EL0 = 0x9808
46
+ SYSREG_DBGDTRRX_EL0 = 0x9828
47
+ SYSREG_MDRAR_EL1 = 0x8080
48
+ SYSREG_OSLSR_EL1 = 0x808c
49
+ SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6
50
+ SYSREG_PMCEID0_EL0 = 0xdce6
51
+ SYSREG_PMCEID1_EL0 = 0xdce7
52
+ SYSREG_MIDR_EL1 = 0xc000
53
+ SYSREG_CCSIDR_EL1 = 0xc800
54
+ SYSREG_CLIDR_EL1 = 0xc801
55
+ SYSREG_CTR_EL0 = 0xd801
56
+ SYSREG_MPIDR_EL1 = 0xc005
57
+ SYSREG_REVIDR_EL1 = 0xc006
58
+ SYSREG_AIDR_EL1 = 0xc807
59
+ SYSREG_DCZID_EL0 = 0xd807
60
+ SYSREG_ID_PFR0_EL1 = 0xc008
61
+ SYSREG_ID_PFR1_EL1 = 0xc009
62
+ SYSREG_ID_DFR0_EL1 = 0xc00a
63
+ SYSREG_ID_AFR0_EL1 = 0xc00b
64
+ SYSREG_ID_MMFR0_EL1 = 0xc00c
65
+ SYSREG_ID_MMFR1_EL1 = 0xc00d
66
+ SYSREG_ID_MMFR2_EL1 = 0xc00e
67
+ SYSREG_ID_MMFR3_EL1 = 0xc00f
68
+ SYSREG_ID_ISAR0_EL1 = 0xc010
69
+ SYSREG_ID_ISAR1_EL1 = 0xc011
70
+ SYSREG_ID_ISAR2_EL1 = 0xc012
71
+ SYSREG_ID_ISAR3_EL1 = 0xc013
72
+ SYSREG_ID_ISAR4_EL1 = 0xc014
73
+ SYSREG_ID_ISAR5_EL1 = 0xc015
74
+ SYSREG_ID_A64PFR0_EL1 = 0xc020
75
+ SYSREG_ID_A64PFR1_EL1 = 0xc021
76
+ SYSREG_ID_A64DFR0_EL1 = 0xc028
77
+ SYSREG_ID_A64DFR1_EL1 = 0xc029
78
+ SYSREG_ID_A64AFR0_EL1 = 0xc02c
79
+ SYSREG_ID_A64AFR1_EL1 = 0xc02d
80
+ SYSREG_ID_A64ISAR0_EL1 = 0xc030
81
+ SYSREG_ID_A64ISAR1_EL1 = 0xc031
82
+ SYSREG_ID_A64MMFR0_EL1 = 0xc038
83
+ SYSREG_ID_A64MMFR1_EL1 = 0xc039
84
+ SYSREG_MVFR0_EL1 = 0xc018
85
+ SYSREG_MVFR1_EL1 = 0xc019
86
+ SYSREG_MVFR2_EL1 = 0xc01a
87
+ SYSREG_RVBAR_EL1 = 0xc601
88
+ SYSREG_RVBAR_EL2 = 0xe601
89
+ SYSREG_RVBAR_EL3 = 0xf601
90
+ SYSREG_ISR_EL1 = 0xc608
91
+ SYSREG_CNTPCT_EL0 = 0xdf01
92
+ SYSREG_CNTVCT_EL0 = 0xdf02
93
+ SYSREG_TRCSTATR = 0x8818
94
+ SYSREG_TRCIDR8 = 0x8806
95
+ SYSREG_TRCIDR9 = 0x880e
96
+ SYSREG_TRCIDR10 = 0x8816
97
+ SYSREG_TRCIDR11 = 0x881e
98
+ SYSREG_TRCIDR12 = 0x8826
99
+ SYSREG_TRCIDR13 = 0x882e
100
+ SYSREG_TRCIDR0 = 0x8847
101
+ SYSREG_TRCIDR1 = 0x884f
102
+ SYSREG_TRCIDR2 = 0x8857
103
+ SYSREG_TRCIDR3 = 0x885f
104
+ SYSREG_TRCIDR4 = 0x8867
105
+ SYSREG_TRCIDR5 = 0x886f
106
+ SYSREG_TRCIDR6 = 0x8877
107
+ SYSREG_TRCIDR7 = 0x887f
108
+ SYSREG_TRCOSLSR = 0x888c
109
+ SYSREG_TRCPDSR = 0x88ac
110
+ SYSREG_TRCDEVAFF0 = 0x8bd6
111
+ SYSREG_TRCDEVAFF1 = 0x8bde
112
+ SYSREG_TRCLSR = 0x8bee
113
+ SYSREG_TRCAUTHSTATUS = 0x8bf6
114
+ SYSREG_TRCDEVARCH = 0x8bfe
115
+ SYSREG_TRCDEVID = 0x8b97
116
+ SYSREG_TRCDEVTYPE = 0x8b9f
117
+ SYSREG_TRCPIDR4 = 0x8ba7
118
+ SYSREG_TRCPIDR5 = 0x8baf
119
+ SYSREG_TRCPIDR6 = 0x8bb7
120
+ SYSREG_TRCPIDR7 = 0x8bbf
121
+ SYSREG_TRCPIDR0 = 0x8bc7
122
+ SYSREG_TRCPIDR1 = 0x8bcf
123
+ SYSREG_TRCPIDR2 = 0x8bd7
124
+ SYSREG_TRCPIDR3 = 0x8bdf
125
+ SYSREG_TRCCIDR0 = 0x8be7
126
+ SYSREG_TRCCIDR1 = 0x8bef
127
+ SYSREG_TRCCIDR2 = 0x8bf7
128
+ SYSREG_TRCCIDR3 = 0x8bff
129
+ SYSREG_ICC_IAR1_EL1 = 0xc660
130
+ SYSREG_ICC_IAR0_EL1 = 0xc640
131
+ SYSREG_ICC_HPPIR1_EL1 = 0xc662
132
+ SYSREG_ICC_HPPIR0_EL1 = 0xc642
133
+ SYSREG_ICC_RPR_EL1 = 0xc65b
134
+ SYSREG_ICH_VTR_EL2 = 0xe659
135
+ SYSREG_ICH_EISR_EL2 = 0xe65b
136
+ SYSREG_ICH_ELSR_EL2 = 0xe65d
137
+ SYSREG_DBGDTRTX_EL0 = 0x9828
138
+ SYSREG_OSLAR_EL1 = 0x8084
139
+ SYSREG_PMSWINC_EL0 = 0xdce4
140
+ SYSREG_TRCOSLAR = 0x8884
141
+ SYSREG_TRCLAR = 0x8be6
142
+ SYSREG_ICC_EOIR1_EL1 = 0xc661
143
+ SYSREG_ICC_EOIR0_EL1 = 0xc641
144
+ SYSREG_ICC_DIR_EL1 = 0xc659
145
+ SYSREG_ICC_SGI1R_EL1 = 0xc65d
146
+ SYSREG_ICC_ASGI1R_EL1 = 0xc65e
147
+ SYSREG_ICC_SGI0R_EL1 = 0xc65f
148
+
149
+ PSTATE_INVALID = 0
150
+ PSTATE_SPSEL = 0x05
151
+ PSTATE_DAIFSET = 0x1e
152
+ PSTATE_DAIFCLR = 0x1f
153
+
154
+ VAS_INVALID = 0
155
+ VAS_8B = 1
156
+ VAS_16B = 2
157
+ VAS_4H = 3
158
+ VAS_8H = 4
159
+ VAS_2S = 5
160
+ VAS_4S = 6
161
+ VAS_1D = 7
162
+ VAS_2D = 8
163
+ VAS_1Q = 9
164
+
165
+ VESS_INVALID = 0
166
+ VESS_B = 1
167
+ VESS_H = 2
168
+ VESS_S = 3
169
+ VESS_D = 4
170
+
171
+ BARRIER_INVALID = 0
172
+ BARRIER_OSHLD = 0x1
173
+ BARRIER_OSHST = 0x2
174
+ BARRIER_OSH = 0x3
175
+ BARRIER_NSHLD = 0x5
176
+ BARRIER_NSHST = 0x6
177
+ BARRIER_NSH = 0x7
178
+ BARRIER_ISHLD = 0x9
179
+ BARRIER_ISHST = 0xa
180
+ BARRIER_ISH = 0xb
181
+ BARRIER_LD = 0xd
182
+ BARRIER_ST = 0xe
183
+ BARRIER_SY = 0xf
184
+
185
+ OP_INVALID = 0
186
+ OP_REG = 1
187
+ OP_IMM = 2
188
+ OP_MEM = 3
189
+ OP_FP = 4
190
+ OP_CIMM = 64
191
+ OP_REG_MRS = 65
192
+ OP_REG_MSR = 66
193
+ OP_PSTATE = 67
194
+ OP_SYS = 68
195
+ OP_PREFETCH = 69
196
+ OP_BARRIER = 70
197
+
198
+ TLBI_INVALID = 0
199
+ TLBI_VMALLE1IS = 1
200
+ TLBI_VAE1IS = 2
201
+ TLBI_ASIDE1IS = 3
202
+ TLBI_VAAE1IS = 4
203
+ TLBI_VALE1IS = 5
204
+ TLBI_VAALE1IS = 6
205
+ TLBI_ALLE2IS = 7
206
+ TLBI_VAE2IS = 8
207
+ TLBI_ALLE1IS = 9
208
+ TLBI_VALE2IS = 10
209
+ TLBI_VMALLS12E1IS = 11
210
+ TLBI_ALLE3IS = 12
211
+ TLBI_VAE3IS = 13
212
+ TLBI_VALE3IS = 14
213
+ TLBI_IPAS2E1IS = 15
214
+ TLBI_IPAS2LE1IS = 16
215
+ TLBI_IPAS2E1 = 17
216
+ TLBI_IPAS2LE1 = 18
217
+ TLBI_VMALLE1 = 19
218
+ TLBI_VAE1 = 20
219
+ TLBI_ASIDE1 = 21
220
+ TLBI_VAAE1 = 22
221
+ TLBI_VALE1 = 23
222
+ TLBI_VAALE1 = 24
223
+ TLBI_ALLE2 = 25
224
+ TLBI_VAE2 = 26
225
+ TLBI_ALLE1 = 27
226
+ TLBI_VALE2 = 28
227
+ TLBI_VMALLS12E1 = 29
228
+ TLBI_ALLE3 = 30
229
+ TLBI_VAE3 = 31
230
+ TLBI_VALE3 = 32
231
+ AT_S1E1R = 33
232
+ AT_S1E1W = 34
233
+ AT_S1E0R = 35
234
+ AT_S1E0W = 36
235
+ AT_S1E2R = 37
236
+ AT_S1E2W = 38
237
+ AT_S12E1R = 39
238
+ AT_S12E1W = 40
239
+ AT_S12E0R = 41
240
+ AT_S12E0W = 42
241
+ AT_S1E3R = 43
242
+ AT_S1E3W = 44
243
+
244
+ DC_INVALID = 0
245
+ DC_ZVA = 1
246
+ DC_IVAC = 2
247
+ DC_ISW = 3
248
+ DC_CVAC = 4
249
+ DC_CSW = 5
250
+ DC_CVAU = 6
251
+ DC_CIVAC = 7
252
+ DC_CISW = 8
253
+
254
+ IC_INVALID = 0
255
+ IC_IALLUIS = 1
256
+ IC_IALLU = 2
257
+ IC_IVAU = 3
258
+
259
+ PRFM_INVALID = 0
260
+ PRFM_PLDL1KEEP = 0x00 + 1
261
+ PRFM_PLDL1STRM = 0x01 + 1
262
+ PRFM_PLDL2KEEP = 0x02 + 1
263
+ PRFM_PLDL2STRM = 0x03 + 1
264
+ PRFM_PLDL3KEEP = 0x04 + 1
265
+ PRFM_PLDL3STRM = 0x05 + 1
266
+ PRFM_PLIL1KEEP = 0x08 + 1
267
+ PRFM_PLIL1STRM = 0x09 + 1
268
+ PRFM_PLIL2KEEP = 0x0a + 1
269
+ PRFM_PLIL2STRM = 0x0b + 1
270
+ PRFM_PLIL3KEEP = 0x0c + 1
271
+ PRFM_PLIL3STRM = 0x0d + 1
272
+ PRFM_PSTL1KEEP = 0x10 + 1
273
+ PRFM_PSTL1STRM = 0x11 + 1
274
+ PRFM_PSTL2KEEP = 0x12 + 1
275
+ PRFM_PSTL2STRM = 0x13 + 1
276
+ PRFM_PSTL3KEEP = 0x14 + 1
277
+ PRFM_PSTL3STRM = 0x15 + 1
278
+
279
+ REG_INVALID = 0
280
+ REG_X29 = 1
281
+ REG_X30 = 2
282
+ REG_NZCV = 3
283
+ REG_SP = 4
284
+ REG_WSP = 5
285
+ REG_WZR = 6
286
+ REG_XZR = 7
287
+ REG_B0 = 8
288
+ REG_B1 = 9
289
+ REG_B2 = 10
290
+ REG_B3 = 11
291
+ REG_B4 = 12
292
+ REG_B5 = 13
293
+ REG_B6 = 14
294
+ REG_B7 = 15
295
+ REG_B8 = 16
296
+ REG_B9 = 17
297
+ REG_B10 = 18
298
+ REG_B11 = 19
299
+ REG_B12 = 20
300
+ REG_B13 = 21
301
+ REG_B14 = 22
302
+ REG_B15 = 23
303
+ REG_B16 = 24
304
+ REG_B17 = 25
305
+ REG_B18 = 26
306
+ REG_B19 = 27
307
+ REG_B20 = 28
308
+ REG_B21 = 29
309
+ REG_B22 = 30
310
+ REG_B23 = 31
311
+ REG_B24 = 32
312
+ REG_B25 = 33
313
+ REG_B26 = 34
314
+ REG_B27 = 35
315
+ REG_B28 = 36
316
+ REG_B29 = 37
317
+ REG_B30 = 38
318
+ REG_B31 = 39
319
+ REG_D0 = 40
320
+ REG_D1 = 41
321
+ REG_D2 = 42
322
+ REG_D3 = 43
323
+ REG_D4 = 44
324
+ REG_D5 = 45
325
+ REG_D6 = 46
326
+ REG_D7 = 47
327
+ REG_D8 = 48
328
+ REG_D9 = 49
329
+ REG_D10 = 50
330
+ REG_D11 = 51
331
+ REG_D12 = 52
332
+ REG_D13 = 53
333
+ REG_D14 = 54
334
+ REG_D15 = 55
335
+ REG_D16 = 56
336
+ REG_D17 = 57
337
+ REG_D18 = 58
338
+ REG_D19 = 59
339
+ REG_D20 = 60
340
+ REG_D21 = 61
341
+ REG_D22 = 62
342
+ REG_D23 = 63
343
+ REG_D24 = 64
344
+ REG_D25 = 65
345
+ REG_D26 = 66
346
+ REG_D27 = 67
347
+ REG_D28 = 68
348
+ REG_D29 = 69
349
+ REG_D30 = 70
350
+ REG_D31 = 71
351
+ REG_H0 = 72
352
+ REG_H1 = 73
353
+ REG_H2 = 74
354
+ REG_H3 = 75
355
+ REG_H4 = 76
356
+ REG_H5 = 77
357
+ REG_H6 = 78
358
+ REG_H7 = 79
359
+ REG_H8 = 80
360
+ REG_H9 = 81
361
+ REG_H10 = 82
362
+ REG_H11 = 83
363
+ REG_H12 = 84
364
+ REG_H13 = 85
365
+ REG_H14 = 86
366
+ REG_H15 = 87
367
+ REG_H16 = 88
368
+ REG_H17 = 89
369
+ REG_H18 = 90
370
+ REG_H19 = 91
371
+ REG_H20 = 92
372
+ REG_H21 = 93
373
+ REG_H22 = 94
374
+ REG_H23 = 95
375
+ REG_H24 = 96
376
+ REG_H25 = 97
377
+ REG_H26 = 98
378
+ REG_H27 = 99
379
+ REG_H28 = 100
380
+ REG_H29 = 101
381
+ REG_H30 = 102
382
+ REG_H31 = 103
383
+ REG_Q0 = 104
384
+ REG_Q1 = 105
385
+ REG_Q2 = 106
386
+ REG_Q3 = 107
387
+ REG_Q4 = 108
388
+ REG_Q5 = 109
389
+ REG_Q6 = 110
390
+ REG_Q7 = 111
391
+ REG_Q8 = 112
392
+ REG_Q9 = 113
393
+ REG_Q10 = 114
394
+ REG_Q11 = 115
395
+ REG_Q12 = 116
396
+ REG_Q13 = 117
397
+ REG_Q14 = 118
398
+ REG_Q15 = 119
399
+ REG_Q16 = 120
400
+ REG_Q17 = 121
401
+ REG_Q18 = 122
402
+ REG_Q19 = 123
403
+ REG_Q20 = 124
404
+ REG_Q21 = 125
405
+ REG_Q22 = 126
406
+ REG_Q23 = 127
407
+ REG_Q24 = 128
408
+ REG_Q25 = 129
409
+ REG_Q26 = 130
410
+ REG_Q27 = 131
411
+ REG_Q28 = 132
412
+ REG_Q29 = 133
413
+ REG_Q30 = 134
414
+ REG_Q31 = 135
415
+ REG_S0 = 136
416
+ REG_S1 = 137
417
+ REG_S2 = 138
418
+ REG_S3 = 139
419
+ REG_S4 = 140
420
+ REG_S5 = 141
421
+ REG_S6 = 142
422
+ REG_S7 = 143
423
+ REG_S8 = 144
424
+ REG_S9 = 145
425
+ REG_S10 = 146
426
+ REG_S11 = 147
427
+ REG_S12 = 148
428
+ REG_S13 = 149
429
+ REG_S14 = 150
430
+ REG_S15 = 151
431
+ REG_S16 = 152
432
+ REG_S17 = 153
433
+ REG_S18 = 154
434
+ REG_S19 = 155
435
+ REG_S20 = 156
436
+ REG_S21 = 157
437
+ REG_S22 = 158
438
+ REG_S23 = 159
439
+ REG_S24 = 160
440
+ REG_S25 = 161
441
+ REG_S26 = 162
442
+ REG_S27 = 163
443
+ REG_S28 = 164
444
+ REG_S29 = 165
445
+ REG_S30 = 166
446
+ REG_S31 = 167
447
+ REG_W0 = 168
448
+ REG_W1 = 169
449
+ REG_W2 = 170
450
+ REG_W3 = 171
451
+ REG_W4 = 172
452
+ REG_W5 = 173
453
+ REG_W6 = 174
454
+ REG_W7 = 175
455
+ REG_W8 = 176
456
+ REG_W9 = 177
457
+ REG_W10 = 178
458
+ REG_W11 = 179
459
+ REG_W12 = 180
460
+ REG_W13 = 181
461
+ REG_W14 = 182
462
+ REG_W15 = 183
463
+ REG_W16 = 184
464
+ REG_W17 = 185
465
+ REG_W18 = 186
466
+ REG_W19 = 187
467
+ REG_W20 = 188
468
+ REG_W21 = 189
469
+ REG_W22 = 190
470
+ REG_W23 = 191
471
+ REG_W24 = 192
472
+ REG_W25 = 193
473
+ REG_W26 = 194
474
+ REG_W27 = 195
475
+ REG_W28 = 196
476
+ REG_W29 = 197
477
+ REG_W30 = 198
478
+ REG_X0 = 199
479
+ REG_X1 = 200
480
+ REG_X2 = 201
481
+ REG_X3 = 202
482
+ REG_X4 = 203
483
+ REG_X5 = 204
484
+ REG_X6 = 205
485
+ REG_X7 = 206
486
+ REG_X8 = 207
487
+ REG_X9 = 208
488
+ REG_X10 = 209
489
+ REG_X11 = 210
490
+ REG_X12 = 211
491
+ REG_X13 = 212
492
+ REG_X14 = 213
493
+ REG_X15 = 214
494
+ REG_X16 = 215
495
+ REG_X17 = 216
496
+ REG_X18 = 217
497
+ REG_X19 = 218
498
+ REG_X20 = 219
499
+ REG_X21 = 220
500
+ REG_X22 = 221
501
+ REG_X23 = 222
502
+ REG_X24 = 223
503
+ REG_X25 = 224
504
+ REG_X26 = 225
505
+ REG_X27 = 226
506
+ REG_X28 = 227
507
+ REG_V0 = 228
508
+ REG_V1 = 229
509
+ REG_V2 = 230
510
+ REG_V3 = 231
511
+ REG_V4 = 232
512
+ REG_V5 = 233
513
+ REG_V6 = 234
514
+ REG_V7 = 235
515
+ REG_V8 = 236
516
+ REG_V9 = 237
517
+ REG_V10 = 238
518
+ REG_V11 = 239
519
+ REG_V12 = 240
520
+ REG_V13 = 241
521
+ REG_V14 = 242
522
+ REG_V15 = 243
523
+ REG_V16 = 244
524
+ REG_V17 = 245
525
+ REG_V18 = 246
526
+ REG_V19 = 247
527
+ REG_V20 = 248
528
+ REG_V21 = 249
529
+ REG_V22 = 250
530
+ REG_V23 = 251
531
+ REG_V24 = 252
532
+ REG_V25 = 253
533
+ REG_V26 = 254
534
+ REG_V27 = 255
535
+ REG_V28 = 256
536
+ REG_V29 = 257
537
+ REG_V30 = 258
538
+ REG_V31 = 259
539
+ REG_ENDING = 260
540
+ REG_IP0 = REG_X16
541
+ REG_IP1 = REG_X17
542
+ REG_FP = REG_X29
543
+ REG_LR = REG_X30
544
+
545
+ INS_INVALID = 0
546
+ INS_ABS = 1
547
+ INS_ADC = 2
548
+ INS_ADDHN = 3
549
+ INS_ADDHN2 = 4
550
+ INS_ADDP = 5
551
+ INS_ADD = 6
552
+ INS_ADDV = 7
553
+ INS_ADR = 8
554
+ INS_ADRP = 9
555
+ INS_AESD = 10
556
+ INS_AESE = 11
557
+ INS_AESIMC = 12
558
+ INS_AESMC = 13
559
+ INS_AND = 14
560
+ INS_ASR = 15
561
+ INS_B = 16
562
+ INS_BFM = 17
563
+ INS_BIC = 18
564
+ INS_BIF = 19
565
+ INS_BIT = 20
566
+ INS_BL = 21
567
+ INS_BLR = 22
568
+ INS_BR = 23
569
+ INS_BRK = 24
570
+ INS_BSL = 25
571
+ INS_CBNZ = 26
572
+ INS_CBZ = 27
573
+ INS_CCMN = 28
574
+ INS_CCMP = 29
575
+ INS_CLREX = 30
576
+ INS_CLS = 31
577
+ INS_CLZ = 32
578
+ INS_CMEQ = 33
579
+ INS_CMGE = 34
580
+ INS_CMGT = 35
581
+ INS_CMHI = 36
582
+ INS_CMHS = 37
583
+ INS_CMLE = 38
584
+ INS_CMLT = 39
585
+ INS_CMTST = 40
586
+ INS_CNT = 41
587
+ INS_MOV = 42
588
+ INS_CRC32B = 43
589
+ INS_CRC32CB = 44
590
+ INS_CRC32CH = 45
591
+ INS_CRC32CW = 46
592
+ INS_CRC32CX = 47
593
+ INS_CRC32H = 48
594
+ INS_CRC32W = 49
595
+ INS_CRC32X = 50
596
+ INS_CSEL = 51
597
+ INS_CSINC = 52
598
+ INS_CSINV = 53
599
+ INS_CSNEG = 54
600
+ INS_DCPS1 = 55
601
+ INS_DCPS2 = 56
602
+ INS_DCPS3 = 57
603
+ INS_DMB = 58
604
+ INS_DRPS = 59
605
+ INS_DSB = 60
606
+ INS_DUP = 61
607
+ INS_EON = 62
608
+ INS_EOR = 63
609
+ INS_ERET = 64
610
+ INS_EXTR = 65
611
+ INS_EXT = 66
612
+ INS_FABD = 67
613
+ INS_FABS = 68
614
+ INS_FACGE = 69
615
+ INS_FACGT = 70
616
+ INS_FADD = 71
617
+ INS_FADDP = 72
618
+ INS_FCCMP = 73
619
+ INS_FCCMPE = 74
620
+ INS_FCMEQ = 75
621
+ INS_FCMGE = 76
622
+ INS_FCMGT = 77
623
+ INS_FCMLE = 78
624
+ INS_FCMLT = 79
625
+ INS_FCMP = 80
626
+ INS_FCMPE = 81
627
+ INS_FCSEL = 82
628
+ INS_FCVTAS = 83
629
+ INS_FCVTAU = 84
630
+ INS_FCVT = 85
631
+ INS_FCVTL = 86
632
+ INS_FCVTL2 = 87
633
+ INS_FCVTMS = 88
634
+ INS_FCVTMU = 89
635
+ INS_FCVTNS = 90
636
+ INS_FCVTNU = 91
637
+ INS_FCVTN = 92
638
+ INS_FCVTN2 = 93
639
+ INS_FCVTPS = 94
640
+ INS_FCVTPU = 95
641
+ INS_FCVTXN = 96
642
+ INS_FCVTXN2 = 97
643
+ INS_FCVTZS = 98
644
+ INS_FCVTZU = 99
645
+ INS_FDIV = 100
646
+ INS_FMADD = 101
647
+ INS_FMAX = 102
648
+ INS_FMAXNM = 103
649
+ INS_FMAXNMP = 104
650
+ INS_FMAXNMV = 105
651
+ INS_FMAXP = 106
652
+ INS_FMAXV = 107
653
+ INS_FMIN = 108
654
+ INS_FMINNM = 109
655
+ INS_FMINNMP = 110
656
+ INS_FMINNMV = 111
657
+ INS_FMINP = 112
658
+ INS_FMINV = 113
659
+ INS_FMLA = 114
660
+ INS_FMLS = 115
661
+ INS_FMOV = 116
662
+ INS_FMSUB = 117
663
+ INS_FMUL = 118
664
+ INS_FMULX = 119
665
+ INS_FNEG = 120
666
+ INS_FNMADD = 121
667
+ INS_FNMSUB = 122
668
+ INS_FNMUL = 123
669
+ INS_FRECPE = 124
670
+ INS_FRECPS = 125
671
+ INS_FRECPX = 126
672
+ INS_FRINTA = 127
673
+ INS_FRINTI = 128
674
+ INS_FRINTM = 129
675
+ INS_FRINTN = 130
676
+ INS_FRINTP = 131
677
+ INS_FRINTX = 132
678
+ INS_FRINTZ = 133
679
+ INS_FRSQRTE = 134
680
+ INS_FRSQRTS = 135
681
+ INS_FSQRT = 136
682
+ INS_FSUB = 137
683
+ INS_HINT = 138
684
+ INS_HLT = 139
685
+ INS_HVC = 140
686
+ INS_INS = 141
687
+ INS_ISB = 142
688
+ INS_LD1 = 143
689
+ INS_LD1R = 144
690
+ INS_LD2R = 145
691
+ INS_LD2 = 146
692
+ INS_LD3R = 147
693
+ INS_LD3 = 148
694
+ INS_LD4 = 149
695
+ INS_LD4R = 150
696
+ INS_LDARB = 151
697
+ INS_LDARH = 152
698
+ INS_LDAR = 153
699
+ INS_LDAXP = 154
700
+ INS_LDAXRB = 155
701
+ INS_LDAXRH = 156
702
+ INS_LDAXR = 157
703
+ INS_LDNP = 158
704
+ INS_LDP = 159
705
+ INS_LDPSW = 160
706
+ INS_LDRB = 161
707
+ INS_LDR = 162
708
+ INS_LDRH = 163
709
+ INS_LDRSB = 164
710
+ INS_LDRSH = 165
711
+ INS_LDRSW = 166
712
+ INS_LDTRB = 167
713
+ INS_LDTRH = 168
714
+ INS_LDTRSB = 169
715
+ INS_LDTRSH = 170
716
+ INS_LDTRSW = 171
717
+ INS_LDTR = 172
718
+ INS_LDURB = 173
719
+ INS_LDUR = 174
720
+ INS_LDURH = 175
721
+ INS_LDURSB = 176
722
+ INS_LDURSH = 177
723
+ INS_LDURSW = 178
724
+ INS_LDXP = 179
725
+ INS_LDXRB = 180
726
+ INS_LDXRH = 181
727
+ INS_LDXR = 182
728
+ INS_LSL = 183
729
+ INS_LSR = 184
730
+ INS_MADD = 185
731
+ INS_MLA = 186
732
+ INS_MLS = 187
733
+ INS_MOVI = 188
734
+ INS_MOVK = 189
735
+ INS_MOVN = 190
736
+ INS_MOVZ = 191
737
+ INS_MRS = 192
738
+ INS_MSR = 193
739
+ INS_MSUB = 194
740
+ INS_MUL = 195
741
+ INS_MVNI = 196
742
+ INS_NEG = 197
743
+ INS_NOT = 198
744
+ INS_ORN = 199
745
+ INS_ORR = 200
746
+ INS_PMULL2 = 201
747
+ INS_PMULL = 202
748
+ INS_PMUL = 203
749
+ INS_PRFM = 204
750
+ INS_PRFUM = 205
751
+ INS_RADDHN = 206
752
+ INS_RADDHN2 = 207
753
+ INS_RBIT = 208
754
+ INS_RET = 209
755
+ INS_REV16 = 210
756
+ INS_REV32 = 211
757
+ INS_REV64 = 212
758
+ INS_REV = 213
759
+ INS_ROR = 214
760
+ INS_RSHRN2 = 215
761
+ INS_RSHRN = 216
762
+ INS_RSUBHN = 217
763
+ INS_RSUBHN2 = 218
764
+ INS_SABAL2 = 219
765
+ INS_SABAL = 220
766
+ INS_SABA = 221
767
+ INS_SABDL2 = 222
768
+ INS_SABDL = 223
769
+ INS_SABD = 224
770
+ INS_SADALP = 225
771
+ INS_SADDLP = 226
772
+ INS_SADDLV = 227
773
+ INS_SADDL2 = 228
774
+ INS_SADDL = 229
775
+ INS_SADDW2 = 230
776
+ INS_SADDW = 231
777
+ INS_SBC = 232
778
+ INS_SBFM = 233
779
+ INS_SCVTF = 234
780
+ INS_SDIV = 235
781
+ INS_SHA1C = 236
782
+ INS_SHA1H = 237
783
+ INS_SHA1M = 238
784
+ INS_SHA1P = 239
785
+ INS_SHA1SU0 = 240
786
+ INS_SHA1SU1 = 241
787
+ INS_SHA256H2 = 242
788
+ INS_SHA256H = 243
789
+ INS_SHA256SU0 = 244
790
+ INS_SHA256SU1 = 245
791
+ INS_SHADD = 246
792
+ INS_SHLL2 = 247
793
+ INS_SHLL = 248
794
+ INS_SHL = 249
795
+ INS_SHRN2 = 250
796
+ INS_SHRN = 251
797
+ INS_SHSUB = 252
798
+ INS_SLI = 253
799
+ INS_SMADDL = 254
800
+ INS_SMAXP = 255
801
+ INS_SMAXV = 256
802
+ INS_SMAX = 257
803
+ INS_SMC = 258
804
+ INS_SMINP = 259
805
+ INS_SMINV = 260
806
+ INS_SMIN = 261
807
+ INS_SMLAL2 = 262
808
+ INS_SMLAL = 263
809
+ INS_SMLSL2 = 264
810
+ INS_SMLSL = 265
811
+ INS_SMOV = 266
812
+ INS_SMSUBL = 267
813
+ INS_SMULH = 268
814
+ INS_SMULL2 = 269
815
+ INS_SMULL = 270
816
+ INS_SQABS = 271
817
+ INS_SQADD = 272
818
+ INS_SQDMLAL = 273
819
+ INS_SQDMLAL2 = 274
820
+ INS_SQDMLSL = 275
821
+ INS_SQDMLSL2 = 276
822
+ INS_SQDMULH = 277
823
+ INS_SQDMULL = 278
824
+ INS_SQDMULL2 = 279
825
+ INS_SQNEG = 280
826
+ INS_SQRDMULH = 281
827
+ INS_SQRSHL = 282
828
+ INS_SQRSHRN = 283
829
+ INS_SQRSHRN2 = 284
830
+ INS_SQRSHRUN = 285
831
+ INS_SQRSHRUN2 = 286
832
+ INS_SQSHLU = 287
833
+ INS_SQSHL = 288
834
+ INS_SQSHRN = 289
835
+ INS_SQSHRN2 = 290
836
+ INS_SQSHRUN = 291
837
+ INS_SQSHRUN2 = 292
838
+ INS_SQSUB = 293
839
+ INS_SQXTN2 = 294
840
+ INS_SQXTN = 295
841
+ INS_SQXTUN2 = 296
842
+ INS_SQXTUN = 297
843
+ INS_SRHADD = 298
844
+ INS_SRI = 299
845
+ INS_SRSHL = 300
846
+ INS_SRSHR = 301
847
+ INS_SRSRA = 302
848
+ INS_SSHLL2 = 303
849
+ INS_SSHLL = 304
850
+ INS_SSHL = 305
851
+ INS_SSHR = 306
852
+ INS_SSRA = 307
853
+ INS_SSUBL2 = 308
854
+ INS_SSUBL = 309
855
+ INS_SSUBW2 = 310
856
+ INS_SSUBW = 311
857
+ INS_ST1 = 312
858
+ INS_ST2 = 313
859
+ INS_ST3 = 314
860
+ INS_ST4 = 315
861
+ INS_STLRB = 316
862
+ INS_STLRH = 317
863
+ INS_STLR = 318
864
+ INS_STLXP = 319
865
+ INS_STLXRB = 320
866
+ INS_STLXRH = 321
867
+ INS_STLXR = 322
868
+ INS_STNP = 323
869
+ INS_STP = 324
870
+ INS_STRB = 325
871
+ INS_STR = 326
872
+ INS_STRH = 327
873
+ INS_STTRB = 328
874
+ INS_STTRH = 329
875
+ INS_STTR = 330
876
+ INS_STURB = 331
877
+ INS_STUR = 332
878
+ INS_STURH = 333
879
+ INS_STXP = 334
880
+ INS_STXRB = 335
881
+ INS_STXRH = 336
882
+ INS_STXR = 337
883
+ INS_SUBHN = 338
884
+ INS_SUBHN2 = 339
885
+ INS_SUB = 340
886
+ INS_SUQADD = 341
887
+ INS_SVC = 342
888
+ INS_SYSL = 343
889
+ INS_SYS = 344
890
+ INS_TBL = 345
891
+ INS_TBNZ = 346
892
+ INS_TBX = 347
893
+ INS_TBZ = 348
894
+ INS_TRN1 = 349
895
+ INS_TRN2 = 350
896
+ INS_UABAL2 = 351
897
+ INS_UABAL = 352
898
+ INS_UABA = 353
899
+ INS_UABDL2 = 354
900
+ INS_UABDL = 355
901
+ INS_UABD = 356
902
+ INS_UADALP = 357
903
+ INS_UADDLP = 358
904
+ INS_UADDLV = 359
905
+ INS_UADDL2 = 360
906
+ INS_UADDL = 361
907
+ INS_UADDW2 = 362
908
+ INS_UADDW = 363
909
+ INS_UBFM = 364
910
+ INS_UCVTF = 365
911
+ INS_UDIV = 366
912
+ INS_UHADD = 367
913
+ INS_UHSUB = 368
914
+ INS_UMADDL = 369
915
+ INS_UMAXP = 370
916
+ INS_UMAXV = 371
917
+ INS_UMAX = 372
918
+ INS_UMINP = 373
919
+ INS_UMINV = 374
920
+ INS_UMIN = 375
921
+ INS_UMLAL2 = 376
922
+ INS_UMLAL = 377
923
+ INS_UMLSL2 = 378
924
+ INS_UMLSL = 379
925
+ INS_UMOV = 380
926
+ INS_UMSUBL = 381
927
+ INS_UMULH = 382
928
+ INS_UMULL2 = 383
929
+ INS_UMULL = 384
930
+ INS_UQADD = 385
931
+ INS_UQRSHL = 386
932
+ INS_UQRSHRN = 387
933
+ INS_UQRSHRN2 = 388
934
+ INS_UQSHL = 389
935
+ INS_UQSHRN = 390
936
+ INS_UQSHRN2 = 391
937
+ INS_UQSUB = 392
938
+ INS_UQXTN2 = 393
939
+ INS_UQXTN = 394
940
+ INS_URECPE = 395
941
+ INS_URHADD = 396
942
+ INS_URSHL = 397
943
+ INS_URSHR = 398
944
+ INS_URSQRTE = 399
945
+ INS_URSRA = 400
946
+ INS_USHLL2 = 401
947
+ INS_USHLL = 402
948
+ INS_USHL = 403
949
+ INS_USHR = 404
950
+ INS_USQADD = 405
951
+ INS_USRA = 406
952
+ INS_USUBL2 = 407
953
+ INS_USUBL = 408
954
+ INS_USUBW2 = 409
955
+ INS_USUBW = 410
956
+ INS_UZP1 = 411
957
+ INS_UZP2 = 412
958
+ INS_XTN2 = 413
959
+ INS_XTN = 414
960
+ INS_ZIP1 = 415
961
+ INS_ZIP2 = 416
962
+ INS_MNEG = 417
963
+ INS_UMNEGL = 418
964
+ INS_SMNEGL = 419
965
+ INS_NOP = 420
966
+ INS_YIELD = 421
967
+ INS_WFE = 422
968
+ INS_WFI = 423
969
+ INS_SEV = 424
970
+ INS_SEVL = 425
971
+ INS_NGC = 426
972
+ INS_SBFIZ = 427
973
+ INS_UBFIZ = 428
974
+ INS_SBFX = 429
975
+ INS_UBFX = 430
976
+ INS_BFI = 431
977
+ INS_BFXIL = 432
978
+ INS_CMN = 433
979
+ INS_MVN = 434
980
+ INS_TST = 435
981
+ INS_CSET = 436
982
+ INS_CINC = 437
983
+ INS_CSETM = 438
984
+ INS_CINV = 439
985
+ INS_CNEG = 440
986
+ INS_SXTB = 441
987
+ INS_SXTH = 442
988
+ INS_SXTW = 443
989
+ INS_CMP = 444
990
+ INS_UXTB = 445
991
+ INS_UXTH = 446
992
+ INS_UXTW = 447
993
+ INS_IC = 448
994
+ INS_DC = 449
995
+ INS_AT = 450
996
+ INS_TLBI = 451
997
+ INS_NEGS = 452
998
+ INS_NGCS = 453
999
+ INS_ENDING = 454
1000
+
1001
+ GRP_INVALID = 0
1002
+ GRP_JUMP = 1
1003
+ GRP_CALL = 2
1004
+ GRP_RET = 3
1005
+ GRP_INT = 4
1006
+ GRP_PRIVILEGE = 6
1007
+ GRP_BRANCH_RELATIVE = 7
1008
+ GRP_CRYPTO = 128
1009
+ GRP_FPARMV8 = 129
1010
+ GRP_NEON = 130
1011
+ GRP_CRC = 131
1012
+ GRP_ENDING = 132
1013
+
1014
+ extend Register
1015
+ end
1016
+ end