crabstone 3.0.3 → 4.0.0

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Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +45 -42
  3. data/README.md +16 -33
  4. data/lib/crabstone.rb +5 -557
  5. data/lib/crabstone/arch.rb +37 -0
  6. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  7. data/lib/crabstone/arch/3/arm64.rb +124 -0
  8. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  9. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  10. data/lib/crabstone/arch/3/mips.rb +57 -0
  11. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  12. data/lib/crabstone/arch/3/ppc.rb +73 -0
  13. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  14. data/lib/crabstone/arch/3/sparc.rb +60 -0
  15. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  16. data/lib/crabstone/arch/3/sysz.rb +67 -0
  17. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  18. data/lib/crabstone/arch/3/x86.rb +82 -0
  19. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  20. data/lib/crabstone/arch/3/xcore.rb +59 -0
  21. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  22. data/lib/crabstone/arch/4/arm.rb +110 -0
  23. data/lib/crabstone/arch/4/arm64.rb +125 -0
  24. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  25. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  26. data/lib/crabstone/arch/4/evm.rb +20 -0
  27. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  28. data/lib/crabstone/arch/4/m680x.rb +106 -0
  29. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  30. data/lib/crabstone/arch/4/m68k.rb +129 -0
  31. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  32. data/lib/crabstone/arch/4/mips.rb +57 -0
  33. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  34. data/lib/crabstone/arch/4/ppc.rb +73 -0
  35. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  36. data/lib/crabstone/arch/4/sparc.rb +60 -0
  37. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  38. data/lib/crabstone/arch/4/sysz.rb +67 -0
  39. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  40. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  41. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  42. data/lib/crabstone/arch/4/x86.rb +91 -0
  43. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  44. data/lib/crabstone/arch/4/xcore.rb +59 -0
  45. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  46. data/lib/crabstone/arch/extension.rb +27 -0
  47. data/lib/crabstone/arch/register.rb +36 -0
  48. data/lib/crabstone/binding.rb +60 -0
  49. data/lib/crabstone/binding/3/detail.rb +36 -0
  50. data/lib/crabstone/binding/3/instruction.rb +23 -0
  51. data/lib/crabstone/binding/4/detail.rb +40 -0
  52. data/lib/crabstone/binding/4/instruction.rb +23 -0
  53. data/lib/crabstone/binding/structs.rb +32 -0
  54. data/lib/crabstone/constants.rb +110 -0
  55. data/lib/crabstone/cs_version.rb +49 -0
  56. data/lib/crabstone/disassembler.rb +153 -0
  57. data/lib/crabstone/error.rb +60 -0
  58. data/lib/crabstone/instruction.rb +183 -0
  59. data/lib/crabstone/version.rb +5 -0
  60. metadata +128 -324
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
@@ -1,3 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0xf1,0x47,0xe8,0x5e = sshl d17, d31, d8
3
- 0xf1,0x47,0xe8,0x7e = ushl d17, d31, d8
@@ -1,13 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x20,0xa4,0x0b,0x0f = sshll v0.8h, v1.8b, #3
3
- 0x20,0xa4,0x13,0x0f = sshll v0.4s, v1.4h, #3
4
- 0x20,0xa4,0x23,0x0f = sshll v0.2d, v1.2s, #3
5
- 0x20,0xa4,0x0b,0x4f = sshll2 v0.8h, v1.16b, #3
6
- 0x20,0xa4,0x13,0x4f = sshll2 v0.4s, v1.8h, #3
7
- 0x20,0xa4,0x23,0x4f = sshll2 v0.2d, v1.4s, #3
8
- 0x20,0xa4,0x0b,0x2f = ushll v0.8h, v1.8b, #3
9
- 0x20,0xa4,0x13,0x2f = ushll v0.4s, v1.4h, #3
10
- 0x20,0xa4,0x23,0x2f = ushll v0.2d, v1.2s, #3
11
- 0x20,0xa4,0x0b,0x6f = ushll2 v0.8h, v1.16b, #3
12
- 0x20,0xa4,0x13,0x6f = ushll2 v0.4s, v1.8h, #3
13
- 0x20,0xa4,0x23,0x6f = ushll2 v0.2d, v1.4s, #3
@@ -1,22 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x20,0x44,0x22,0x0e = sshl v0.8b, v1.8b, v2.8b
3
- 0x20,0x44,0x22,0x4e = sshl v0.16b, v1.16b, v2.16b
4
- 0x20,0x44,0x62,0x0e = sshl v0.4h, v1.4h, v2.4h
5
- 0x20,0x44,0x62,0x4e = sshl v0.8h, v1.8h, v2.8h
6
- 0x20,0x44,0xa2,0x0e = sshl v0.2s, v1.2s, v2.2s
7
- 0x20,0x44,0xa2,0x4e = sshl v0.4s, v1.4s, v2.4s
8
- 0x20,0x44,0xe2,0x4e = sshl v0.2d, v1.2d, v2.2d
9
- 0x20,0x44,0x22,0x2e = ushl v0.8b, v1.8b, v2.8b
10
- 0x20,0x44,0x22,0x6e = ushl v0.16b, v1.16b, v2.16b
11
- 0x20,0x44,0x62,0x2e = ushl v0.4h, v1.4h, v2.4h
12
- 0x20,0x44,0x62,0x6e = ushl v0.8h, v1.8h, v2.8h
13
- 0x20,0x44,0xa2,0x2e = ushl v0.2s, v1.2s, v2.2s
14
- 0x20,0x44,0xa2,0x6e = ushl v0.4s, v1.4s, v2.4s
15
- 0x20,0x44,0xe2,0x6e = ushl v0.2d, v1.2d, v2.2d
16
- 0x20,0x54,0x0b,0x0f = shl v0.8b, v1.8b, #3
17
- 0x20,0x54,0x13,0x0f = shl v0.4h, v1.4h, #3
18
- 0x20,0x54,0x23,0x0f = shl v0.2s, v1.2s, #3
19
- 0x20,0x54,0x0b,0x4f = shl v0.16b, v1.16b, #3
20
- 0x20,0x54,0x13,0x4f = shl v0.8h, v1.8h, #3
21
- 0x20,0x54,0x23,0x4f = shl v0.4s, v1.4s, #3
22
- 0x20,0x54,0x43,0x4f = shl v0.2d, v1.2d, #3
@@ -1,42 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x22,0x1c,0x05,0x4e = ins v2.b[2], w1
3
- 0xc7,0x1d,0x1e,0x4e = ins v7.h[7], w14
4
- 0xd4,0x1f,0x04,0x4e = ins v20.s[0], w30
5
- 0xe1,0x1c,0x18,0x4e = ins v1.d[1], x7
6
- 0x22,0x1c,0x05,0x4e = ins v2.b[2], w1
7
- 0xc7,0x1d,0x1e,0x4e = ins v7.h[7], w14
8
- 0xd4,0x1f,0x04,0x4e = ins v20.s[0], w30
9
- 0xe1,0x1c,0x18,0x4e = ins v1.d[1], x7
10
- 0x01,0x2c,0x1f,0x0e = smov w1, v0.b[15]
11
- 0xce,0x2c,0x12,0x0e = smov w14, v6.h[4]
12
- 0x01,0x2c,0x1f,0x4e = smov x1, v0.b[15]
13
- 0xce,0x2c,0x12,0x4e = smov x14, v6.h[4]
14
- 0x34,0x2d,0x14,0x4e = smov x20, v9.s[2]
15
- 0x01,0x3c,0x1f,0x0e = umov w1, v0.b[15]
16
- 0xce,0x3c,0x12,0x0e = umov w14, v6.h[4]
17
- 0x34,0x3d,0x14,0x0e = umov w20, v9.s[2]
18
- 0x47,0x3e,0x18,0x4e = umov x7, v18.d[1]
19
- 0x34,0x3d,0x14,0x0e = umov w20, v9.s[2]
20
- 0x47,0x3e,0x18,0x4e = umov x7, v18.d[1]
21
- 0x61,0x34,0x1d,0x6e = ins v1.b[14], v3.b[6]
22
- 0xe6,0x54,0x1e,0x6e = ins v6.h[7], v7.h[5]
23
- 0xcf,0x46,0x1c,0x6e = ins v15.s[3], v22.s[2]
24
- 0x80,0x44,0x08,0x6e = ins v0.d[0], v4.d[1]
25
- 0x61,0x34,0x1d,0x6e = ins v1.b[14], v3.b[6]
26
- 0xe6,0x54,0x1e,0x6e = ins v6.h[7], v7.h[5]
27
- 0xcf,0x46,0x1c,0x6e = ins v15.s[3], v22.s[2]
28
- 0x80,0x44,0x08,0x6e = ins v0.d[0], v4.d[1]
29
- 0x41,0x04,0x05,0x0e = dup v1.8b, v2.b[2]
30
- 0xeb,0x04,0x1e,0x0e = dup v11.4h, v7.h[7]
31
- 0x91,0x06,0x04,0x0e = dup v17.2s, v20.s[0]
32
- 0x41,0x04,0x05,0x4e = dup v1.16b, v2.b[2]
33
- 0xeb,0x04,0x1e,0x4e = dup v11.8h, v7.h[7]
34
- 0x91,0x06,0x04,0x4e = dup v17.4s, v20.s[0]
35
- 0x25,0x04,0x18,0x4e = dup v5.2d, v1.d[1]
36
- 0x21,0x0c,0x01,0x0e = dup v1.8b, w1
37
- 0xcb,0x0d,0x02,0x0e = dup v11.4h, w14
38
- 0xd1,0x0f,0x04,0x0e = dup v17.2s, w30
39
- 0x41,0x0c,0x01,0x4e = dup v1.16b, w2
40
- 0x0b,0x0e,0x02,0x4e = dup v11.8h, w16
41
- 0x91,0x0f,0x04,0x4e = dup v17.4s, w28
42
- 0x05,0x0c,0x08,0x4e = dup v5.2d, x0
@@ -1,197 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x00,0x70,0x00,0x4c = st1 {v0.16b}, [x0]
3
- 0xef,0x75,0x00,0x4c = st1 {v15.8h}, [x15]
4
- 0xff,0x7b,0x00,0x4c = st1 {v31.4s}, [sp]
5
- 0x00,0x7c,0x00,0x4c = st1 {v0.2d}, [x0]
6
- 0x00,0x70,0x00,0x0c = st1 {v0.8b}, [x0]
7
- 0xef,0x75,0x00,0x0c = st1 {v15.4h}, [x15]
8
- 0xff,0x7b,0x00,0x0c = st1 {v31.2s}, [sp]
9
- 0x00,0x7c,0x00,0x0c = st1 {v0.1d}, [x0]
10
- 0x00,0xa0,0x00,0x4c = st1 {v0.16b, v1.16b}, [x0]
11
- 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15]
12
- 0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp]
13
- 0x00,0xac,0x00,0x4c = st1 {v0.2d, v1.2d}, [x0]
14
- 0x00,0xa0,0x00,0x0c = st1 {v0.8b, v1.8b}, [x0]
15
- 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15]
16
- 0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp]
17
- 0x00,0xac,0x00,0x0c = st1 {v0.1d, v1.1d}, [x0]
18
- 0x00,0xa0,0x00,0x4c = st1 {v0.16b, v1.16b}, [x0]
19
- 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15]
20
- 0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp]
21
- 0x00,0xac,0x00,0x4c = st1 {v0.2d, v1.2d}, [x0]
22
- 0x00,0xa0,0x00,0x0c = st1 {v0.8b, v1.8b}, [x0]
23
- 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15]
24
- 0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp]
25
- 0x00,0xac,0x00,0x0c = st1 {v0.1d, v1.1d}, [x0]
26
- 0x00,0x60,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0]
27
- 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15]
28
- 0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp]
29
- 0x00,0x6c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0]
30
- 0x00,0x60,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0]
31
- 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15]
32
- 0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp]
33
- 0x00,0x6c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0]
34
- 0x00,0x60,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0]
35
- 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15]
36
- 0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp]
37
- 0x00,0x6c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0]
38
- 0x00,0x60,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0]
39
- 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15]
40
- 0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp]
41
- 0x00,0x6c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0]
42
- 0x00,0x20,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
43
- 0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
44
- 0xff,0x2b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
45
- 0x00,0x2c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
46
- 0x00,0x20,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
47
- 0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
48
- 0xff,0x2b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
49
- 0x00,0x2c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0]
50
- 0x00,0x20,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
51
- 0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
52
- 0xff,0x2b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
53
- 0x00,0x2c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
54
- 0x00,0x20,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
55
- 0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
56
- 0xff,0x2b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
57
- 0x00,0x2c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0]
58
- 0x00,0x80,0x00,0x4c = st2 {v0.16b, v1.16b}, [x0]
59
- 0xef,0x85,0x00,0x4c = st2 {v15.8h, v16.8h}, [x15]
60
- 0xff,0x8b,0x00,0x4c = st2 {v31.4s, v0.4s}, [sp]
61
- 0x00,0x8c,0x00,0x4c = st2 {v0.2d, v1.2d}, [x0]
62
- 0x00,0x80,0x00,0x0c = st2 {v0.8b, v1.8b}, [x0]
63
- 0xef,0x85,0x00,0x0c = st2 {v15.4h, v16.4h}, [x15]
64
- 0xff,0x8b,0x00,0x0c = st2 {v31.2s, v0.2s}, [sp]
65
- 0x00,0x80,0x00,0x4c = st2 {v0.16b, v1.16b}, [x0]
66
- 0xef,0x85,0x00,0x4c = st2 {v15.8h, v16.8h}, [x15]
67
- 0xff,0x8b,0x00,0x4c = st2 {v31.4s, v0.4s}, [sp]
68
- 0x00,0x8c,0x00,0x4c = st2 {v0.2d, v1.2d}, [x0]
69
- 0x00,0x80,0x00,0x0c = st2 {v0.8b, v1.8b}, [x0]
70
- 0xef,0x85,0x00,0x0c = st2 {v15.4h, v16.4h}, [x15]
71
- 0xff,0x8b,0x00,0x0c = st2 {v31.2s, v0.2s}, [sp]
72
- 0x00,0x40,0x00,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0]
73
- 0xef,0x45,0x00,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15]
74
- 0xff,0x4b,0x00,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp]
75
- 0x00,0x4c,0x00,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0]
76
- 0x00,0x40,0x00,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0]
77
- 0xef,0x45,0x00,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15]
78
- 0xff,0x4b,0x00,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp]
79
- 0x00,0x40,0x00,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0]
80
- 0xef,0x45,0x00,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15]
81
- 0xff,0x4b,0x00,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp]
82
- 0x00,0x4c,0x00,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0]
83
- 0x00,0x40,0x00,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0]
84
- 0xef,0x45,0x00,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15]
85
- 0xff,0x4b,0x00,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp]
86
- 0x00,0x00,0x00,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
87
- 0xef,0x05,0x00,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
88
- 0xff,0x0b,0x00,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
89
- 0x00,0x0c,0x00,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
90
- 0x00,0x00,0x00,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
91
- 0xef,0x05,0x00,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
92
- 0xff,0x0b,0x00,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
93
- 0x00,0x00,0x00,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
94
- 0xef,0x05,0x00,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
95
- 0xff,0x0b,0x00,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
96
- 0x00,0x0c,0x00,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
97
- 0x00,0x00,0x00,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
98
- 0xef,0x05,0x00,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
99
- 0xff,0x0b,0x00,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
100
- 0x00,0x70,0x40,0x4c = ld1 {v0.16b}, [x0]
101
- 0xef,0x75,0x40,0x4c = ld1 {v15.8h}, [x15]
102
- 0xff,0x7b,0x40,0x4c = ld1 {v31.4s}, [sp]
103
- 0x00,0x7c,0x40,0x4c = ld1 {v0.2d}, [x0]
104
- 0x00,0x70,0x40,0x0c = ld1 {v0.8b}, [x0]
105
- 0xef,0x75,0x40,0x0c = ld1 {v15.4h}, [x15]
106
- 0xff,0x7b,0x40,0x0c = ld1 {v31.2s}, [sp]
107
- 0x00,0x7c,0x40,0x0c = ld1 {v0.1d}, [x0]
108
- 0x00,0xa0,0x40,0x4c = ld1 {v0.16b, v1.16b}, [x0]
109
- 0xef,0xa5,0x40,0x4c = ld1 {v15.8h, v16.8h}, [x15]
110
- 0xff,0xab,0x40,0x4c = ld1 {v31.4s, v0.4s}, [sp]
111
- 0x00,0xac,0x40,0x4c = ld1 {v0.2d, v1.2d}, [x0]
112
- 0x00,0xa0,0x40,0x0c = ld1 {v0.8b, v1.8b}, [x0]
113
- 0xef,0xa5,0x40,0x0c = ld1 {v15.4h, v16.4h}, [x15]
114
- 0xff,0xab,0x40,0x0c = ld1 {v31.2s, v0.2s}, [sp]
115
- 0x00,0xac,0x40,0x0c = ld1 {v0.1d, v1.1d}, [x0]
116
- 0x00,0xa0,0x40,0x4c = ld1 {v0.16b, v1.16b}, [x0]
117
- 0xef,0xa5,0x40,0x4c = ld1 {v15.8h, v16.8h}, [x15]
118
- 0xff,0xab,0x40,0x4c = ld1 {v31.4s, v0.4s}, [sp]
119
- 0x00,0xac,0x40,0x4c = ld1 {v0.2d, v1.2d}, [x0]
120
- 0x00,0xa0,0x40,0x0c = ld1 {v0.8b, v1.8b}, [x0]
121
- 0xef,0xa5,0x40,0x0c = ld1 {v15.4h, v16.4h}, [x15]
122
- 0xff,0xab,0x40,0x0c = ld1 {v31.2s, v0.2s}, [sp]
123
- 0x00,0xac,0x40,0x0c = ld1 {v0.1d, v1.1d}, [x0]
124
- 0x00,0x60,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0]
125
- 0xef,0x65,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15]
126
- 0xff,0x6b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp]
127
- 0x00,0x6c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0]
128
- 0x00,0x60,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0]
129
- 0xef,0x65,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15]
130
- 0xff,0x6b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp]
131
- 0x00,0x6c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0]
132
- 0x00,0x60,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0]
133
- 0xef,0x65,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15]
134
- 0xff,0x6b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp]
135
- 0x00,0x6c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0]
136
- 0x00,0x60,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0]
137
- 0xef,0x65,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15]
138
- 0xff,0x6b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp]
139
- 0x00,0x6c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0]
140
- 0x00,0x20,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
141
- 0xef,0x25,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
142
- 0xff,0x2b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
143
- 0x00,0x2c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
144
- 0x00,0x20,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
145
- 0xef,0x25,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
146
- 0xff,0x2b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
147
- 0x00,0x2c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0]
148
- 0x00,0x20,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
149
- 0xef,0x25,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
150
- 0xff,0x2b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
151
- 0x00,0x2c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
152
- 0x00,0x20,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
153
- 0xef,0x25,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
154
- 0xff,0x2b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
155
- 0x00,0x2c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0]
156
- 0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0]
157
- 0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15]
158
- 0xff,0x8b,0x40,0x4c = ld2 {v31.4s, v0.4s}, [sp]
159
- 0x00,0x8c,0x40,0x4c = ld2 {v0.2d, v1.2d}, [x0]
160
- 0x00,0x80,0x40,0x0c = ld2 {v0.8b, v1.8b}, [x0]
161
- 0xef,0x85,0x40,0x0c = ld2 {v15.4h, v16.4h}, [x15]
162
- 0xff,0x8b,0x40,0x0c = ld2 {v31.2s, v0.2s}, [sp]
163
- 0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0]
164
- 0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15]
165
- 0xff,0x8b,0x40,0x4c = ld2 {v31.4s, v0.4s}, [sp]
166
- 0x00,0x8c,0x40,0x4c = ld2 {v0.2d, v1.2d}, [x0]
167
- 0x00,0x80,0x40,0x0c = ld2 {v0.8b, v1.8b}, [x0]
168
- 0xef,0x85,0x40,0x0c = ld2 {v15.4h, v16.4h}, [x15]
169
- 0xff,0x8b,0x40,0x0c = ld2 {v31.2s, v0.2s}, [sp]
170
- 0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0]
171
- 0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15]
172
- 0xff,0x4b,0x40,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp]
173
- 0x00,0x4c,0x40,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0]
174
- 0x00,0x40,0x40,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0]
175
- 0xef,0x45,0x40,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15]
176
- 0xff,0x4b,0x40,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp]
177
- 0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0]
178
- 0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15]
179
- 0xff,0x4b,0x40,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp]
180
- 0x00,0x4c,0x40,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0]
181
- 0x00,0x40,0x40,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0]
182
- 0xef,0x45,0x40,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15]
183
- 0xff,0x4b,0x40,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp]
184
- 0x00,0x00,0x40,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
185
- 0xef,0x05,0x40,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
186
- 0xff,0x0b,0x40,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
187
- 0x00,0x0c,0x40,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
188
- 0x00,0x00,0x40,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
189
- 0xef,0x05,0x40,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
190
- 0xff,0x0b,0x40,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
191
- 0x00,0x00,0x40,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
192
- 0xef,0x05,0x40,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
193
- 0xff,0x0b,0x40,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
194
- 0x00,0x0c,0x40,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
195
- 0x00,0x00,0x40,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
196
- 0xef,0x05,0x40,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
197
- 0xff,0x0b,0x40,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
@@ -1,129 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x00,0xc0,0x40,0x4d = ld1r {v0.16b}, [x0]
3
- 0xef,0xc5,0x40,0x4d = ld1r {v15.8h}, [x15]
4
- 0xff,0xcb,0x40,0x4d = ld1r {v31.4s}, [sp]
5
- 0x00,0xcc,0x40,0x4d = ld1r {v0.2d}, [x0]
6
- 0x00,0xc0,0x40,0x0d = ld1r {v0.8b}, [x0]
7
- 0xef,0xc5,0x40,0x0d = ld1r {v15.4h}, [x15]
8
- 0xff,0xcb,0x40,0x0d = ld1r {v31.2s}, [sp]
9
- 0x00,0xcc,0x40,0x0d = ld1r {v0.1d}, [x0]
10
- 0x00,0xc0,0x60,0x4d = ld2r {v0.16b, v1.16b}, [x0]
11
- 0xef,0xc5,0x60,0x4d = ld2r {v15.8h, v16.8h}, [x15]
12
- 0xff,0xcb,0x60,0x4d = ld2r {v31.4s, v0.4s}, [sp]
13
- 0x00,0xcc,0x60,0x4d = ld2r {v0.2d, v1.2d}, [x0]
14
- 0x00,0xc0,0x60,0x0d = ld2r {v0.8b, v1.8b}, [x0]
15
- 0xef,0xc5,0x60,0x0d = ld2r {v15.4h, v16.4h}, [x15]
16
- 0xff,0xcb,0x60,0x0d = ld2r {v31.2s, v0.2s}, [sp]
17
- 0xff,0xcf,0x60,0x0d = ld2r {v31.1d, v0.1d}, [sp]
18
- 0x00,0xe0,0x40,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0]
19
- 0xef,0xe5,0x40,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15]
20
- 0xff,0xeb,0x40,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp]
21
- 0x00,0xec,0x40,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0]
22
- 0x00,0xe0,0x40,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0]
23
- 0xef,0xe5,0x40,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15]
24
- 0xff,0xeb,0x40,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp]
25
- 0xff,0xef,0x40,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp]
26
- 0x00,0xe0,0x60,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
27
- 0xef,0xe5,0x60,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
28
- 0xff,0xeb,0x60,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
29
- 0x00,0xec,0x60,0x4d = ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
30
- 0x00,0xe0,0x60,0x0d = ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
31
- 0xef,0xe5,0x60,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
32
- 0xff,0xeb,0x60,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
33
- 0xff,0xef,0x60,0x0d = ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp]
34
- 0x00,0x04,0x40,0x4d = ld1 {v0.b}[9], [x0]
35
- 0xef,0x59,0x40,0x4d = ld1 {v15.h}[7], [x15]
36
- 0xff,0x93,0x40,0x4d = ld1 {v31.s}[3], [sp]
37
- 0x00,0x84,0x40,0x4d = ld1 {v0.d}[1], [x0]
38
- 0x00,0x04,0x60,0x4d = ld2 {v0.b, v1.b}[9], [x0]
39
- 0xef,0x59,0x60,0x4d = ld2 {v15.h, v16.h}[7], [x15]
40
- 0xff,0x93,0x60,0x4d = ld2 {v31.s, v0.s}[3], [sp]
41
- 0x00,0x84,0x60,0x4d = ld2 {v0.d, v1.d}[1], [x0]
42
- 0x00,0x24,0x40,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0]
43
- 0xef,0x79,0x40,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15]
44
- 0xff,0xb3,0x40,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp]
45
- 0x00,0xa4,0x40,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0]
46
- 0x00,0x24,0x60,0x4d = ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0]
47
- 0xef,0x79,0x60,0x4d = ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15]
48
- 0xff,0xb3,0x60,0x4d = ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp]
49
- 0x00,0xa4,0x60,0x4d = ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0]
50
- 0x00,0x04,0x00,0x4d = st1 {v0.b}[9], [x0]
51
- 0xef,0x59,0x00,0x4d = st1 {v15.h}[7], [x15]
52
- 0xff,0x93,0x00,0x4d = st1 {v31.s}[3], [sp]
53
- 0x00,0x84,0x00,0x4d = st1 {v0.d}[1], [x0]
54
- 0x00,0x04,0x20,0x4d = st2 {v0.b, v1.b}[9], [x0]
55
- 0xef,0x59,0x20,0x4d = st2 {v15.h, v16.h}[7], [x15]
56
- 0xff,0x93,0x20,0x4d = st2 {v31.s, v0.s}[3], [sp]
57
- 0x00,0x84,0x20,0x4d = st2 {v0.d, v1.d}[1], [x0]
58
- 0x00,0x24,0x00,0x4d = st3 {v0.b, v1.b, v2.b}[9], [x0]
59
- 0xef,0x79,0x00,0x4d = st3 {v15.h, v16.h, v17.h}[7], [x15]
60
- 0xff,0xb3,0x00,0x4d = st3 {v31.s, v0.s, v1.s}[3], [sp]
61
- 0x00,0xa4,0x00,0x4d = st3 {v0.d, v1.d, v2.d}[1], [x0]
62
- 0x00,0x24,0x20,0x4d = st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0]
63
- 0xef,0x79,0x20,0x4d = st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15]
64
- 0xff,0xb3,0x20,0x4d = st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp]
65
- 0x00,0xa4,0x20,0x4d = st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0]
66
- 0x00,0xc0,0xdf,0x4d = ld1r {v0.16b}, [x0], #1
67
- 0xef,0xc5,0xdf,0x4d = ld1r {v15.8h}, [x15], #2
68
- 0xff,0xcb,0xdf,0x4d = ld1r {v31.4s}, [sp], #4
69
- 0x00,0xcc,0xdf,0x4d = ld1r {v0.2d}, [x0], #8
70
- 0x00,0xc0,0xc0,0x0d = ld1r {v0.8b}, [x0], x0
71
- 0xef,0xc5,0xc1,0x0d = ld1r {v15.4h}, [x15], x1
72
- 0xff,0xcb,0xc2,0x0d = ld1r {v31.2s}, [sp], x2
73
- 0x00,0xcc,0xc3,0x0d = ld1r {v0.1d}, [x0], x3
74
- 0x00,0xc0,0xff,0x4d = ld2r {v0.16b, v1.16b}, [x0], #2
75
- 0xef,0xc5,0xff,0x4d = ld2r {v15.8h, v16.8h}, [x15], #4
76
- 0xff,0xcb,0xff,0x4d = ld2r {v31.4s, v0.4s}, [sp], #8
77
- 0x00,0xcc,0xff,0x4d = ld2r {v0.2d, v1.2d}, [x0], #16
78
- 0x00,0xc0,0xe6,0x0d = ld2r {v0.8b, v1.8b}, [x0], x6
79
- 0xef,0xc5,0xe7,0x0d = ld2r {v15.4h, v16.4h}, [x15], x7
80
- 0xff,0xcb,0xe9,0x0d = ld2r {v31.2s, v0.2s}, [sp], x9
81
- 0x1f,0xcc,0xe5,0x0d = ld2r {v31.1d, v0.1d}, [x0], x5
82
- 0x00,0xe0,0xc9,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9
83
- 0xef,0xe5,0xc6,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6
84
- 0xff,0xeb,0xc7,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7
85
- 0x00,0xec,0xc5,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5
86
- 0x00,0xe0,0xdf,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3
87
- 0xef,0xe5,0xdf,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6
88
- 0xff,0xeb,0xdf,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12
89
- 0xff,0xef,0xdf,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24
90
- 0x00,0xe0,0xff,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4
91
- 0xef,0xe5,0xff,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8
92
- 0xff,0xeb,0xff,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16
93
- 0x00,0xec,0xff,0x4d = ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32
94
- 0x00,0xe0,0xe5,0x0d = ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5
95
- 0xef,0xe5,0xe9,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9
96
- 0xff,0xeb,0xfe,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30
97
- 0xff,0xef,0xe7,0x0d = ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7
98
- 0x00,0x04,0xdf,0x4d = ld1 {v0.b}[9], [x0], #1
99
- 0xef,0x59,0xc9,0x4d = ld1 {v15.h}[7], [x15], x9
100
- 0xff,0x93,0xc6,0x4d = ld1 {v31.s}[3], [sp], x6
101
- 0x00,0x84,0xdf,0x4d = ld1 {v0.d}[1], [x0], #8
102
- 0x00,0x04,0xe3,0x4d = ld2 {v0.b, v1.b}[9], [x0], x3
103
- 0xef,0x59,0xff,0x4d = ld2 {v15.h, v16.h}[7], [x15], #4
104
- 0xff,0x93,0xff,0x4d = ld2 {v31.s, v0.s}[3], [sp], #8
105
- 0x00,0x84,0xe0,0x4d = ld2 {v0.d, v1.d}[1], [x0], x0
106
- 0x00,0x24,0xdf,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0], #3
107
- 0xef,0x79,0xdf,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15], #6
108
- 0xff,0xb3,0xc3,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
109
- 0x00,0xa4,0xc6,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0], x6
110
- 0x00,0x24,0xe5,0x4d = ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5
111
- 0xef,0x79,0xe7,0x4d = ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7
112
- 0xff,0xb3,0xff,0x4d = ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16
113
- 0x00,0xa4,0xff,0x4d = ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
114
- 0x00,0x04,0x9f,0x4d = st1 {v0.b}[9], [x0], #1
115
- 0xef,0x59,0x89,0x4d = st1 {v15.h}[7], [x15], x9
116
- 0xff,0x93,0x86,0x4d = st1 {v31.s}[3], [sp], x6
117
- 0x00,0x84,0x9f,0x4d = st1 {v0.d}[1], [x0], #8
118
- 0x00,0x04,0xa3,0x4d = st2 {v0.b, v1.b}[9], [x0], x3
119
- 0xef,0x59,0xbf,0x4d = st2 {v15.h, v16.h}[7], [x15], #4
120
- 0xff,0x93,0xbf,0x4d = st2 {v31.s, v0.s}[3], [sp], #8
121
- 0x00,0x84,0xa0,0x4d = st2 {v0.d, v1.d}[1], [x0], x0
122
- 0x00,0x24,0x9f,0x4d = st3 {v0.b, v1.b, v2.b}[9], [x0], #3
123
- 0xef,0x79,0x9f,0x4d = st3 {v15.h, v16.h, v17.h}[7], [x15], #6
124
- 0xff,0xb3,0x83,0x4d = st3 {v31.s, v0.s, v1.s}[3], [sp], x3
125
- 0x00,0xa4,0x86,0x4d = st3 {v0.d, v1.d, v2.d}[1], [x0], x6
126
- 0x00,0x24,0xa5,0x4d = st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5
127
- 0xef,0x79,0xa7,0x4d = st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7
128
- 0xff,0xb3,0xbf,0x4d = st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16
129
- 0x00,0xa4,0xbf,0x4d = st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
@@ -1,213 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0xe0,0x0b,0x20,0x4e = rev64 v0.16b, v31.16b
3
- 0x82,0x08,0x60,0x4e = rev64 v2.8h, v4.8h
4
- 0x06,0x09,0xa0,0x4e = rev64 v6.4s, v8.4s
5
- 0x21,0x09,0x20,0x0e = rev64 v1.8b, v9.8b
6
- 0xad,0x0a,0x60,0x0e = rev64 v13.4h, v21.4h
7
- 0x04,0x08,0xa0,0x0e = rev64 v4.2s, v0.2s
8
- 0xfe,0x0b,0x20,0x6e = rev32 v30.16b, v31.16b
9
- 0xe4,0x08,0x60,0x6e = rev32 v4.8h, v7.8h
10
- 0x35,0x08,0x20,0x2e = rev32 v21.8b, v1.8b
11
- 0x20,0x09,0x60,0x2e = rev32 v0.4h, v9.4h
12
- 0xfe,0x1b,0x20,0x4e = rev16 v30.16b, v31.16b
13
- 0x35,0x18,0x20,0x0e = rev16 v21.8b, v1.8b
14
- 0xa3,0x2a,0x20,0x4e = saddlp v3.8h, v21.16b
15
- 0xa8,0x28,0x20,0x0e = saddlp v8.4h, v5.8b
16
- 0x29,0x28,0x60,0x4e = saddlp v9.4s, v1.8h
17
- 0x20,0x28,0x60,0x0e = saddlp v0.2s, v1.4h
18
- 0x8c,0x28,0xa0,0x4e = saddlp v12.2d, v4.4s
19
- 0x91,0x2b,0xa0,0x0e = saddlp v17.1d, v28.2s
20
- 0xa3,0x2a,0x20,0x6e = uaddlp v3.8h, v21.16b
21
- 0xa8,0x28,0x20,0x2e = uaddlp v8.4h, v5.8b
22
- 0x29,0x28,0x60,0x6e = uaddlp v9.4s, v1.8h
23
- 0x20,0x28,0x60,0x2e = uaddlp v0.2s, v1.4h
24
- 0x8c,0x28,0xa0,0x6e = uaddlp v12.2d, v4.4s
25
- 0x91,0x2b,0xa0,0x2e = uaddlp v17.1d, v28.2s
26
- 0xa3,0x6a,0x20,0x4e = sadalp v3.8h, v21.16b
27
- 0xa8,0x68,0x20,0x0e = sadalp v8.4h, v5.8b
28
- 0x29,0x68,0x60,0x4e = sadalp v9.4s, v1.8h
29
- 0x20,0x68,0x60,0x0e = sadalp v0.2s, v1.4h
30
- 0x8c,0x68,0xa0,0x4e = sadalp v12.2d, v4.4s
31
- 0x91,0x6b,0xa0,0x0e = sadalp v17.1d, v28.2s
32
- 0xa3,0x6a,0x20,0x6e = uadalp v3.8h, v21.16b
33
- 0xa8,0x68,0x20,0x2e = uadalp v8.4h, v5.8b
34
- 0x29,0x68,0x60,0x6e = uadalp v9.4s, v1.8h
35
- 0x20,0x68,0x60,0x2e = uadalp v0.2s, v1.4h
36
- 0x8c,0x68,0xa0,0x6e = uadalp v12.2d, v4.4s
37
- 0x91,0x6b,0xa0,0x2e = uadalp v17.1d, v28.2s
38
- 0xe0,0x3b,0x20,0x4e = suqadd v0.16b, v31.16b
39
- 0x82,0x38,0x60,0x4e = suqadd v2.8h, v4.8h
40
- 0x06,0x39,0xa0,0x4e = suqadd v6.4s, v8.4s
41
- 0x06,0x39,0xe0,0x4e = suqadd v6.2d, v8.2d
42
- 0x21,0x39,0x20,0x0e = suqadd v1.8b, v9.8b
43
- 0xad,0x3a,0x60,0x0e = suqadd v13.4h, v21.4h
44
- 0x04,0x38,0xa0,0x0e = suqadd v4.2s, v0.2s
45
- 0xe0,0x3b,0x20,0x6e = usqadd v0.16b, v31.16b
46
- 0x82,0x38,0x60,0x6e = usqadd v2.8h, v4.8h
47
- 0x06,0x39,0xa0,0x6e = usqadd v6.4s, v8.4s
48
- 0x06,0x39,0xe0,0x6e = usqadd v6.2d, v8.2d
49
- 0x21,0x39,0x20,0x2e = usqadd v1.8b, v9.8b
50
- 0xad,0x3a,0x60,0x2e = usqadd v13.4h, v21.4h
51
- 0x04,0x38,0xa0,0x2e = usqadd v4.2s, v0.2s
52
- 0xe0,0x7b,0x20,0x4e = sqabs v0.16b, v31.16b
53
- 0x82,0x78,0x60,0x4e = sqabs v2.8h, v4.8h
54
- 0x06,0x79,0xa0,0x4e = sqabs v6.4s, v8.4s
55
- 0x06,0x79,0xe0,0x4e = sqabs v6.2d, v8.2d
56
- 0x21,0x79,0x20,0x0e = sqabs v1.8b, v9.8b
57
- 0xad,0x7a,0x60,0x0e = sqabs v13.4h, v21.4h
58
- 0x04,0x78,0xa0,0x0e = sqabs v4.2s, v0.2s
59
- 0xe0,0x7b,0x20,0x6e = sqneg v0.16b, v31.16b
60
- 0x82,0x78,0x60,0x6e = sqneg v2.8h, v4.8h
61
- 0x06,0x79,0xa0,0x6e = sqneg v6.4s, v8.4s
62
- 0x06,0x79,0xe0,0x6e = sqneg v6.2d, v8.2d
63
- 0x21,0x79,0x20,0x2e = sqneg v1.8b, v9.8b
64
- 0xad,0x7a,0x60,0x2e = sqneg v13.4h, v21.4h
65
- 0x04,0x78,0xa0,0x2e = sqneg v4.2s, v0.2s
66
- 0xe0,0xbb,0x20,0x4e = abs v0.16b, v31.16b
67
- 0x82,0xb8,0x60,0x4e = abs v2.8h, v4.8h
68
- 0x06,0xb9,0xa0,0x4e = abs v6.4s, v8.4s
69
- 0x06,0xb9,0xe0,0x4e = abs v6.2d, v8.2d
70
- 0x21,0xb9,0x20,0x0e = abs v1.8b, v9.8b
71
- 0xad,0xba,0x60,0x0e = abs v13.4h, v21.4h
72
- 0x04,0xb8,0xa0,0x0e = abs v4.2s, v0.2s
73
- 0xe0,0xbb,0x20,0x6e = neg v0.16b, v31.16b
74
- 0x82,0xb8,0x60,0x6e = neg v2.8h, v4.8h
75
- 0x06,0xb9,0xa0,0x6e = neg v6.4s, v8.4s
76
- 0x06,0xb9,0xe0,0x6e = neg v6.2d, v8.2d
77
- 0x21,0xb9,0x20,0x2e = neg v1.8b, v9.8b
78
- 0xad,0xba,0x60,0x2e = neg v13.4h, v21.4h
79
- 0x04,0xb8,0xa0,0x2e = neg v4.2s, v0.2s
80
- 0xe0,0x4b,0x20,0x4e = cls v0.16b, v31.16b
81
- 0x82,0x48,0x60,0x4e = cls v2.8h, v4.8h
82
- 0x06,0x49,0xa0,0x4e = cls v6.4s, v8.4s
83
- 0x21,0x49,0x20,0x0e = cls v1.8b, v9.8b
84
- 0xad,0x4a,0x60,0x0e = cls v13.4h, v21.4h
85
- 0x04,0x48,0xa0,0x0e = cls v4.2s, v0.2s
86
- 0xe0,0x4b,0x20,0x6e = clz v0.16b, v31.16b
87
- 0x82,0x48,0x60,0x6e = clz v2.8h, v4.8h
88
- 0x06,0x49,0xa0,0x6e = clz v6.4s, v8.4s
89
- 0x21,0x49,0x20,0x2e = clz v1.8b, v9.8b
90
- 0xad,0x4a,0x60,0x2e = clz v13.4h, v21.4h
91
- 0x04,0x48,0xa0,0x2e = clz v4.2s, v0.2s
92
- 0xe0,0x5b,0x20,0x4e = cnt v0.16b, v31.16b
93
- 0x21,0x59,0x20,0x0e = cnt v1.8b, v9.8b
94
- 0xe0,0x5b,0x20,0x6e = not v0.16b, v31.16b
95
- 0x21,0x59,0x20,0x2e = not v1.8b, v9.8b
96
- 0xe0,0x5b,0x60,0x6e = rbit v0.16b, v31.16b
97
- 0x21,0x59,0x60,0x2e = rbit v1.8b, v9.8b
98
- 0x06,0xf9,0xa0,0x4e = fabs v6.4s, v8.4s
99
- 0x06,0xf9,0xe0,0x4e = fabs v6.2d, v8.2d
100
- 0x04,0xf8,0xa0,0x0e = fabs v4.2s, v0.2s
101
- 0x06,0xf9,0xa0,0x6e = fneg v6.4s, v8.4s
102
- 0x06,0xf9,0xe0,0x6e = fneg v6.2d, v8.2d
103
- 0x04,0xf8,0xa0,0x2e = fneg v4.2s, v0.2s
104
- 0xe0,0x2b,0x21,0x4e = xtn2 v0.16b, v31.8h
105
- 0x82,0x28,0x61,0x4e = xtn2 v2.8h, v4.4s
106
- 0x06,0x29,0xa1,0x4e = xtn2 v6.4s, v8.2d
107
- 0x21,0x29,0x21,0x0e = xtn v1.8b, v9.8h
108
- 0xad,0x2a,0x61,0x0e = xtn v13.4h, v21.4s
109
- 0x04,0x28,0xa1,0x0e = xtn v4.2s, v0.2d
110
- 0xe0,0x2b,0x21,0x6e = sqxtun2 v0.16b, v31.8h
111
- 0x82,0x28,0x61,0x6e = sqxtun2 v2.8h, v4.4s
112
- 0x06,0x29,0xa1,0x6e = sqxtun2 v6.4s, v8.2d
113
- 0x21,0x29,0x21,0x2e = sqxtun v1.8b, v9.8h
114
- 0xad,0x2a,0x61,0x2e = sqxtun v13.4h, v21.4s
115
- 0x04,0x28,0xa1,0x2e = sqxtun v4.2s, v0.2d
116
- 0xe0,0x4b,0x21,0x4e = sqxtn2 v0.16b, v31.8h
117
- 0x82,0x48,0x61,0x4e = sqxtn2 v2.8h, v4.4s
118
- 0x06,0x49,0xa1,0x4e = sqxtn2 v6.4s, v8.2d
119
- 0x21,0x49,0x21,0x0e = sqxtn v1.8b, v9.8h
120
- 0xad,0x4a,0x61,0x0e = sqxtn v13.4h, v21.4s
121
- 0x04,0x48,0xa1,0x0e = sqxtn v4.2s, v0.2d
122
- 0xe0,0x4b,0x21,0x6e = uqxtn2 v0.16b, v31.8h
123
- 0x82,0x48,0x61,0x6e = uqxtn2 v2.8h, v4.4s
124
- 0x06,0x49,0xa1,0x6e = uqxtn2 v6.4s, v8.2d
125
- 0x21,0x49,0x21,0x2e = uqxtn v1.8b, v9.8h
126
- 0xad,0x4a,0x61,0x2e = uqxtn v13.4h, v21.4s
127
- 0x04,0x48,0xa1,0x2e = uqxtn v4.2s, v0.2d
128
- 0x82,0x38,0x21,0x6e = shll2 v2.8h, v4.16b, #8
129
- 0x06,0x39,0x61,0x6e = shll2 v6.4s, v8.8h, #16
130
- 0x06,0x39,0xa1,0x6e = shll2 v6.2d, v8.4s, #32
131
- 0x82,0x38,0x21,0x2e = shll v2.8h, v4.8b, #8
132
- 0x06,0x39,0x61,0x2e = shll v6.4s, v8.4h, #16
133
- 0x06,0x39,0xa1,0x2e = shll v6.2d, v8.2s, #32
134
- 0x82,0x68,0x21,0x4e = fcvtn2 v2.8h, v4.4s
135
- 0x06,0x69,0x61,0x4e = fcvtn2 v6.4s, v8.2d
136
- 0xad,0x6a,0x21,0x0e = fcvtn v13.4h, v21.4s
137
- 0x04,0x68,0x61,0x0e = fcvtn v4.2s, v0.2d
138
- 0x06,0x69,0x61,0x6e = fcvtxn2 v6.4s, v8.2d
139
- 0x04,0x68,0x61,0x2e = fcvtxn v4.2s, v0.2d
140
- 0x29,0x78,0x21,0x0e = fcvtl v9.4s, v1.4h
141
- 0x20,0x78,0x61,0x0e = fcvtl v0.2d, v1.2s
142
- 0x8c,0x78,0x21,0x4e = fcvtl2 v12.4s, v4.8h
143
- 0x91,0x7b,0x61,0x4e = fcvtl2 v17.2d, v28.4s
144
- 0x06,0x89,0x21,0x4e = frintn v6.4s, v8.4s
145
- 0x06,0x89,0x61,0x4e = frintn v6.2d, v8.2d
146
- 0x04,0x88,0x21,0x0e = frintn v4.2s, v0.2s
147
- 0x06,0x89,0x21,0x6e = frinta v6.4s, v8.4s
148
- 0x06,0x89,0x61,0x6e = frinta v6.2d, v8.2d
149
- 0x04,0x88,0x21,0x2e = frinta v4.2s, v0.2s
150
- 0x06,0x89,0xa1,0x4e = frintp v6.4s, v8.4s
151
- 0x06,0x89,0xe1,0x4e = frintp v6.2d, v8.2d
152
- 0x04,0x88,0xa1,0x0e = frintp v4.2s, v0.2s
153
- 0x06,0x99,0x21,0x4e = frintm v6.4s, v8.4s
154
- 0x06,0x99,0x61,0x4e = frintm v6.2d, v8.2d
155
- 0x04,0x98,0x21,0x0e = frintm v4.2s, v0.2s
156
- 0x06,0x99,0x21,0x6e = frintx v6.4s, v8.4s
157
- 0x06,0x99,0x61,0x6e = frintx v6.2d, v8.2d
158
- 0x04,0x98,0x21,0x2e = frintx v4.2s, v0.2s
159
- 0x06,0x99,0xa1,0x4e = frintz v6.4s, v8.4s
160
- 0x06,0x99,0xe1,0x4e = frintz v6.2d, v8.2d
161
- 0x04,0x98,0xa1,0x0e = frintz v4.2s, v0.2s
162
- 0x06,0x99,0xa1,0x6e = frinti v6.4s, v8.4s
163
- 0x06,0x99,0xe1,0x6e = frinti v6.2d, v8.2d
164
- 0x04,0x98,0xa1,0x2e = frinti v4.2s, v0.2s
165
- 0x06,0xa9,0x21,0x4e = fcvtns v6.4s, v8.4s
166
- 0x06,0xa9,0x61,0x4e = fcvtns v6.2d, v8.2d
167
- 0x04,0xa8,0x21,0x0e = fcvtns v4.2s, v0.2s
168
- 0x06,0xa9,0x21,0x6e = fcvtnu v6.4s, v8.4s
169
- 0x06,0xa9,0x61,0x6e = fcvtnu v6.2d, v8.2d
170
- 0x04,0xa8,0x21,0x2e = fcvtnu v4.2s, v0.2s
171
- 0x06,0xa9,0xa1,0x4e = fcvtps v6.4s, v8.4s
172
- 0x06,0xa9,0xe1,0x4e = fcvtps v6.2d, v8.2d
173
- 0x04,0xa8,0xa1,0x0e = fcvtps v4.2s, v0.2s
174
- 0x06,0xa9,0xa1,0x6e = fcvtpu v6.4s, v8.4s
175
- 0x06,0xa9,0xe1,0x6e = fcvtpu v6.2d, v8.2d
176
- 0x04,0xa8,0xa1,0x2e = fcvtpu v4.2s, v0.2s
177
- 0x06,0xb9,0x21,0x4e = fcvtms v6.4s, v8.4s
178
- 0x06,0xb9,0x61,0x4e = fcvtms v6.2d, v8.2d
179
- 0x04,0xb8,0x21,0x0e = fcvtms v4.2s, v0.2s
180
- 0x06,0xb9,0x21,0x6e = fcvtmu v6.4s, v8.4s
181
- 0x06,0xb9,0x61,0x6e = fcvtmu v6.2d, v8.2d
182
- 0x04,0xb8,0x21,0x2e = fcvtmu v4.2s, v0.2s
183
- 0x06,0xb9,0xa1,0x4e = fcvtzs v6.4s, v8.4s
184
- 0x06,0xb9,0xe1,0x4e = fcvtzs v6.2d, v8.2d
185
- 0x04,0xb8,0xa1,0x0e = fcvtzs v4.2s, v0.2s
186
- 0x06,0xb9,0xa1,0x6e = fcvtzu v6.4s, v8.4s
187
- 0x06,0xb9,0xe1,0x6e = fcvtzu v6.2d, v8.2d
188
- 0x04,0xb8,0xa1,0x2e = fcvtzu v4.2s, v0.2s
189
- 0x06,0xc9,0x21,0x4e = fcvtas v6.4s, v8.4s
190
- 0x06,0xc9,0x61,0x4e = fcvtas v6.2d, v8.2d
191
- 0x04,0xc8,0x21,0x0e = fcvtas v4.2s, v0.2s
192
- 0x06,0xc9,0x21,0x6e = fcvtau v6.4s, v8.4s
193
- 0x06,0xc9,0x61,0x6e = fcvtau v6.2d, v8.2d
194
- 0x04,0xc8,0x21,0x2e = fcvtau v4.2s, v0.2s
195
- 0x06,0xc9,0xa1,0x4e = urecpe v6.4s, v8.4s
196
- 0x04,0xc8,0xa1,0x0e = urecpe v4.2s, v0.2s
197
- 0x06,0xc9,0xa1,0x6e = ursqrte v6.4s, v8.4s
198
- 0x04,0xc8,0xa1,0x2e = ursqrte v4.2s, v0.2s
199
- 0x06,0xd9,0x21,0x4e = scvtf v6.4s, v8.4s
200
- 0x06,0xd9,0x61,0x4e = scvtf v6.2d, v8.2d
201
- 0x04,0xd8,0x21,0x0e = scvtf v4.2s, v0.2s
202
- 0x06,0xd9,0x21,0x6e = ucvtf v6.4s, v8.4s
203
- 0x06,0xd9,0x61,0x6e = ucvtf v6.2d, v8.2d
204
- 0x04,0xd8,0x21,0x2e = ucvtf v4.2s, v0.2s
205
- 0x06,0xd9,0xa1,0x4e = frecpe v6.4s, v8.4s
206
- 0x06,0xd9,0xe1,0x4e = frecpe v6.2d, v8.2d
207
- 0x04,0xd8,0xa1,0x0e = frecpe v4.2s, v0.2s
208
- 0x06,0xd9,0xa1,0x6e = frsqrte v6.4s, v8.4s
209
- 0x06,0xd9,0xe1,0x6e = frsqrte v6.2d, v8.2d
210
- 0x04,0xd8,0xa1,0x2e = frsqrte v4.2s, v0.2s
211
- 0x06,0xf9,0xa1,0x6e = fsqrt v6.4s, v8.4s
212
- 0x06,0xf9,0xe1,0x6e = fsqrt v6.2d, v8.2d
213
- 0x04,0xf8,0xa1,0x2e = fsqrt v4.2s, v0.2s