crabstone 3.0.3 → 4.0.0

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Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +45 -42
  3. data/README.md +16 -33
  4. data/lib/crabstone.rb +5 -557
  5. data/lib/crabstone/arch.rb +37 -0
  6. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  7. data/lib/crabstone/arch/3/arm64.rb +124 -0
  8. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  9. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  10. data/lib/crabstone/arch/3/mips.rb +57 -0
  11. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  12. data/lib/crabstone/arch/3/ppc.rb +73 -0
  13. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  14. data/lib/crabstone/arch/3/sparc.rb +60 -0
  15. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  16. data/lib/crabstone/arch/3/sysz.rb +67 -0
  17. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  18. data/lib/crabstone/arch/3/x86.rb +82 -0
  19. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  20. data/lib/crabstone/arch/3/xcore.rb +59 -0
  21. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  22. data/lib/crabstone/arch/4/arm.rb +110 -0
  23. data/lib/crabstone/arch/4/arm64.rb +125 -0
  24. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  25. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  26. data/lib/crabstone/arch/4/evm.rb +20 -0
  27. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  28. data/lib/crabstone/arch/4/m680x.rb +106 -0
  29. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  30. data/lib/crabstone/arch/4/m68k.rb +129 -0
  31. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  32. data/lib/crabstone/arch/4/mips.rb +57 -0
  33. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  34. data/lib/crabstone/arch/4/ppc.rb +73 -0
  35. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  36. data/lib/crabstone/arch/4/sparc.rb +60 -0
  37. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  38. data/lib/crabstone/arch/4/sysz.rb +67 -0
  39. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  40. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  41. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  42. data/lib/crabstone/arch/4/x86.rb +91 -0
  43. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  44. data/lib/crabstone/arch/4/xcore.rb +59 -0
  45. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  46. data/lib/crabstone/arch/extension.rb +27 -0
  47. data/lib/crabstone/arch/register.rb +36 -0
  48. data/lib/crabstone/binding.rb +60 -0
  49. data/lib/crabstone/binding/3/detail.rb +36 -0
  50. data/lib/crabstone/binding/3/instruction.rb +23 -0
  51. data/lib/crabstone/binding/4/detail.rb +40 -0
  52. data/lib/crabstone/binding/4/instruction.rb +23 -0
  53. data/lib/crabstone/binding/structs.rb +32 -0
  54. data/lib/crabstone/constants.rb +110 -0
  55. data/lib/crabstone/cs_version.rb +49 -0
  56. data/lib/crabstone/disassembler.rb +153 -0
  57. data/lib/crabstone/error.rb +60 -0
  58. data/lib/crabstone/instruction.rb +183 -0
  59. data/lib/crabstone/version.rb +5 -0
  60. metadata +128 -324
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
data/test/MC/ARM/crc32-thumb.s.cs DELETED
@@ -1,7 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
2
- 0xc1,0xfa,0x82,0xf0 = crc32b r0, r1, r2
3
- 0xc1,0xfa,0x92,0xf0 = crc32h r0, r1, r2
4
- 0xc1,0xfa,0xa2,0xf0 = crc32w r0, r1, r2
5
- 0xd1,0xfa,0x82,0xf0 = crc32cb r0, r1, r2
6
- 0xd1,0xfa,0x92,0xf0 = crc32ch r0, r1, r2
7
- 0xd1,0xfa,0xa2,0xf0 = crc32cw r0, r1, r2
data/test/MC/ARM/crc32.s.cs DELETED
@@ -1,7 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
2
- 0x42,0x00,0x01,0xe1 = crc32b r0, r1, r2
3
- 0x42,0x00,0x21,0xe1 = crc32h r0, r1, r2
4
- 0x42,0x00,0x41,0xe1 = crc32w r0, r1, r2
5
- 0x42,0x02,0x01,0xe1 = crc32cb r0, r1, r2
6
- 0x42,0x02,0x21,0xe1 = crc32ch r0, r1, r2
7
- 0x42,0x02,0x41,0xe1 = crc32cw r0, r1, r2
data/test/MC/ARM/dot-req.s.cs DELETED
@@ -1,3 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x05,0xb0,0xa0,0xe1 = mov r11, r5
3
- 0x06,0x10,0xa0,0xe1 = mov r1, r6
data/test/MC/ARM/fp-armv8.s.cs DELETED
@@ -1,52 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
2
- 0xe0,0x3b,0xb2,0xee = vcvtt.f64.f16 d3, s1
3
- 0xcc,0x2b,0xf3,0xee = vcvtt.f16.f64 s5, d12
4
- 0x60,0x3b,0xb2,0xee = vcvtb.f64.f16 d3, s1
5
- 0x41,0x2b,0xb3,0xee = vcvtb.f16.f64 s4, d1
6
- 0xe0,0x3b,0xb2,0xae = vcvttge.f64.f16 d3, s1
7
- 0xcc,0x2b,0xf3,0xce = vcvttgt.f16.f64 s5, d12
8
- 0x60,0x3b,0xb2,0x0e = vcvtbeq.f64.f16 d3, s1
9
- 0x41,0x2b,0xb3,0xbe = vcvtblt.f16.f64 s4, d1
10
- 0xe1,0x1a,0xbc,0xfe = vcvta.s32.f32 s2, s3
11
- 0xc3,0x1b,0xbc,0xfe = vcvta.s32.f64 s2, d3
12
- 0xeb,0x3a,0xbd,0xfe = vcvtn.s32.f32 s6, s23
13
- 0xe7,0x3b,0xbd,0xfe = vcvtn.s32.f64 s6, d23
14
- 0xc2,0x0a,0xbe,0xfe = vcvtp.s32.f32 s0, s4
15
- 0xc4,0x0b,0xbe,0xfe = vcvtp.s32.f64 s0, d4
16
- 0xc4,0x8a,0xff,0xfe = vcvtm.s32.f32 s17, s8
17
- 0xc8,0x8b,0xff,0xfe = vcvtm.s32.f64 s17, d8
18
- 0x61,0x1a,0xbc,0xfe = vcvta.u32.f32 s2, s3
19
- 0x43,0x1b,0xbc,0xfe = vcvta.u32.f64 s2, d3
20
- 0x6b,0x3a,0xbd,0xfe = vcvtn.u32.f32 s6, s23
21
- 0x67,0x3b,0xbd,0xfe = vcvtn.u32.f64 s6, d23
22
- 0x42,0x0a,0xbe,0xfe = vcvtp.u32.f32 s0, s4
23
- 0x44,0x0b,0xbe,0xfe = vcvtp.u32.f64 s0, d4
24
- 0x44,0x8a,0xff,0xfe = vcvtm.u32.f32 s17, s8
25
- 0x48,0x8b,0xff,0xfe = vcvtm.u32.f64 s17, d8
26
- 0xab,0x2a,0x20,0xfe = vselge.f32 s4, s1, s23
27
- 0xa7,0xeb,0x6f,0xfe = vselge.f64 d30, d31, d23
28
- 0x80,0x0a,0x30,0xfe = vselgt.f32 s0, s1, s0
29
- 0x24,0x5b,0x3a,0xfe = vselgt.f64 d5, d10, d20
30
- 0x2b,0xfa,0x0e,0xfe = vseleq.f32 s30, s28, s23
31
- 0x08,0x2b,0x04,0xfe = vseleq.f64 d2, d4, d8
32
- 0x07,0xaa,0x58,0xfe = vselvs.f32 s21, s16, s14
33
- 0x2f,0x0b,0x11,0xfe = vselvs.f64 d0, d1, d31
34
- 0x00,0x2a,0xc6,0xfe = vmaxnm.f32 s5, s12, s0
35
- 0xae,0x5b,0x86,0xfe = vmaxnm.f64 d5, d22, d30
36
- 0x46,0x0a,0x80,0xfe = vminnm.f32 s0, s0, s12
37
- 0x49,0x4b,0x86,0xfe = vminnm.f64 d4, d6, d9
38
- 0xcc,0x3b,0xb6,0xae = vrintzge.f64 d3, d12
39
- 0xcc,0x1a,0xf6,0xee = vrintz.f32 s3, s24
40
- 0x40,0x5b,0xb6,0xbe = vrintrlt.f64 d5, d0
41
- 0x64,0x0a,0xb6,0xee = vrintr.f32 s0, s9
42
- 0x6e,0xcb,0xf7,0x0e = vrintxeq.f64 d28, d30
43
- 0x47,0x5a,0xb7,0x6e = vrintxvs.f32 s10, s14
44
- 0x44,0x3b,0xb8,0xfe = vrinta.f64 d3, d4
45
- 0x60,0x6a,0xb8,0xfe = vrinta.f32 s12, s1
46
- 0x44,0x3b,0xb9,0xfe = vrintn.f64 d3, d4
47
- 0x60,0x6a,0xb9,0xfe = vrintn.f32 s12, s1
48
- 0x44,0x3b,0xba,0xfe = vrintp.f64 d3, d4
49
- 0x60,0x6a,0xba,0xfe = vrintp.f32 s12, s1
50
- 0x44,0x3b,0xbb,0xfe = vrintm.f64 d3, d4
51
- 0x60,0x6a,0xbb,0xfe = vrintm.f32 s12, s1
52
- 0x10,0xda,0xf5,0xee = vmrs sp, mvfr2
data/test/MC/ARM/idiv-thumb.s.cs DELETED
@@ -1,3 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB, None
2
- 0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3
3
- 0xb4,0xfb,0xf5,0xf3 = udiv r3, r4, r5
data/test/MC/ARM/idiv.s.cs DELETED
@@ -1,3 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3
3
- 0x14,0xf5,0x33,0xe7 = udiv r3, r4, r5
data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs DELETED
@@ -1,15 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
2
- 0xd4,0xe8,0xcf,0x3f = ldaexb r3, [r4]
3
- 0xd5,0xe8,0xdf,0x2f = ldaexh r2, [r5]
4
- 0xd7,0xe8,0xef,0x1f = ldaex r1, [r7]
5
- 0xd8,0xe8,0xff,0x67 = ldaexd r6, r7, [r8]
6
- 0xc4,0xe8,0xc1,0x3f = stlexb r1, r3, [r4]
7
- 0xc5,0xe8,0xd4,0x2f = stlexh r4, r2, [r5]
8
- 0xc7,0xe8,0xe2,0x1f = stlex r2, r1, [r7]
9
- 0xc8,0xe8,0xf6,0x23 = stlexd r6, r2, r3, [r8]
10
- 0xd6,0xe8,0xaf,0x5f = lda r5, [r6]
11
- 0xd6,0xe8,0x8f,0x5f = ldab r5, [r6]
12
- 0xd9,0xe8,0x9f,0xcf = ldah r12, [r9]
13
- 0xc0,0xe8,0xaf,0x3f = stl r3, [r0]
14
- 0xc1,0xe8,0x8f,0x2f = stlb r2, [r1]
15
- 0xc3,0xe8,0x9f,0x2f = stlh r2, [r3]
data/test/MC/ARM/load-store-acquire-release-v8.s.cs DELETED
@@ -1,15 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
2
- 0x9f,0x3e,0xd4,0xe1 = ldaexb r3, [r4]
3
- 0x9f,0x2e,0xf5,0xe1 = ldaexh r2, [r5]
4
- 0x9f,0x1e,0x97,0xe1 = ldaex r1, [r7]
5
- 0x9f,0x6e,0xb8,0xe1 = ldaexd r6, r7, [r8]
6
- 0x93,0x1e,0xc4,0xe1 = stlexb r1, r3, [r4]
7
- 0x92,0x4e,0xe5,0xe1 = stlexh r4, r2, [r5]
8
- 0x91,0x2e,0x87,0xe1 = stlex r2, r1, [r7]
9
- 0x92,0x6e,0xa8,0xe1 = stlexd r6, r2, r3, [r8]
10
- 0x9f,0x5c,0x96,0xe1 = lda r5, [r6]
11
- 0x9f,0x5c,0xd6,0xe1 = ldab r5, [r6]
12
- 0x9f,0xcc,0xf9,0xe1 = ldah r12, [r9]
13
- 0x93,0xfc,0x80,0xe1 = stl r3, [r0]
14
- 0x92,0xfc,0xc1,0xe1 = stlb r2, [r1]
15
- 0x92,0xfc,0xe3,0xe1 = stlh r2, [r3]
data/test/MC/ARM/mode-switch.s.cs DELETED
@@ -1,7 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB, None
2
- 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1
3
- 0x01,0x00,0x80,0xe0 = add r0, r0, r1
4
- 0x40,0x18 = adds r0, r0, r1
5
- 0x01,0x00,0x80,0xe0 = add r0, r0, r1
6
- 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1
7
- 0x40,0x18 = adds r0, r0, r1
data/test/MC/ARM/neon-abs-encoding.s.cs DELETED
@@ -1,15 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x20,0x03,0xf1,0xf3 = vabs.s8 d16, d16
3
- 0x20,0x03,0xf5,0xf3 = vabs.s16 d16, d16
4
- 0x20,0x03,0xf9,0xf3 = vabs.s32 d16, d16
5
- 0x20,0x07,0xf9,0xf3 = vabs.f32 d16, d16
6
- 0x60,0x03,0xf1,0xf3 = vabs.s8 q8, q8
7
- 0x60,0x03,0xf5,0xf3 = vabs.s16 q8, q8
8
- 0x60,0x03,0xf9,0xf3 = vabs.s32 q8, q8
9
- 0x60,0x07,0xf9,0xf3 = vabs.f32 q8, q8
10
- 0x20,0x07,0xf0,0xf3 = vqabs.s8 d16, d16
11
- 0x20,0x07,0xf4,0xf3 = vqabs.s16 d16, d16
12
- 0x20,0x07,0xf8,0xf3 = vqabs.s32 d16, d16
13
- 0x60,0x07,0xf0,0xf3 = vqabs.s8 q8, q8
14
- 0x60,0x07,0xf4,0xf3 = vqabs.s16 q8, q8
15
- 0x60,0x07,0xf8,0xf3 = vqabs.s32 q8, q8
data/test/MC/ARM/neon-absdiff-encoding.s.cs DELETED
@@ -1,39 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xa1,0x07,0x40,0xf2 = vabd.s8 d16, d16, d17
3
- 0xa1,0x07,0x50,0xf2 = vabd.s16 d16, d16, d17
4
- 0xa1,0x07,0x60,0xf2 = vabd.s32 d16, d16, d17
5
- 0xa1,0x07,0x40,0xf3 = vabd.u8 d16, d16, d17
6
- 0xa1,0x07,0x50,0xf3 = vabd.u16 d16, d16, d17
7
- 0xa1,0x07,0x60,0xf3 = vabd.u32 d16, d16, d17
8
- 0xa1,0x0d,0x60,0xf3 = vabd.f32 d16, d16, d17
9
- 0xe2,0x07,0x40,0xf2 = vabd.s8 q8, q8, q9
10
- 0xe2,0x07,0x50,0xf2 = vabd.s16 q8, q8, q9
11
- 0xe2,0x07,0x60,0xf2 = vabd.s32 q8, q8, q9
12
- 0xe2,0x07,0x40,0xf3 = vabd.u8 q8, q8, q9
13
- 0xe2,0x07,0x50,0xf3 = vabd.u16 q8, q8, q9
14
- 0xe2,0x07,0x60,0xf3 = vabd.u32 q8, q8, q9
15
- 0xe2,0x0d,0x60,0xf3 = vabd.f32 q8, q8, q9
16
- 0xa1,0x07,0xc0,0xf2 = vabdl.s8 q8, d16, d17
17
- 0xa1,0x07,0xd0,0xf2 = vabdl.s16 q8, d16, d17
18
- 0xa1,0x07,0xe0,0xf2 = vabdl.s32 q8, d16, d17
19
- 0xa1,0x07,0xc0,0xf3 = vabdl.u8 q8, d16, d17
20
- 0xa1,0x07,0xd0,0xf3 = vabdl.u16 q8, d16, d17
21
- 0xa1,0x07,0xe0,0xf3 = vabdl.u32 q8, d16, d17
22
- 0xb1,0x07,0x42,0xf2 = vaba.s8 d16, d18, d17
23
- 0xb1,0x07,0x52,0xf2 = vaba.s16 d16, d18, d17
24
- 0xb1,0x07,0x62,0xf2 = vaba.s32 d16, d18, d17
25
- 0xb1,0x07,0x42,0xf3 = vaba.u8 d16, d18, d17
26
- 0xb1,0x07,0x52,0xf3 = vaba.u16 d16, d18, d17
27
- 0xb1,0x07,0x62,0xf3 = vaba.u32 d16, d18, d17
28
- 0xf4,0x27,0x40,0xf2 = vaba.s8 q9, q8, q10
29
- 0xf4,0x27,0x50,0xf2 = vaba.s16 q9, q8, q10
30
- 0xf4,0x27,0x60,0xf2 = vaba.s32 q9, q8, q10
31
- 0xf4,0x27,0x40,0xf3 = vaba.u8 q9, q8, q10
32
- 0xf4,0x27,0x50,0xf3 = vaba.u16 q9, q8, q10
33
- 0xf4,0x27,0x60,0xf3 = vaba.u32 q9, q8, q10
34
- 0xa2,0x05,0xc3,0xf2 = vabal.s8 q8, d19, d18
35
- 0xa2,0x05,0xd3,0xf2 = vabal.s16 q8, d19, d18
36
- 0xa2,0x05,0xe3,0xf2 = vabal.s32 q8, d19, d18
37
- 0xa2,0x05,0xc3,0xf3 = vabal.u8 q8, d19, d18
38
- 0xa2,0x05,0xd3,0xf3 = vabal.u16 q8, d19, d18
39
- 0xa2,0x05,0xe3,0xf3 = vabal.u32 q8, d19, d18
data/test/MC/ARM/neon-add-encoding.s.cs DELETED
@@ -1,119 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xa0,0x08,0x41,0xf2 = vadd.i8 d16, d17, d16
3
- 0xa0,0x08,0x51,0xf2 = vadd.i16 d16, d17, d16
4
- 0xa0,0x08,0x71,0xf2 = vadd.i64 d16, d17, d16
5
- 0xa0,0x08,0x61,0xf2 = vadd.i32 d16, d17, d16
6
- 0xa1,0x0d,0x40,0xf2 = vadd.f32 d16, d16, d17
7
- 0xe2,0x0d,0x40,0xf2 = vadd.f32 q8, q8, q9
8
- 0xa0,0x00,0xc1,0xf2 = vaddl.s8 q8, d17, d16
9
- 0xa0,0x00,0xd1,0xf2 = vaddl.s16 q8, d17, d16
10
- 0xa0,0x00,0xe1,0xf2 = vaddl.s32 q8, d17, d16
11
- 0xa0,0x00,0xc1,0xf3 = vaddl.u8 q8, d17, d16
12
- 0xa0,0x00,0xd1,0xf3 = vaddl.u16 q8, d17, d16
13
- 0xa0,0x00,0xe1,0xf3 = vaddl.u32 q8, d17, d16
14
- 0xa2,0x01,0xc0,0xf2 = vaddw.s8 q8, q8, d18
15
- 0xa2,0x01,0xd0,0xf2 = vaddw.s16 q8, q8, d18
16
- 0xa2,0x01,0xe0,0xf2 = vaddw.s32 q8, q8, d18
17
- 0xa2,0x01,0xc0,0xf3 = vaddw.u8 q8, q8, d18
18
- 0xa2,0x01,0xd0,0xf3 = vaddw.u16 q8, q8, d18
19
- 0xa2,0x01,0xe0,0xf3 = vaddw.u32 q8, q8, d18
20
- 0xa1,0x00,0x40,0xf2 = vhadd.s8 d16, d16, d17
21
- 0xa1,0x00,0x50,0xf2 = vhadd.s16 d16, d16, d17
22
- 0xa1,0x00,0x60,0xf2 = vhadd.s32 d16, d16, d17
23
- 0xa1,0x00,0x40,0xf3 = vhadd.u8 d16, d16, d17
24
- 0xa1,0x00,0x50,0xf3 = vhadd.u16 d16, d16, d17
25
- 0xa1,0x00,0x60,0xf3 = vhadd.u32 d16, d16, d17
26
- 0xe2,0x00,0x40,0xf2 = vhadd.s8 q8, q8, q9
27
- 0xe2,0x00,0x50,0xf2 = vhadd.s16 q8, q8, q9
28
- 0xe2,0x00,0x60,0xf2 = vhadd.s32 q8, q8, q9
29
- 0xe2,0x00,0x40,0xf3 = vhadd.u8 q8, q8, q9
30
- 0xe2,0x00,0x50,0xf3 = vhadd.u16 q8, q8, q9
31
- 0xe2,0x00,0x60,0xf3 = vhadd.u32 q8, q8, q9
32
- 0x28,0xb0,0x0b,0xf2 = vhadd.s8 d11, d11, d24
33
- 0x27,0xc0,0x1c,0xf2 = vhadd.s16 d12, d12, d23
34
- 0x26,0xd0,0x2d,0xf2 = vhadd.s32 d13, d13, d22
35
- 0x25,0xe0,0x0e,0xf3 = vhadd.u8 d14, d14, d21
36
- 0x24,0xf0,0x1f,0xf3 = vhadd.u16 d15, d15, d20
37
- 0xa3,0x00,0x60,0xf3 = vhadd.u32 d16, d16, d19
38
- 0x68,0x20,0x02,0xf2 = vhadd.s8 q1, q1, q12
39
- 0x66,0x40,0x14,0xf2 = vhadd.s16 q2, q2, q11
40
- 0x64,0x60,0x26,0xf2 = vhadd.s32 q3, q3, q10
41
- 0x62,0x80,0x08,0xf3 = vhadd.u8 q4, q4, q9
42
- 0x60,0xa0,0x1a,0xf3 = vhadd.u16 q5, q5, q8
43
- 0x4e,0xc0,0x2c,0xf3 = vhadd.u32 q6, q6, q7
44
- 0xa1,0x01,0x40,0xf2 = vrhadd.s8 d16, d16, d17
45
- 0xa1,0x01,0x50,0xf2 = vrhadd.s16 d16, d16, d17
46
- 0xa1,0x01,0x60,0xf2 = vrhadd.s32 d16, d16, d17
47
- 0xa1,0x01,0x40,0xf3 = vrhadd.u8 d16, d16, d17
48
- 0xa1,0x01,0x50,0xf3 = vrhadd.u16 d16, d16, d17
49
- 0xa1,0x01,0x60,0xf3 = vrhadd.u32 d16, d16, d17
50
- 0xe2,0x01,0x40,0xf2 = vrhadd.s8 q8, q8, q9
51
- 0xe2,0x01,0x50,0xf2 = vrhadd.s16 q8, q8, q9
52
- 0xe2,0x01,0x60,0xf2 = vrhadd.s32 q8, q8, q9
53
- 0xe2,0x01,0x40,0xf3 = vrhadd.u8 q8, q8, q9
54
- 0xe2,0x01,0x50,0xf3 = vrhadd.u16 q8, q8, q9
55
- 0xe2,0x01,0x60,0xf3 = vrhadd.u32 q8, q8, q9
56
- 0xa1,0x01,0x40,0xf2 = vrhadd.s8 d16, d16, d17
57
- 0xa1,0x01,0x50,0xf2 = vrhadd.s16 d16, d16, d17
58
- 0xa1,0x01,0x60,0xf2 = vrhadd.s32 d16, d16, d17
59
- 0xa1,0x01,0x40,0xf3 = vrhadd.u8 d16, d16, d17
60
- 0xa1,0x01,0x50,0xf3 = vrhadd.u16 d16, d16, d17
61
- 0xa1,0x01,0x60,0xf3 = vrhadd.u32 d16, d16, d17
62
- 0xe2,0x01,0x40,0xf2 = vrhadd.s8 q8, q8, q9
63
- 0xe2,0x01,0x50,0xf2 = vrhadd.s16 q8, q8, q9
64
- 0xe2,0x01,0x60,0xf2 = vrhadd.s32 q8, q8, q9
65
- 0xe2,0x01,0x40,0xf3 = vrhadd.u8 q8, q8, q9
66
- 0xe2,0x01,0x50,0xf3 = vrhadd.u16 q8, q8, q9
67
- 0xe2,0x01,0x60,0xf3 = vrhadd.u32 q8, q8, q9
68
- 0xb1,0x00,0x40,0xf2 = vqadd.s8 d16, d16, d17
69
- 0xb1,0x00,0x50,0xf2 = vqadd.s16 d16, d16, d17
70
- 0xb1,0x00,0x60,0xf2 = vqadd.s32 d16, d16, d17
71
- 0xb1,0x00,0x70,0xf2 = vqadd.s64 d16, d16, d17
72
- 0xb1,0x00,0x40,0xf3 = vqadd.u8 d16, d16, d17
73
- 0xb1,0x00,0x50,0xf3 = vqadd.u16 d16, d16, d17
74
- 0xb1,0x00,0x60,0xf3 = vqadd.u32 d16, d16, d17
75
- 0xb1,0x00,0x70,0xf3 = vqadd.u64 d16, d16, d17
76
- 0xf2,0x00,0x40,0xf2 = vqadd.s8 q8, q8, q9
77
- 0xf2,0x00,0x50,0xf2 = vqadd.s16 q8, q8, q9
78
- 0xf2,0x00,0x60,0xf2 = vqadd.s32 q8, q8, q9
79
- 0xf2,0x00,0x70,0xf2 = vqadd.s64 q8, q8, q9
80
- 0xf2,0x00,0x40,0xf3 = vqadd.u8 q8, q8, q9
81
- 0xf2,0x00,0x50,0xf3 = vqadd.u16 q8, q8, q9
82
- 0xf2,0x00,0x60,0xf3 = vqadd.u32 q8, q8, q9
83
- 0xf2,0x00,0x70,0xf3 = vqadd.u64 q8, q8, q9
84
- 0xb1,0x00,0x40,0xf2 = vqadd.s8 d16, d16, d17
85
- 0xb1,0x00,0x50,0xf2 = vqadd.s16 d16, d16, d17
86
- 0xb1,0x00,0x60,0xf2 = vqadd.s32 d16, d16, d17
87
- 0xb1,0x00,0x70,0xf2 = vqadd.s64 d16, d16, d17
88
- 0xb1,0x00,0x40,0xf3 = vqadd.u8 d16, d16, d17
89
- 0xb1,0x00,0x50,0xf3 = vqadd.u16 d16, d16, d17
90
- 0xb1,0x00,0x60,0xf3 = vqadd.u32 d16, d16, d17
91
- 0xb1,0x00,0x70,0xf3 = vqadd.u64 d16, d16, d17
92
- 0xf2,0x00,0x40,0xf2 = vqadd.s8 q8, q8, q9
93
- 0xf2,0x00,0x50,0xf2 = vqadd.s16 q8, q8, q9
94
- 0xf2,0x00,0x60,0xf2 = vqadd.s32 q8, q8, q9
95
- 0xf2,0x00,0x70,0xf2 = vqadd.s64 q8, q8, q9
96
- 0xf2,0x00,0x40,0xf3 = vqadd.u8 q8, q8, q9
97
- 0xf2,0x00,0x50,0xf3 = vqadd.u16 q8, q8, q9
98
- 0xf2,0x00,0x60,0xf3 = vqadd.u32 q8, q8, q9
99
- 0xf2,0x00,0x70,0xf3 = vqadd.u64 q8, q8, q9
100
- 0xa2,0x04,0xc0,0xf2 = vaddhn.i16 d16, q8, q9
101
- 0xa2,0x04,0xd0,0xf2 = vaddhn.i32 d16, q8, q9
102
- 0xa2,0x04,0xe0,0xf2 = vaddhn.i64 d16, q8, q9
103
- 0xa2,0x04,0xc0,0xf3 = vraddhn.i16 d16, q8, q9
104
- 0xa2,0x04,0xd0,0xf3 = vraddhn.i32 d16, q8, q9
105
- 0xa2,0x04,0xe0,0xf3 = vraddhn.i64 d16, q8, q9
106
- 0x05,0x68,0x06,0xf2 = vadd.i8 d6, d6, d5
107
- 0x01,0x78,0x17,0xf2 = vadd.i16 d7, d7, d1
108
- 0x02,0x88,0x28,0xf2 = vadd.i32 d8, d8, d2
109
- 0x03,0x98,0x39,0xf2 = vadd.i64 d9, d9, d3
110
- 0x4a,0xc8,0x0c,0xf2 = vadd.i8 q6, q6, q5
111
- 0x42,0xe8,0x1e,0xf2 = vadd.i16 q7, q7, q1
112
- 0xc4,0x08,0x60,0xf2 = vadd.i32 q8, q8, q2
113
- 0xc6,0x28,0x72,0xf2 = vadd.i64 q9, q9, q3
114
- 0x05,0xc1,0x8c,0xf2 = vaddw.s8 q6, q6, d5
115
- 0x01,0xe1,0x9e,0xf2 = vaddw.s16 q7, q7, d1
116
- 0x82,0x01,0xe0,0xf2 = vaddw.s32 q8, q8, d2
117
- 0x05,0xc1,0x8c,0xf3 = vaddw.u8 q6, q6, d5
118
- 0x01,0xe1,0x9e,0xf3 = vaddw.u16 q7, q7, d1
119
- 0x82,0x01,0xe0,0xf3 = vaddw.u32 q8, q8, d2
data/test/MC/ARM/neon-bitcount-encoding.s.cs DELETED
@@ -1,15 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x20,0x05,0xf0,0xf3 = vcnt.8 d16, d16
3
- 0x60,0x05,0xf0,0xf3 = vcnt.8 q8, q8
4
- 0xa0,0x04,0xf0,0xf3 = vclz.i8 d16, d16
5
- 0xa0,0x04,0xf4,0xf3 = vclz.i16 d16, d16
6
- 0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16
7
- 0xe0,0x04,0xf0,0xf3 = vclz.i8 q8, q8
8
- 0xe0,0x04,0xf4,0xf3 = vclz.i16 q8, q8
9
- 0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8
10
- 0x20,0x04,0xf0,0xf3 = vcls.s8 d16, d16
11
- 0x20,0x04,0xf4,0xf3 = vcls.s16 d16, d16
12
- 0x20,0x04,0xf8,0xf3 = vcls.s32 d16, d16
13
- 0x60,0x04,0xf0,0xf3 = vcls.s8 q8, q8
14
- 0x60,0x04,0xf4,0xf3 = vcls.s16 q8, q8
15
- 0x60,0x04,0xf8,0xf3 = vcls.s32 q8, q8
data/test/MC/ARM/neon-bitwise-encoding.s.cs DELETED
@@ -1,126 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xb0,0x01,0x41,0xf2 = vand d16, d17, d16
3
- 0xf2,0x01,0x40,0xf2 = vand q8, q8, q9
4
- 0xb0,0x01,0x41,0xf3 = veor d16, d17, d16
5
- 0xf2,0x01,0x40,0xf3 = veor q8, q8, q9
6
- 0xb0,0x01,0x61,0xf2 = vorr d16, d17, d16
7
- 0xf2,0x01,0x60,0xf2 = vorr q8, q8, q9
8
- 0x11,0x07,0xc0,0xf2 = vorr.i32 d16, #0x1000000
9
- 0x51,0x07,0xc0,0xf2 = vorr.i32 q8, #0x1000000
10
- 0x50,0x01,0xc0,0xf2 = vorr.i32 q8, #0
11
- 0xb0,0x01,0x51,0xf2 = vbic d16, d17, d16
12
- 0xf2,0x01,0x50,0xf2 = vbic q8, q8, q9
13
- 0x3f,0x07,0xc7,0xf3 = vbic.i32 d16, #0xff000000
14
- 0x7f,0x07,0xc7,0xf3 = vbic.i32 q8, #0xff000000
15
- 0xf6,0x41,0x54,0xf2 = vbic q10, q10, q11
16
- 0x11,0x91,0x19,0xf2 = vbic d9, d9, d1
17
- 0xb0,0x01,0x71,0xf2 = vorn d16, d17, d16
18
- 0xf2,0x01,0x70,0xf2 = vorn q8, q8, q9
19
- 0xa0,0x05,0xf0,0xf3 = vmvn d16, d16
20
- 0xe0,0x05,0xf0,0xf3 = vmvn q8, q8
21
- 0xb0,0x21,0x51,0xf3 = vbsl d18, d17, d16
22
- 0xf2,0x01,0x54,0xf3 = vbsl q8, q10, q9
23
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
24
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
25
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
26
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
27
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
28
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
29
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
30
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
31
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
32
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
33
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
34
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
35
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
36
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
37
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
38
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
39
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
40
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
41
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
42
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
43
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
44
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
45
- 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
46
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
47
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
48
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
49
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
50
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
51
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
52
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
53
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
54
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
55
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
56
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
57
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
58
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
59
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
60
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
61
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
62
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
63
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
64
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
65
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
66
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
67
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
68
- 0x13,0x41,0x07,0xf2 = vand d4, d7, d3
69
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
70
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
71
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
72
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
73
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
74
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
75
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
76
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
77
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
78
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
79
- 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3
80
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
81
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
82
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
83
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
84
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
85
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
86
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
87
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
88
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
89
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
90
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
91
- 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3
92
- 0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5
93
- 0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5
94
- 0x52,0xe1,0x0e,0xf2 = vand q7, q7, q1
95
- 0xd4,0x01,0x40,0xf2 = vand q8, q8, q2
96
- 0xd4,0x01,0x40,0xf2 = vand q8, q8, q2
97
- 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5
98
- 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5
99
- 0x52,0xe1,0x0e,0xf3 = veor q7, q7, q1
100
- 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2
101
- 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2
102
- 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5
103
- 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5
104
- 0x52,0xe1,0x0e,0xf3 = veor q7, q7, q1
105
- 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2
106
- 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2
107
- 0x4a,0xa2,0xb5,0xf3 = vclt.s16 q5, q5, #0
108
- 0x05,0x52,0xb5,0xf3 = vclt.s16 d5, d5, #0
109
- 0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3
110
- 0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3
111
- 0x46,0xa3,0x1a,0xf2 = vcgt.s16 q5, q5, q3
112
- 0x03,0x53,0x15,0xf2 = vcgt.s16 d5, d5, d3
113
- 0x56,0xa3,0x1a,0xf2 = vcge.s16 q5, q5, q3
114
- 0x13,0x53,0x15,0xf2 = vcge.s16 d5, d5, d3
115
- 0x4a,0xa0,0xb5,0xf3 = vcgt.s16 q5, q5, #0
116
- 0x05,0x50,0xb5,0xf3 = vcgt.s16 d5, d5, #0
117
- 0xca,0xa0,0xb5,0xf3 = vcge.s16 q5, q5, #0
118
- 0x85,0x50,0xb5,0xf3 = vcge.s16 d5, d5, #0
119
- 0x4a,0xa1,0xb5,0xf3 = vceq.i16 q5, q5, #0
120
- 0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0
121
- 0xca,0xa1,0xb5,0xf3 = vcle.s16 q5, q5, #0
122
- 0x85,0x51,0xb5,0xf3 = vcle.s16 d5, d5, #0
123
- 0x3e,0x5e,0x05,0xf3 = vacge.f32 d5, d5, d30
124
- 0x56,0xae,0x0a,0xf3 = vacge.f32 q5, q5, q3
125
- 0x3e,0x5e,0x25,0xf3 = vacgt.f32 d5, d5, d30
126
- 0x56,0xae,0x2a,0xf3 = vacgt.f32 q5, q5, q3