crabstone 3.0.3 → 4.0.0

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Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +45 -42
  3. data/README.md +16 -33
  4. data/lib/crabstone.rb +5 -557
  5. data/lib/crabstone/arch.rb +37 -0
  6. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  7. data/lib/crabstone/arch/3/arm64.rb +124 -0
  8. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  9. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  10. data/lib/crabstone/arch/3/mips.rb +57 -0
  11. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  12. data/lib/crabstone/arch/3/ppc.rb +73 -0
  13. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  14. data/lib/crabstone/arch/3/sparc.rb +60 -0
  15. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  16. data/lib/crabstone/arch/3/sysz.rb +67 -0
  17. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  18. data/lib/crabstone/arch/3/x86.rb +82 -0
  19. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  20. data/lib/crabstone/arch/3/xcore.rb +59 -0
  21. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  22. data/lib/crabstone/arch/4/arm.rb +110 -0
  23. data/lib/crabstone/arch/4/arm64.rb +125 -0
  24. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  25. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  26. data/lib/crabstone/arch/4/evm.rb +20 -0
  27. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  28. data/lib/crabstone/arch/4/m680x.rb +106 -0
  29. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  30. data/lib/crabstone/arch/4/m68k.rb +129 -0
  31. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  32. data/lib/crabstone/arch/4/mips.rb +57 -0
  33. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  34. data/lib/crabstone/arch/4/ppc.rb +73 -0
  35. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  36. data/lib/crabstone/arch/4/sparc.rb +60 -0
  37. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  38. data/lib/crabstone/arch/4/sysz.rb +67 -0
  39. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  40. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  41. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  42. data/lib/crabstone/arch/4/x86.rb +91 -0
  43. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  44. data/lib/crabstone/arch/4/xcore.rb +59 -0
  45. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  46. data/lib/crabstone/arch/extension.rb +27 -0
  47. data/lib/crabstone/arch/register.rb +36 -0
  48. data/lib/crabstone/binding.rb +60 -0
  49. data/lib/crabstone/binding/3/detail.rb +36 -0
  50. data/lib/crabstone/binding/3/instruction.rb +23 -0
  51. data/lib/crabstone/binding/4/detail.rb +40 -0
  52. data/lib/crabstone/binding/4/instruction.rb +23 -0
  53. data/lib/crabstone/binding/structs.rb +32 -0
  54. data/lib/crabstone/constants.rb +110 -0
  55. data/lib/crabstone/cs_version.rb +49 -0
  56. data/lib/crabstone/disassembler.rb +153 -0
  57. data/lib/crabstone/error.rb +60 -0
  58. data/lib/crabstone/instruction.rb +183 -0
  59. data/lib/crabstone/version.rb +5 -0
  60. metadata +128 -324
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
data/test/MC/ARM/thumb2-pldw.s.cs DELETED
@@ -1,2 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB,
2
- 0xb0,0xf8,0x01,0xf1 = pldw [r0, #257]
data/test/MC/ARM/vfp4-thumb.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB,
2
- 0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17
3
- 0xa2,0xee,0x00,0x1a = vfma.f32 s2, s4, s0
4
- 0x42,0xef,0xb1,0x0c = vfma.f32 d16, d18, d17
5
- 0x08,0xef,0x50,0x4c = vfma.f32 q2, q4, q0
6
- 0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17
7
- 0x92,0xee,0x40,0x1a = vfnma.f32 s2, s4, s0
8
- 0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17
9
- 0xa2,0xee,0x40,0x1a = vfms.f32 s2, s4, s0
10
- 0x62,0xef,0xb1,0x0c = vfms.f32 d16, d18, d17
11
- 0x28,0xef,0x50,0x4c = vfms.f32 q2, q4, q0
12
- 0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17
13
- 0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0
data/test/MC/ARM/vfp4.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17
3
- 0x00,0x1a,0xa2,0xee = vfma.f32 s2, s4, s0
4
- 0xb1,0x0c,0x42,0xf2 = vfma.f32 d16, d18, d17
5
- 0x50,0x4c,0x08,0xf2 = vfma.f32 q2, q4, q0
6
- 0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17
7
- 0x40,0x1a,0x92,0xee = vfnma.f32 s2, s4, s0
8
- 0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17
9
- 0x40,0x1a,0xa2,0xee = vfms.f32 s2, s4, s0
10
- 0xb1,0x0c,0x62,0xf2 = vfms.f32 d16, d18, d17
11
- 0x50,0x4c,0x28,0xf2 = vfms.f32 q2, q4, q0
12
- 0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17
13
- 0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0
data/test/MC/ARM/vpush-vpop-thumb.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_THUMB,
2
- 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12}
3
- 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12}
4
- 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12}
5
- 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12}
6
- 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12}
7
- 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12}
8
- 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12}
9
- 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12}
data/test/MC/ARM/vpush-vpop.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_ARM, CS_MODE_ARM, None
2
- 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12}
3
- 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12}
4
- 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12}
5
- 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12}
6
- 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12}
7
- 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12}
8
- 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12}
9
- 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12}
data/test/MC/Mips/hilo-addressing.s.cs DELETED
@@ -1,4 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x3c,0x04,0xde,0xae = lui $4, %hi(addr)
3
- 0x03,0xe0,0x00,0x08 = jr $31
4
- 0x80,0x82,0xbe,0xef = lb $2, %lo(addr)($4)
data/test/MC/Mips/micromips-alu-instructions-EB.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None
2
- 0x00,0xe6,0x49,0x10 = add $9, $6, $7
3
- 0x11,0x26,0x45,0x67 = addi $9, $6, 17767
4
- 0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001
5
- 0x11,0x26,0x45,0x67 = addi $9, $6, 17767
6
- 0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001
7
- 0x00,0xe6,0x49,0x50 = addu $9, $6, $7
8
- 0x00,0xe6,0x49,0x90 = sub $9, $6, $7
9
- 0x00,0xa3,0x21,0xd0 = subu $4, $3, $5
10
- 0x00,0xe0,0x31,0x90 = neg $6, $7
11
- 0x00,0xe0,0x31,0xd0 = negu $6, $7
12
- 0x00,0x08,0x39,0x50 = move $7, $8
13
- 0x00,0xa3,0x1b,0x50 = slt $3, $3, $5
14
- 0x90,0x63,0x00,0x67 = slti $3, $3, 103
15
- 0x90,0x63,0x00,0x67 = slti $3, $3, 103
16
- 0xb0,0x63,0x00,0x67 = sltiu $3, $3, 103
17
- 0x00,0xa3,0x1b,0x90 = sltu $3, $3, $5
18
- 0x41,0xa9,0x45,0x67 = lui $9, 17767
19
- 0x00,0xe6,0x4a,0x50 = and $9, $6, $7
20
- 0xd1,0x26,0x45,0x67 = andi $9, $6, 17767
21
- 0xd1,0x26,0x45,0x67 = andi $9, $6, 17767
22
- 0x00,0xa4,0x1a,0x90 = or $3, $4, $5
23
- 0x51,0x26,0x45,0x67 = ori $9, $6, 17767
24
- 0x00,0xa3,0x1b,0x10 = xor $3, $3, $5
25
- 0x71,0x26,0x45,0x67 = xori $9, $6, 17767
26
- 0x71,0x26,0x45,0x67 = xori $9, $6, 17767
27
- 0x00,0xe6,0x4a,0xd0 = nor $9, $6, $7
28
- 0x00,0x08,0x3a,0xd0 = not $7, $8
29
- 0x00,0xe6,0x4a,0x10 = mul $9, $6, $7
30
- 0x00,0xe9,0x8b,0x3c = mult $9, $7
31
- 0x00,0xe9,0x9b,0x3c = multu $9, $7
32
- 0x00,0xe9,0xab,0x3c = div $zero, $9, $7
33
- 0x00,0xe9,0xbb,0x3c = divu $zero, $9, $7
data/test/MC/Mips/micromips-alu-instructions.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0xe6,0x00,0x10,0x49 = add $9, $6, $7
3
- 0x26,0x11,0x67,0x45 = addi $9, $6, 17767
4
- 0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001
5
- 0x26,0x11,0x67,0x45 = addi $9, $6, 17767
6
- 0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001
7
- 0xe6,0x00,0x50,0x49 = addu $9, $6, $7
8
- 0xe6,0x00,0x90,0x49 = sub $9, $6, $7
9
- 0xa3,0x00,0xd0,0x21 = subu $4, $3, $5
10
- 0xe0,0x00,0x90,0x31 = neg $6, $7
11
- 0xe0,0x00,0xd0,0x31 = negu $6, $7
12
- 0x08,0x00,0x50,0x39 = move $7, $8
13
- 0xa3,0x00,0x50,0x1b = slt $3, $3, $5
14
- 0x63,0x90,0x67,0x00 = slti $3, $3, 103
15
- 0x63,0x90,0x67,0x00 = slti $3, $3, 103
16
- 0x63,0xb0,0x67,0x00 = sltiu $3, $3, 103
17
- 0xa3,0x00,0x90,0x1b = sltu $3, $3, $5
18
- 0xa9,0x41,0x67,0x45 = lui $9, 17767
19
- 0xe6,0x00,0x50,0x4a = and $9, $6, $7
20
- 0x26,0xd1,0x67,0x45 = andi $9, $6, 17767
21
- 0x26,0xd1,0x67,0x45 = andi $9, $6, 17767
22
- 0xa4,0x00,0x90,0x1a = or $3, $4, $5
23
- 0x26,0x51,0x67,0x45 = ori $9, $6, 17767
24
- 0xa3,0x00,0x10,0x1b = xor $3, $3, $5
25
- 0x26,0x71,0x67,0x45 = xori $9, $6, 17767
26
- 0x26,0x71,0x67,0x45 = xori $9, $6, 17767
27
- 0xe6,0x00,0xd0,0x4a = nor $9, $6, $7
28
- 0x08,0x00,0xd0,0x3a = not $7, $8
29
- 0xe6,0x00,0x10,0x4a = mul $9, $6, $7
30
- 0xe9,0x00,0x3c,0x8b = mult $9, $7
31
- 0xe9,0x00,0x3c,0x9b = multu $9, $7
32
- 0xe9,0x00,0x3c,0xab = div $zero, $9, $7
33
- 0xe9,0x00,0x3c,0xbb = divu $zero, $9, $7
data/test/MC/Mips/micromips-branch-instructions-EB.s.cs DELETED
@@ -1,11 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x94,0x00,0x02,0x9a = b 1332
3
- 0x94,0xc9,0x02,0x9a = beq $9, $6, 1332
4
- 0x40,0x46,0x02,0x9a = bgez $6, 1332
5
- 0x40,0x66,0x02,0x9a = bgezal $6, 1332
6
- 0x40,0x26,0x02,0x9a = bltzal $6, 1332
7
- 0x40,0xc6,0x02,0x9a = bgtz $6, 1332
8
- 0x40,0x86,0x02,0x9a = blez $6, 1332
9
- 0xb4,0xc9,0x02,0x9a = bne $9, $6, 1332
10
- 0x40,0x60,0x02,0x9a = bal 1332
11
- 0x40,0x06,0x02,0x9a = bltz $6, 1332
data/test/MC/Mips/micromips-branch-instructions.s.cs DELETED
@@ -1,11 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0x00,0x94,0x9a,0x02 = b 1332
3
- 0xc9,0x94,0x9a,0x02 = beq $9, $6, 1332
4
- 0x46,0x40,0x9a,0x02 = bgez $6, 1332
5
- 0x66,0x40,0x9a,0x02 = bgezal $6, 1332
6
- 0x26,0x40,0x9a,0x02 = bltzal $6, 1332
7
- 0xc6,0x40,0x9a,0x02 = bgtz $6, 1332
8
- 0x86,0x40,0x9a,0x02 = blez $6, 1332
9
- 0xc9,0xb4,0x9a,0x02 = bne $9, $6, 1332
10
- 0x60,0x40,0x9a,0x02 = bal 1332
11
- 0x06,0x40,0x9a,0x02 = bltz $6, 1332
data/test/MC/Mips/micromips-expansions.s.cs DELETED
@@ -1,20 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0xa0,0x50,0x7b,0x00 = ori $5, $zero, 123
3
- 0xc0,0x30,0xd7,0xf6 = addiu $6, $zero, -2345
4
- 0xa7,0x41,0x01,0x00 = lui $7, 1
5
- 0xe7,0x50,0x02,0x00 = ori $7, $7, 2
6
- 0x80,0x30,0x14,0x00 = addiu $4, $zero, 20
7
- 0xa7,0x41,0x01,0x00 = lui $7, 1
8
- 0xe7,0x50,0x02,0x00 = ori $7, $7, 2
9
- 0x85,0x30,0x14,0x00 = addiu $4, $5, 20
10
- 0xa7,0x41,0x01,0x00 = lui $7, 1
11
- 0xe7,0x50,0x02,0x00 = ori $7, $7, 2
12
- 0x07,0x01,0x50,0x39 = addu $7, $7, $8
13
- 0x8a,0x00,0x50,0x51 = addu $10, $10, $4
14
- 0x21,0x01,0x50,0x09 = addu $1, $1, $9
15
- 0xaa,0x41,0x0a,0x00 = lui $10, 10
16
- 0x8a,0x00,0x50,0x51 = addu $10, $10, $4
17
- 0x4a,0xfd,0x7b,0x00 = lw $10, 123($10)
18
- 0xa1,0x41,0x02,0x00 = lui $1, 2
19
- 0x21,0x01,0x50,0x09 = addu $1, $1, $9
20
- 0x41,0xf9,0x40,0xe2 = sw $10, 57920($1)
data/test/MC/Mips/micromips-jump-instructions-EB.s.cs DELETED
@@ -1,5 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0xd4,0x00,0x02,0x98 = j 1328
3
- 0xf4,0x00,0x02,0x98 = jal 1328
4
- 0x03,0xe6,0x0f,0x3c = jalr $6
5
- 0x00,0x07,0x0f,0x3c = jr $7
data/test/MC/Mips/micromips-jump-instructions.s.cs DELETED
@@ -1,6 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0x00,0xd4,0x98,0x02 = j 1328
3
- 0x00,0xf4,0x98,0x02 = jal 1328
4
- 0xe6,0x03,0x3c,0x0f = jalr $6
5
- 0x07,0x00,0x3c,0x0f = jr $7
6
- 0x07,0x00,0x3c,0x0f = jr $7
data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x1c,0xa4,0x00,0x08 = lb $5, 8($4)
3
- 0x14,0xc4,0x00,0x08 = lbu $6, 8($4)
4
- 0x3c,0x44,0x00,0x08 = lh $2, 8($4)
5
- 0x34,0x82,0x00,0x08 = lhu $4, 8($2)
6
- 0xfc,0xc5,0x00,0x04 = lw $6, 4($5)
7
- 0x18,0xa4,0x00,0x08 = sb $5, 8($4)
8
- 0x38,0x44,0x00,0x08 = sh $2, 8($4)
9
- 0xf8,0xa6,0x00,0x04 = sw $5, 4($6)
data/test/MC/Mips/micromips-loadstore-instructions.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0xa4,0x1c,0x08,0x00 = lb $5, 8($4)
3
- 0xc4,0x14,0x08,0x00 = lbu $6, 8($4)
4
- 0x44,0x3c,0x08,0x00 = lh $2, 8($4)
5
- 0x82,0x34,0x08,0x00 = lhu $4, 8($2)
6
- 0xc5,0xfc,0x04,0x00 = lw $6, 4($5)
7
- 0xa4,0x18,0x08,0x00 = sb $5, 8($4)
8
- 0x44,0x38,0x08,0x00 = sh $2, 8($4)
9
- 0xa6,0xf8,0x04,0x00 = sw $5, 4($6)
data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs DELETED
@@ -1,5 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x60,0x85,0x00,0x10 = lwl $4, 16($5)
3
- 0x60,0x85,0x10,0x10 = lwr $4, 16($5)
4
- 0x60,0x85,0x80,0x10 = swl $4, 16($5)
5
- 0x60,0x85,0x90,0x10 = swr $4, 16($5)
data/test/MC/Mips/micromips-loadstore-unaligned.s.cs DELETED
@@ -1,5 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0x85,0x60,0x10,0x00 = lwl $4, 16($5)
3
- 0x85,0x60,0x10,0x10 = lwr $4, 16($5)
4
- 0x85,0x60,0x10,0x80 = swl $4, 16($5)
5
- 0x85,0x60,0x10,0x90 = swr $4, 16($5)
data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs DELETED
@@ -1,5 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x00,0xe6,0x48,0x58 = movz $9, $6, $7
3
- 0x00,0xe6,0x48,0x18 = movn $9, $6, $7
4
- 0x55,0x26,0x09,0x7b = movt $9, $6, $fcc0
5
- 0x55,0x26,0x01,0x7b = movf $9, $6, $fcc0
data/test/MC/Mips/micromips-movcond-instructions.s.cs DELETED
@@ -1,5 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0xe6,0x00,0x58,0x48 = movz $9, $6, $7
3
- 0xe6,0x00,0x18,0x48 = movn $9, $6, $7
4
- 0x26,0x55,0x7b,0x09 = movt $9, $6, $fcc0
5
- 0x26,0x55,0x7b,0x01 = movf $9, $6, $fcc0
data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs DELETED
@@ -1,5 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x00,0xa4,0xcb,0x3c = madd $4, $5
3
- 0x00,0xa4,0xdb,0x3c = maddu $4, $5
4
- 0x00,0xa4,0xeb,0x3c = msub $4, $5
5
- 0x00,0xa4,0xfb,0x3c = msubu $4, $5
data/test/MC/Mips/micromips-multiply-instructions.s.cs DELETED
@@ -1,5 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0xa4,0x00,0x3c,0xcb = madd $4, $5
3
- 0xa4,0x00,0x3c,0xdb = maddu $4, $5
4
- 0xa4,0x00,0x3c,0xeb = msub $4, $5
5
- 0xa4,0x00,0x3c,0xfb = msubu $4, $5
data/test/MC/Mips/micromips-shift-instructions-EB.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x00,0x83,0x38,0x00 = sll $4, $3, 7
3
- 0x00,0x65,0x10,0x10 = sllv $2, $3, $5
4
- 0x00,0x83,0x38,0x80 = sra $4, $3, 7
5
- 0x00,0x65,0x10,0x90 = srav $2, $3, $5
6
- 0x00,0x83,0x38,0x40 = srl $4, $3, 7
7
- 0x00,0x65,0x10,0x50 = srlv $2, $3, $5
8
- 0x01,0x26,0x38,0xc0 = rotr $9, $6, 7
9
- 0x00,0xc7,0x48,0xd0 = rotrv $9, $6, $7
data/test/MC/Mips/micromips-shift-instructions.s.cs DELETED
@@ -1,9 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0x83,0x00,0x00,0x38 = sll $4, $3, 7
3
- 0x65,0x00,0x10,0x10 = sllv $2, $3, $5
4
- 0x83,0x00,0x80,0x38 = sra $4, $3, 7
5
- 0x65,0x00,0x90,0x10 = srav $2, $3, $5
6
- 0x83,0x00,0x40,0x38 = srl $4, $3, 7
7
- 0x65,0x00,0x50,0x10 = srlv $2, $3, $5
8
- 0x26,0x01,0xc0,0x38 = rotr $9, $6, 7
9
- 0xc7,0x00,0xd0,0x48 = rotrv $9, $6, $7
data/test/MC/Mips/micromips-trap-instructions-EB.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
2
- 0x01,0x28,0x00,0x3c = teq $8, $9
3
- 0x01,0x28,0x02,0x3c = tge $8, $9
4
- 0x01,0x28,0x04,0x3c = tgeu $8, $9
5
- 0x01,0x28,0x08,0x3c = tlt $8, $9
6
- 0x01,0x28,0x0a,0x3c = tltu $8, $9
7
- 0x01,0x28,0x0c,0x3c = tne $8, $9
8
- 0x41,0xc9,0x45,0x67 = teqi $9, 17767
9
- 0x41,0x29,0x45,0x67 = tgei $9, 17767
10
- 0x41,0x69,0x45,0x67 = tgeiu $9, 17767
11
- 0x41,0x09,0x45,0x67 = tlti $9, 17767
12
- 0x41,0x49,0x45,0x67 = tltiu $9, 17767
13
- 0x41,0x89,0x45,0x67 = tnei $9, 17767
data/test/MC/Mips/micromips-trap-instructions.s.cs DELETED
@@ -1,13 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
2
- 0x28,0x01,0x3c,0x00 = teq $8, $9
3
- 0x28,0x01,0x3c,0x02 = tge $8, $9
4
- 0x28,0x01,0x3c,0x04 = tgeu $8, $9
5
- 0x28,0x01,0x3c,0x08 = tlt $8, $9
6
- 0x28,0x01,0x3c,0x0a = tltu $8, $9
7
- 0x28,0x01,0x3c,0x0c = tne $8, $9
8
- 0xc9,0x41,0x67,0x45 = teqi $9, 17767
9
- 0x29,0x41,0x67,0x45 = tgei $9, 17767
10
- 0x69,0x41,0x67,0x45 = tgeiu $9, 17767
11
- 0x09,0x41,0x67,0x45 = tlti $9, 17767
12
- 0x49,0x41,0x67,0x45 = tltiu $9, 17767
13
- 0x89,0x41,0x67,0x45 = tnei $9, 17767
data/test/MC/Mips/mips-alu-instructions.s.cs DELETED
@@ -1,53 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32, None
2
- 0x24,0x48,0xc7,0x00 = and $9, $6, $7
3
- 0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
4
- 0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
5
- 0x67,0x45,0x29,0x31 = andi $9, $9, 17767
6
- 0x21,0x30,0xe6,0x70 = clo $6, $7
7
- 0x20,0x30,0xe6,0x70 = clz $6, $7
8
- 0x84,0x61,0x33,0x7d = ins $19, $9, 6, 7
9
- 0x27,0x48,0xc7,0x00 = nor $9, $6, $7
10
- 0x25,0x18,0x65,0x00 = or $3, $3, $5
11
- 0x67,0x45,0xa4,0x34 = ori $4, $5, 17767
12
- 0x67,0x45,0xc9,0x34 = ori $9, $6, 17767
13
- 0x80,0x00,0x6b,0x35 = ori $11, $11, 128
14
- 0xc2,0x49,0x26,0x00 = rotr $9, $6, 7
15
- 0x46,0x48,0xe6,0x00 = rotrv $9, $6, $7
16
- 0xc0,0x21,0x03,0x00 = sll $4, $3, 7
17
- 0x04,0x10,0xa3,0x00 = sllv $2, $3, $5
18
- 0x2a,0x18,0x65,0x00 = slt $3, $3, $5
19
- 0x67,0x00,0x63,0x28 = slti $3, $3, 103
20
- 0x67,0x00,0x63,0x28 = slti $3, $3, 103
21
- 0x67,0x00,0x63,0x2c = sltiu $3, $3, 103
22
- 0x2b,0x18,0x65,0x00 = sltu $3, $3, $5
23
- 0xc3,0x21,0x03,0x00 = sra $4, $3, 7
24
- 0x07,0x10,0xa3,0x00 = srav $2, $3, $5
25
- 0xc2,0x21,0x03,0x00 = srl $4, $3, 7
26
- 0x06,0x10,0xa3,0x00 = srlv $2, $3, $5
27
- 0x26,0x18,0x65,0x00 = xor $3, $3, $5
28
- 0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
29
- 0x67,0x45,0xc9,0x38 = xori $9, $6, 17767
30
- 0x0c,0x00,0x6b,0x39 = xori $11, $11, 12
31
- 0xa0,0x30,0x07,0x7c = wsbh $6, $7
32
- 0x27,0x38,0x00,0x01 = not $7, $8
33
- 0x20,0x48,0xc7,0x00 = add $9, $6, $7
34
- 0x67,0x45,0xc9,0x20 = addi $9, $6, 17767
35
- 0x67,0xc5,0xc9,0x24 = addiu $9, $6, -15001
36
- 0x67,0x45,0xc9,0x20 = addi $9, $6, 17767
37
- 0x67,0x45,0x29,0x21 = addi $9, $9, 17767
38
- 0x67,0xc5,0xc9,0x24 = addiu $9, $6, -15001
39
- 0x28,0x00,0x6b,0x25 = addiu $11, $11, 40
40
- 0x21,0x48,0xc7,0x00 = addu $9, $6, $7
41
- 0x00,0x00,0xc7,0x70 = madd $6, $7
42
- 0x01,0x00,0xc7,0x70 = maddu $6, $7
43
- 0x04,0x00,0xc7,0x70 = msub $6, $7
44
- 0x05,0x00,0xc7,0x70 = msubu $6, $7
45
- 0x18,0x00,0x65,0x00 = mult $3, $5
46
- 0x19,0x00,0x65,0x00 = multu $3, $5
47
- 0x22,0x48,0xc7,0x00 = sub $9, $6, $7
48
- 0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56
49
- 0x23,0x20,0x65,0x00 = subu $4, $3, $5
50
- 0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40
51
- 0x22,0x30,0x07,0x00 = neg $6, $7
52
- 0x23,0x30,0x07,0x00 = negu $6, $7
53
- 0x21,0x38,0x00,0x01 = move $7, $8
data/test/MC/Mips/mips-control-instructions-64.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
2
- 0x00,0x00,0x00,0x0d = break
3
- 0x00,0x07,0x00,0x0d = break 7, 0
4
- 0x00,0x07,0x01,0x4d = break 7, 5
5
- 0x00,0x00,0x00,0x0c = syscall
6
- 0x00,0x0d,0x15,0x0c = syscall 13396
7
- 0x42,0x00,0x00,0x18 = eret
8
- 0x42,0x00,0x00,0x1f = deret
9
- 0x41,0x60,0x60,0x00 = di
10
- 0x41,0x60,0x60,0x00 = di
11
- 0x41,0x6a,0x60,0x00 = di $10
12
- 0x41,0x60,0x60,0x20 = ei
13
- 0x41,0x60,0x60,0x20 = ei
14
- 0x41,0x6a,0x60,0x20 = ei $10
15
- 0x42,0x00,0x00,0x20 = wait
16
- 0x00,0x03,0x00,0x34 = teq $zero, $3
17
- 0x00,0x03,0x00,0x74 = teq $zero, $3, 1
18
- 0x04,0x6c,0x00,0x01 = teqi $3, 1
19
- 0x00,0x03,0x00,0x30 = tge $zero, $3
20
- 0x00,0x03,0x00,0xf0 = tge $zero, $3, 3
21
- 0x04,0x68,0x00,0x03 = tgei $3, 3
22
- 0x00,0x03,0x00,0x31 = tgeu $zero, $3
23
- 0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7
24
- 0x04,0x69,0x00,0x07 = tgeiu $3, 7
25
- 0x00,0x03,0x00,0x32 = tlt $zero, $3
26
- 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
27
- 0x04,0x6a,0x00,0x1f = tlti $3, 31
28
- 0x00,0x03,0x00,0x33 = tltu $zero, $3
29
- 0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255
30
- 0x04,0x6b,0x00,0xff = tltiu $3, 255
31
- 0x00,0x03,0x00,0x36 = tne $zero, $3
32
- 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
33
- 0x04,0x6e,0x03,0xff = tnei $3, 1023
data/test/MC/Mips/mips-control-instructions.s.cs DELETED
@@ -1,33 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
2
- 0x00,0x00,0x00,0x0d = break
3
- 0x00,0x07,0x00,0x0d = break 7, 0
4
- 0x00,0x07,0x01,0x4d = break 7, 5
5
- 0x00,0x00,0x00,0x0c = syscall
6
- 0x00,0x0d,0x15,0x0c = syscall 13396
7
- 0x42,0x00,0x00,0x18 = eret
8
- 0x42,0x00,0x00,0x1f = deret
9
- 0x41,0x60,0x60,0x00 = di
10
- 0x41,0x60,0x60,0x00 = di
11
- 0x41,0x6a,0x60,0x00 = di $10
12
- 0x41,0x60,0x60,0x20 = ei
13
- 0x41,0x60,0x60,0x20 = ei
14
- 0x41,0x6a,0x60,0x20 = ei $10
15
- 0x42,0x00,0x00,0x20 = wait
16
- 0x00,0x03,0x00,0x34 = teq $zero, $3
17
- 0x00,0x03,0x00,0x74 = teq $zero, $3, 1
18
- 0x04,0x6c,0x00,0x01 = teqi $3, 1
19
- 0x00,0x03,0x00,0x30 = tge $zero, $3
20
- 0x00,0x03,0x00,0xf0 = tge $zero, $3, 3
21
- 0x04,0x68,0x00,0x03 = tgei $3, 3
22
- 0x00,0x03,0x00,0x31 = tgeu $zero, $3
23
- 0x00,0x03,0x01,0xf1 = tgeu $zero, $3, 7
24
- 0x04,0x69,0x00,0x07 = tgeiu $3, 7
25
- 0x00,0x03,0x00,0x32 = tlt $zero, $3
26
- 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
27
- 0x04,0x6a,0x00,0x1f = tlti $3, 31
28
- 0x00,0x03,0x00,0x33 = tltu $zero, $3
29
- 0x00,0x03,0x3f,0xf3 = tltu $zero, $3, 255
30
- 0x04,0x6b,0x00,0xff = tltiu $3, 255
31
- 0x00,0x03,0x00,0x36 = tne $zero, $3
32
- 0x00,0x03,0xff,0xf6 = tne $zero, $3, 1023
33
- 0x04,0x6e,0x03,0xff = tnei $3, 1023
data/test/MC/Mips/mips-coprocessor-encodings.s.cs DELETED
@@ -1,17 +0,0 @@
1
- # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
2
- 0x40,0xac,0x80,0x02 = dmtc0 $12, $16, 2
3
- 0x40,0xac,0x80,0x00 = dmtc0 $12, $16, 0
4
- 0x40,0x8c,0x80,0x02 = mtc0 $12, $16, 2
5
- 0x40,0x8c,0x80,0x00 = mtc0 $12, $16, 0
6
- 0x40,0x2c,0x80,0x02 = dmfc0 $12, $16, 2
7
- 0x40,0x2c,0x80,0x00 = dmfc0 $12, $16, 0
8
- 0x40,0x0c,0x80,0x02 = mfc0 $12, $16, 2
9
- 0x40,0x0c,0x80,0x00 = mfc0 $12, $16, 0
10
- 0x48,0xac,0x80,0x02 = dmtc2 $12, $16, 2
11
- 0x48,0xac,0x80,0x00 = dmtc2 $12, $16, 0
12
- 0x48,0x8c,0x80,0x02 = mtc2 $12, $16, 2
13
- 0x48,0x8c,0x80,0x00 = mtc2 $12, $16, 0
14
- 0x48,0x2c,0x80,0x02 = dmfc2 $12, $16, 2
15
- 0x48,0x2c,0x80,0x00 = dmfc2 $12, $16, 0
16
- 0x48,0x0c,0x80,0x02 = mfc2 $12, $16, 2
17
- 0x48,0x0c,0x80,0x00 = mfc2 $12, $16, 0