RubyGems - crabstone - Versions diffs - 3.0.3 → 4.0.0 - Mend

crabstone 3.0.3 → 4.0.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.

Files changed (347) hide show

checksums.yaml +5 -5
data/CHANGES.md +45 -42
data/README.md +16 -33
data/lib/crabstone.rb +5 -557
data/lib/crabstone/arch.rb +37 -0
data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
data/lib/crabstone/arch/3/arm64.rb +124 -0
data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
data/lib/crabstone/arch/3/mips.rb +57 -0
data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
data/lib/crabstone/arch/3/ppc.rb +73 -0
data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
data/lib/crabstone/arch/3/sparc.rb +60 -0
data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
data/lib/crabstone/arch/3/sysz.rb +67 -0
data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
data/lib/crabstone/arch/3/x86.rb +82 -0
data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
data/lib/crabstone/arch/3/xcore.rb +59 -0
data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
data/lib/crabstone/arch/4/arm.rb +110 -0
data/lib/crabstone/arch/4/arm64.rb +125 -0
data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
data/lib/crabstone/arch/4/arm_const.rb +785 -0
data/lib/crabstone/arch/4/evm.rb +20 -0
data/lib/crabstone/arch/4/evm_const.rb +161 -0
data/lib/crabstone/arch/4/m680x.rb +106 -0
data/lib/crabstone/arch/4/m680x_const.rb +426 -0
data/lib/crabstone/arch/4/m68k.rb +129 -0
data/lib/crabstone/arch/4/m68k_const.rb +496 -0
data/lib/crabstone/arch/4/mips.rb +57 -0
data/lib/crabstone/arch/4/mips_const.rb +869 -0
data/lib/crabstone/arch/4/ppc.rb +73 -0
data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
data/lib/crabstone/arch/4/sparc.rb +60 -0
data/lib/crabstone/arch/4/sparc_const.rb +439 -0
data/lib/crabstone/arch/4/sysz.rb +67 -0
data/lib/crabstone/arch/4/sysz_const.rb +763 -0
data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
data/lib/crabstone/arch/4/x86.rb +91 -0
data/lib/crabstone/arch/4/x86_const.rb +1972 -0
data/lib/crabstone/arch/4/xcore.rb +59 -0
data/lib/crabstone/arch/4/xcore_const.rb +171 -0
data/lib/crabstone/arch/extension.rb +27 -0
data/lib/crabstone/arch/register.rb +36 -0
data/lib/crabstone/binding.rb +60 -0
data/lib/crabstone/binding/3/detail.rb +36 -0
data/lib/crabstone/binding/3/instruction.rb +23 -0
data/lib/crabstone/binding/4/detail.rb +40 -0
data/lib/crabstone/binding/4/instruction.rb +23 -0
data/lib/crabstone/binding/structs.rb +32 -0
data/lib/crabstone/constants.rb +110 -0
data/lib/crabstone/cs_version.rb +49 -0
data/lib/crabstone/disassembler.rb +153 -0
data/lib/crabstone/error.rb +60 -0
data/lib/crabstone/instruction.rb +183 -0
data/lib/crabstone/version.rb +5 -0
metadata +128 -324
data/MANIFEST +0 -312
data/Rakefile +0 -27
data/bin/genconst +0 -66
data/bin/genreg +0 -99
data/crabstone.gemspec +0 -27
data/examples/hello_world.rb +0 -43
data/lib/arch/arm64.rb +0 -167
data/lib/arch/arm64_registers.rb +0 -295
data/lib/arch/arm_registers.rb +0 -149
data/lib/arch/mips.rb +0 -78
data/lib/arch/mips_registers.rb +0 -208
data/lib/arch/ppc.rb +0 -90
data/lib/arch/ppc_registers.rb +0 -209
data/lib/arch/sparc.rb +0 -79
data/lib/arch/sparc_registers.rb +0 -121
data/lib/arch/systemz.rb +0 -79
data/lib/arch/sysz_registers.rb +0 -66
data/lib/arch/x86.rb +0 -107
data/lib/arch/x86_registers.rb +0 -265
data/lib/arch/xcore.rb +0 -78
data/lib/arch/xcore_registers.rb +0 -57
data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
data/test/MC/AArch64/neon-2velem.s.cs +0 -113
data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
data/test/MC/AArch64/neon-across.s.cs +0 -40
data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
data/test/MC/AArch64/neon-crypto.s.cs +0 -15
data/test/MC/AArch64/neon-extract.s.cs +0 -3
data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
data/test/MC/AArch64/neon-max-min.s.cs +0 -37
data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
data/test/MC/AArch64/neon-mov.s.cs +0 -74
data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
data/test/MC/AArch64/neon-perm.s.cs +0 -43
data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
data/test/MC/AArch64/neon-shift.s.cs +0 -22
data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
data/test/MC/AArch64/neon-tbl.s.cs +0 -21
data/test/MC/AArch64/trace-regs.s.cs +0 -383
data/test/MC/ARM/arm-aliases.s.cs +0 -7
data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
data/test/MC/ARM/arm-it-block.s.cs +0 -2
data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
data/test/MC/ARM/arm-trustzone.s.cs +0 -3
data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
data/test/MC/ARM/arm_instructions.s.cs +0 -25
data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
data/test/MC/ARM/crc32-thumb.s.cs +0 -7
data/test/MC/ARM/crc32.s.cs +0 -7
data/test/MC/ARM/dot-req.s.cs +0 -3
data/test/MC/ARM/fp-armv8.s.cs +0 -52
data/test/MC/ARM/idiv-thumb.s.cs +0 -3
data/test/MC/ARM/idiv.s.cs +0 -3
data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
data/test/MC/ARM/mode-switch.s.cs +0 -7
data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
data/test/MC/ARM/neon-crypto.s.cs +0 -16
data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
data/test/MC/ARM/neon-v8.s.cs +0 -38
data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
data/test/MC/ARM/neon-vswp.s.cs +0 -3
data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
data/test/MC/ARM/thumb-hints.s.cs +0 -12
data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
data/test/MC/ARM/thumb.s.cs +0 -19
data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
data/test/MC/ARM/thumb2-branches.s.cs +0 -85
data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
data/test/MC/ARM/vfp4.s.cs +0 -13
data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
data/test/MC/ARM/vpush-vpop.s.cs +0 -9
data/test/MC/Mips/hilo-addressing.s.cs +0 -4
data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
data/test/MC/Mips/micromips-expansions.s.cs +0 -20
data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
data/test/MC/Mips/mips-expansions.s.cs +0 -20
data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
data/test/MC/Mips/mips-register-names.s.cs +0 -33
data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
data/test/MC/Mips/mips64-instructions.s.cs +0 -3
data/test/MC/Mips/mips64-register-names.s.cs +0 -33
data/test/MC/Mips/mips_directives.s.cs +0 -12
data/test/MC/Mips/nabi-regs.s.cs +0 -12
data/test/MC/Mips/set-at-directive.s.cs +0 -6
data/test/MC/Mips/test_2r.s.cs +0 -16
data/test/MC/Mips/test_2rf.s.cs +0 -33
data/test/MC/Mips/test_3r.s.cs +0 -243
data/test/MC/Mips/test_3rf.s.cs +0 -83
data/test/MC/Mips/test_bit.s.cs +0 -49
data/test/MC/Mips/test_cbranch.s.cs +0 -11
data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
data/test/MC/Mips/test_elm.s.cs +0 -16
data/test/MC/Mips/test_elm_insert.s.cs +0 -4
data/test/MC/Mips/test_elm_insve.s.cs +0 -5
data/test/MC/Mips/test_i10.s.cs +0 -5
data/test/MC/Mips/test_i5.s.cs +0 -45
data/test/MC/Mips/test_i8.s.cs +0 -11
data/test/MC/Mips/test_lsa.s.cs +0 -5
data/test/MC/Mips/test_mi10.s.cs +0 -24
data/test/MC/Mips/test_vec.s.cs +0 -8
data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
data/test/MC/README +0 -6
data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
data/test/MC/Sparc/sparc-vis.s.cs +0 -2
data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
data/test/MC/SystemZ/insn-good.s.cs +0 -2265
data/test/MC/SystemZ/regs-good.s.cs +0 -45
data/test/MC/X86/3DNow.s.cs +0 -29
data/test/MC/X86/address-size.s.cs +0 -5
data/test/MC/X86/avx512-encodings.s.cs +0 -12
data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
data/test/MC/X86/x86-32-avx.s.cs +0 -833
data/test/MC/X86/x86-32-fma3.s.cs +0 -169
data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
data/test/MC/X86/x86_64-encoding.s.cs +0 -59
data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
data/test/README +0 -6
data/test/test.rb +0 -205
data/test/test.rb.SPEC +0 -235
data/test/test_arm.rb +0 -202
data/test/test_arm.rb.SPEC +0 -275
data/test/test_arm64.rb +0 -150
data/test/test_arm64.rb.SPEC +0 -116
data/test/test_detail.rb +0 -228
data/test/test_detail.rb.SPEC +0 -322
data/test/test_exhaustive.rb +0 -80
data/test/test_mips.rb +0 -118
data/test/test_mips.rb.SPEC +0 -91
data/test/test_ppc.rb +0 -137
data/test/test_ppc.rb.SPEC +0 -84
data/test/test_sanity.rb +0 -83
data/test/test_skipdata.rb +0 -111
data/test/test_skipdata.rb.SPEC +0 -58
data/test/test_sparc.rb +0 -113
data/test/test_sparc.rb.SPEC +0 -116
data/test/test_sysz.rb +0 -111
data/test/test_sysz.rb.SPEC +0 -61
data/test/test_x86.rb +0 -189
data/test/test_x86.rb.SPEC +0 -579
data/test/test_xcore.rb +0 -100
data/test/test_xcore.rb.SPEC +0 -75

data/lib/crabstone/arch/4/arm_const.rb ADDED

@@ -0,0 +1,785 @@
+# frozen_string_literal: true
+# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
+require 'crabstone/arch/register'
+module Crabstone
+  module ARM
+    SFT_INVALID = 0
+    SFT_ASR = 1
+    SFT_LSL = 2
+    SFT_LSR = 3
+    SFT_ROR = 4
+    SFT_RRX = 5
+    SFT_ASR_REG = 6
+    SFT_LSL_REG = 7
+    SFT_LSR_REG = 8
+    SFT_ROR_REG = 9
+    SFT_RRX_REG = 10
+    CC_INVALID = 0
+    CC_EQ = 1
+    CC_NE = 2
+    CC_HS = 3
+    CC_LO = 4
+    CC_MI = 5
+    CC_PL = 6
+    CC_VS = 7
+    CC_VC = 8
+    CC_HI = 9
+    CC_LS = 10
+    CC_GE = 11
+    CC_LT = 12
+    CC_GT = 13
+    CC_LE = 14
+    CC_AL = 15
+    SYSREG_INVALID = 0
+    SYSREG_SPSR_C = 1
+    SYSREG_SPSR_X = 2
+    SYSREG_SPSR_S = 4
+    SYSREG_SPSR_F = 8
+    SYSREG_CPSR_C = 16
+    SYSREG_CPSR_X = 32
+    SYSREG_CPSR_S = 64
+    SYSREG_CPSR_F = 128
+    SYSREG_APSR = 256
+    SYSREG_APSR_G = 257
+    SYSREG_APSR_NZCVQ = 258
+    SYSREG_APSR_NZCVQG = 259
+    SYSREG_IAPSR = 260
+    SYSREG_IAPSR_G = 261
+    SYSREG_IAPSR_NZCVQG = 262
+    SYSREG_IAPSR_NZCVQ = 263
+    SYSREG_EAPSR = 264
+    SYSREG_EAPSR_G = 265
+    SYSREG_EAPSR_NZCVQG = 266
+    SYSREG_EAPSR_NZCVQ = 267
+    SYSREG_XPSR = 268
+    SYSREG_XPSR_G = 269
+    SYSREG_XPSR_NZCVQG = 270
+    SYSREG_XPSR_NZCVQ = 271
+    SYSREG_IPSR = 272
+    SYSREG_EPSR = 273
+    SYSREG_IEPSR = 274
+    SYSREG_MSP = 275
+    SYSREG_PSP = 276
+    SYSREG_PRIMASK = 277
+    SYSREG_BASEPRI = 278
+    SYSREG_BASEPRI_MAX = 279
+    SYSREG_FAULTMASK = 280
+    SYSREG_CONTROL = 281
+    SYSREG_R8_USR = 282
+    SYSREG_R9_USR = 283
+    SYSREG_R10_USR = 284
+    SYSREG_R11_USR = 285
+    SYSREG_R12_USR = 286
+    SYSREG_SP_USR = 287
+    SYSREG_LR_USR = 288
+    SYSREG_R8_FIQ = 289
+    SYSREG_R9_FIQ = 290
+    SYSREG_R10_FIQ = 291
+    SYSREG_R11_FIQ = 292
+    SYSREG_R12_FIQ = 293
+    SYSREG_SP_FIQ = 294
+    SYSREG_LR_FIQ = 295
+    SYSREG_LR_IRQ = 296
+    SYSREG_SP_IRQ = 297
+    SYSREG_LR_SVC = 298
+    SYSREG_SP_SVC = 299
+    SYSREG_LR_ABT = 300
+    SYSREG_SP_ABT = 301
+    SYSREG_LR_UND = 302
+    SYSREG_SP_UND = 303
+    SYSREG_LR_MON = 304
+    SYSREG_SP_MON = 305
+    SYSREG_ELR_HYP = 306
+    SYSREG_SP_HYP = 307
+    SYSREG_SPSR_FIQ = 308
+    SYSREG_SPSR_IRQ = 309
+    SYSREG_SPSR_SVC = 310
+    SYSREG_SPSR_ABT = 311
+    SYSREG_SPSR_UND = 312
+    SYSREG_SPSR_MON = 313
+    SYSREG_SPSR_HYP = 314
+    MB_INVALID = 0
+    MB_RESERVED_0 = 1
+    MB_OSHLD = 2
+    MB_OSHST = 3
+    MB_OSH = 4
+    MB_RESERVED_4 = 5
+    MB_NSHLD = 6
+    MB_NSHST = 7
+    MB_NSH = 8
+    MB_RESERVED_8 = 9
+    MB_ISHLD = 10
+    MB_ISHST = 11
+    MB_ISH = 12
+    MB_RESERVED_12 = 13
+    MB_LD = 14
+    MB_ST = 15
+    MB_SY = 16
+    OP_INVALID = 0
+    OP_REG = 1
+    OP_IMM = 2
+    OP_MEM = 3
+    OP_FP = 4
+    OP_CIMM = 64
+    OP_PIMM = 65
+    OP_SETEND = 66
+    OP_SYSREG = 67
+    SETEND_INVALID = 0
+    SETEND_BE = 1
+    SETEND_LE = 2
+    CPSMODE_INVALID = 0
+    CPSMODE_IE = 2
+    CPSMODE_ID = 3
+    CPSFLAG_INVALID = 0
+    CPSFLAG_F = 1
+    CPSFLAG_I = 2
+    CPSFLAG_A = 4
+    CPSFLAG_NONE = 16
+    VECTORDATA_INVALID = 0
+    VECTORDATA_I8 = 1
+    VECTORDATA_I16 = 2
+    VECTORDATA_I32 = 3
+    VECTORDATA_I64 = 4
+    VECTORDATA_S8 = 5
+    VECTORDATA_S16 = 6
+    VECTORDATA_S32 = 7
+    VECTORDATA_S64 = 8
+    VECTORDATA_U8 = 9
+    VECTORDATA_U16 = 10
+    VECTORDATA_U32 = 11
+    VECTORDATA_U64 = 12
+    VECTORDATA_P8 = 13
+    VECTORDATA_F32 = 14
+    VECTORDATA_F64 = 15
+    VECTORDATA_F16F64 = 16
+    VECTORDATA_F64F16 = 17
+    VECTORDATA_F32F16 = 18
+    VECTORDATA_F16F32 = 19
+    VECTORDATA_F64F32 = 20
+    VECTORDATA_F32F64 = 21
+    VECTORDATA_S32F32 = 22
+    VECTORDATA_U32F32 = 23
+    VECTORDATA_F32S32 = 24
+    VECTORDATA_F32U32 = 25
+    VECTORDATA_F64S16 = 26
+    VECTORDATA_F32S16 = 27
+    VECTORDATA_F64S32 = 28
+    VECTORDATA_S16F64 = 29
+    VECTORDATA_S16F32 = 30
+    VECTORDATA_S32F64 = 31
+    VECTORDATA_U16F64 = 32
+    VECTORDATA_U16F32 = 33
+    VECTORDATA_U32F64 = 34
+    VECTORDATA_F64U16 = 35
+    VECTORDATA_F32U16 = 36
+    VECTORDATA_F64U32 = 37
+    REG_INVALID = 0
+    REG_APSR = 1
+    REG_APSR_NZCV = 2
+    REG_CPSR = 3
+    REG_FPEXC = 4
+    REG_FPINST = 5
+    REG_FPSCR = 6
+    REG_FPSCR_NZCV = 7
+    REG_FPSID = 8
+    REG_ITSTATE = 9
+    REG_LR = 10
+    REG_PC = 11
+    REG_SP = 12
+    REG_SPSR = 13
+    REG_D0 = 14
+    REG_D1 = 15
+    REG_D2 = 16
+    REG_D3 = 17
+    REG_D4 = 18
+    REG_D5 = 19
+    REG_D6 = 20
+    REG_D7 = 21
+    REG_D8 = 22
+    REG_D9 = 23
+    REG_D10 = 24
+    REG_D11 = 25
+    REG_D12 = 26
+    REG_D13 = 27
+    REG_D14 = 28
+    REG_D15 = 29
+    REG_D16 = 30
+    REG_D17 = 31
+    REG_D18 = 32
+    REG_D19 = 33
+    REG_D20 = 34
+    REG_D21 = 35
+    REG_D22 = 36
+    REG_D23 = 37
+    REG_D24 = 38
+    REG_D25 = 39
+    REG_D26 = 40
+    REG_D27 = 41
+    REG_D28 = 42
+    REG_D29 = 43
+    REG_D30 = 44
+    REG_D31 = 45
+    REG_FPINST2 = 46
+    REG_MVFR0 = 47
+    REG_MVFR1 = 48
+    REG_MVFR2 = 49
+    REG_Q0 = 50
+    REG_Q1 = 51
+    REG_Q2 = 52
+    REG_Q3 = 53
+    REG_Q4 = 54
+    REG_Q5 = 55
+    REG_Q6 = 56
+    REG_Q7 = 57
+    REG_Q8 = 58
+    REG_Q9 = 59
+    REG_Q10 = 60
+    REG_Q11 = 61
+    REG_Q12 = 62
+    REG_Q13 = 63
+    REG_Q14 = 64
+    REG_Q15 = 65
+    REG_R0 = 66
+    REG_R1 = 67
+    REG_R2 = 68
+    REG_R3 = 69
+    REG_R4 = 70
+    REG_R5 = 71
+    REG_R6 = 72
+    REG_R7 = 73
+    REG_R8 = 74
+    REG_R9 = 75
+    REG_R10 = 76
+    REG_R11 = 77
+    REG_R12 = 78
+    REG_S0 = 79
+    REG_S1 = 80
+    REG_S2 = 81
+    REG_S3 = 82
+    REG_S4 = 83
+    REG_S5 = 84
+    REG_S6 = 85
+    REG_S7 = 86
+    REG_S8 = 87
+    REG_S9 = 88
+    REG_S10 = 89
+    REG_S11 = 90
+    REG_S12 = 91
+    REG_S13 = 92
+    REG_S14 = 93
+    REG_S15 = 94
+    REG_S16 = 95
+    REG_S17 = 96
+    REG_S18 = 97
+    REG_S19 = 98
+    REG_S20 = 99
+    REG_S21 = 100
+    REG_S22 = 101
+    REG_S23 = 102
+    REG_S24 = 103
+    REG_S25 = 104
+    REG_S26 = 105
+    REG_S27 = 106
+    REG_S28 = 107
+    REG_S29 = 108
+    REG_S30 = 109
+    REG_S31 = 110
+    REG_ENDING = 111
+    REG_R13 = REG_SP
+    REG_R14 = REG_LR
+    REG_R15 = REG_PC
+    REG_SB = REG_R9
+    REG_SL = REG_R10
+    REG_FP = REG_R11
+    REG_IP = REG_R12
+    INS_INVALID = 0
+    INS_ADC = 1
+    INS_ADD = 2
+    INS_ADR = 3
+    INS_AESD = 4
+    INS_AESE = 5
+    INS_AESIMC = 6
+    INS_AESMC = 7
+    INS_AND = 8
+    INS_BFC = 9
+    INS_BFI = 10
+    INS_BIC = 11
+    INS_BKPT = 12
+    INS_BL = 13
+    INS_BLX = 14
+    INS_BX = 15
+    INS_BXJ = 16
+    INS_B = 17
+    INS_CDP = 18
+    INS_CDP2 = 19
+    INS_CLREX = 20
+    INS_CLZ = 21
+    INS_CMN = 22
+    INS_CMP = 23
+    INS_CPS = 24
+    INS_CRC32B = 25
+    INS_CRC32CB = 26
+    INS_CRC32CH = 27
+    INS_CRC32CW = 28
+    INS_CRC32H = 29
+    INS_CRC32W = 30
+    INS_DBG = 31
+    INS_DMB = 32
+    INS_DSB = 33
+    INS_EOR = 34
+    INS_ERET = 35
+    INS_VMOV = 36
+    INS_FLDMDBX = 37
+    INS_FLDMIAX = 38
+    INS_VMRS = 39
+    INS_FSTMDBX = 40
+    INS_FSTMIAX = 41
+    INS_HINT = 42
+    INS_HLT = 43
+    INS_HVC = 44
+    INS_ISB = 45
+    INS_LDA = 46
+    INS_LDAB = 47
+    INS_LDAEX = 48
+    INS_LDAEXB = 49
+    INS_LDAEXD = 50
+    INS_LDAEXH = 51
+    INS_LDAH = 52
+    INS_LDC2L = 53
+    INS_LDC2 = 54
+    INS_LDCL = 55
+    INS_LDC = 56
+    INS_LDMDA = 57
+    INS_LDMDB = 58
+    INS_LDM = 59
+    INS_LDMIB = 60
+    INS_LDRBT = 61
+    INS_LDRB = 62
+    INS_LDRD = 63
+    INS_LDREX = 64
+    INS_LDREXB = 65
+    INS_LDREXD = 66
+    INS_LDREXH = 67
+    INS_LDRH = 68
+    INS_LDRHT = 69
+    INS_LDRSB = 70
+    INS_LDRSBT = 71
+    INS_LDRSH = 72
+    INS_LDRSHT = 73
+    INS_LDRT = 74
+    INS_LDR = 75
+    INS_MCR = 76
+    INS_MCR2 = 77
+    INS_MCRR = 78
+    INS_MCRR2 = 79
+    INS_MLA = 80
+    INS_MLS = 81
+    INS_MOV = 82
+    INS_MOVT = 83
+    INS_MOVW = 84
+    INS_MRC = 85
+    INS_MRC2 = 86
+    INS_MRRC = 87
+    INS_MRRC2 = 88
+    INS_MRS = 89
+    INS_MSR = 90
+    INS_MUL = 91
+    INS_MVN = 92
+    INS_ORR = 93
+    INS_PKHBT = 94
+    INS_PKHTB = 95
+    INS_PLDW = 96
+    INS_PLD = 97
+    INS_PLI = 98
+    INS_QADD = 99
+    INS_QADD16 = 100
+    INS_QADD8 = 101
+    INS_QASX = 102
+    INS_QDADD = 103
+    INS_QDSUB = 104
+    INS_QSAX = 105
+    INS_QSUB = 106
+    INS_QSUB16 = 107
+    INS_QSUB8 = 108
+    INS_RBIT = 109
+    INS_REV = 110
+    INS_REV16 = 111
+    INS_REVSH = 112
+    INS_RFEDA = 113
+    INS_RFEDB = 114
+    INS_RFEIA = 115
+    INS_RFEIB = 116
+    INS_RSB = 117
+    INS_RSC = 118
+    INS_SADD16 = 119
+    INS_SADD8 = 120
+    INS_SASX = 121
+    INS_SBC = 122
+    INS_SBFX = 123
+    INS_SDIV = 124
+    INS_SEL = 125
+    INS_SETEND = 126
+    INS_SHA1C = 127
+    INS_SHA1H = 128
+    INS_SHA1M = 129
+    INS_SHA1P = 130
+    INS_SHA1SU0 = 131
+    INS_SHA1SU1 = 132
+    INS_SHA256H = 133
+    INS_SHA256H2 = 134
+    INS_SHA256SU0 = 135
+    INS_SHA256SU1 = 136
+    INS_SHADD16 = 137
+    INS_SHADD8 = 138
+    INS_SHASX = 139
+    INS_SHSAX = 140
+    INS_SHSUB16 = 141
+    INS_SHSUB8 = 142
+    INS_SMC = 143
+    INS_SMLABB = 144
+    INS_SMLABT = 145
+    INS_SMLAD = 146
+    INS_SMLADX = 147
+    INS_SMLAL = 148
+    INS_SMLALBB = 149
+    INS_SMLALBT = 150
+    INS_SMLALD = 151
+    INS_SMLALDX = 152
+    INS_SMLALTB = 153
+    INS_SMLALTT = 154
+    INS_SMLATB = 155
+    INS_SMLATT = 156
+    INS_SMLAWB = 157
+    INS_SMLAWT = 158
+    INS_SMLSD = 159
+    INS_SMLSDX = 160
+    INS_SMLSLD = 161
+    INS_SMLSLDX = 162
+    INS_SMMLA = 163
+    INS_SMMLAR = 164
+    INS_SMMLS = 165
+    INS_SMMLSR = 166
+    INS_SMMUL = 167
+    INS_SMMULR = 168
+    INS_SMUAD = 169
+    INS_SMUADX = 170
+    INS_SMULBB = 171
+    INS_SMULBT = 172
+    INS_SMULL = 173
+    INS_SMULTB = 174
+    INS_SMULTT = 175
+    INS_SMULWB = 176
+    INS_SMULWT = 177
+    INS_SMUSD = 178
+    INS_SMUSDX = 179
+    INS_SRSDA = 180
+    INS_SRSDB = 181
+    INS_SRSIA = 182
+    INS_SRSIB = 183
+    INS_SSAT = 184
+    INS_SSAT16 = 185
+    INS_SSAX = 186
+    INS_SSUB16 = 187
+    INS_SSUB8 = 188
+    INS_STC2L = 189
+    INS_STC2 = 190
+    INS_STCL = 191
+    INS_STC = 192
+    INS_STL = 193
+    INS_STLB = 194
+    INS_STLEX = 195
+    INS_STLEXB = 196
+    INS_STLEXD = 197
+    INS_STLEXH = 198
+    INS_STLH = 199
+    INS_STMDA = 200
+    INS_STMDB = 201
+    INS_STM = 202
+    INS_STMIB = 203
+    INS_STRBT = 204
+    INS_STRB = 205
+    INS_STRD = 206
+    INS_STREX = 207
+    INS_STREXB = 208
+    INS_STREXD = 209
+    INS_STREXH = 210
+    INS_STRH = 211
+    INS_STRHT = 212
+    INS_STRT = 213
+    INS_STR = 214
+    INS_SUB = 215
+    INS_SVC = 216
+    INS_SWP = 217
+    INS_SWPB = 218
+    INS_SXTAB = 219
+    INS_SXTAB16 = 220
+    INS_SXTAH = 221
+    INS_SXTB = 222
+    INS_SXTB16 = 223
+    INS_SXTH = 224
+    INS_TEQ = 225
+    INS_TRAP = 226
+    INS_TST = 227
+    INS_UADD16 = 228
+    INS_UADD8 = 229
+    INS_UASX = 230
+    INS_UBFX = 231
+    INS_UDF = 232
+    INS_UDIV = 233
+    INS_UHADD16 = 234
+    INS_UHADD8 = 235
+    INS_UHASX = 236
+    INS_UHSAX = 237
+    INS_UHSUB16 = 238
+    INS_UHSUB8 = 239
+    INS_UMAAL = 240
+    INS_UMLAL = 241
+    INS_UMULL = 242
+    INS_UQADD16 = 243
+    INS_UQADD8 = 244
+    INS_UQASX = 245
+    INS_UQSAX = 246
+    INS_UQSUB16 = 247
+    INS_UQSUB8 = 248
+    INS_USAD8 = 249
+    INS_USADA8 = 250
+    INS_USAT = 251
+    INS_USAT16 = 252
+    INS_USAX = 253
+    INS_USUB16 = 254
+    INS_USUB8 = 255
+    INS_UXTAB = 256
+    INS_UXTAB16 = 257
+    INS_UXTAH = 258
+    INS_UXTB = 259
+    INS_UXTB16 = 260
+    INS_UXTH = 261
+    INS_VABAL = 262
+    INS_VABA = 263
+    INS_VABDL = 264
+    INS_VABD = 265
+    INS_VABS = 266
+    INS_VACGE = 267
+    INS_VACGT = 268
+    INS_VADD = 269
+    INS_VADDHN = 270
+    INS_VADDL = 271
+    INS_VADDW = 272
+    INS_VAND = 273
+    INS_VBIC = 274
+    INS_VBIF = 275
+    INS_VBIT = 276
+    INS_VBSL = 277
+    INS_VCEQ = 278
+    INS_VCGE = 279
+    INS_VCGT = 280
+    INS_VCLE = 281
+    INS_VCLS = 282
+    INS_VCLT = 283
+    INS_VCLZ = 284
+    INS_VCMP = 285
+    INS_VCMPE = 286
+    INS_VCNT = 287
+    INS_VCVTA = 288
+    INS_VCVTB = 289
+    INS_VCVT = 290
+    INS_VCVTM = 291
+    INS_VCVTN = 292
+    INS_VCVTP = 293
+    INS_VCVTT = 294
+    INS_VDIV = 295
+    INS_VDUP = 296
+    INS_VEOR = 297
+    INS_VEXT = 298
+    INS_VFMA = 299
+    INS_VFMS = 300
+    INS_VFNMA = 301
+    INS_VFNMS = 302
+    INS_VHADD = 303
+    INS_VHSUB = 304
+    INS_VLD1 = 305
+    INS_VLD2 = 306
+    INS_VLD3 = 307
+    INS_VLD4 = 308
+    INS_VLDMDB = 309
+    INS_VLDMIA = 310
+    INS_VLDR = 311
+    INS_VMAXNM = 312
+    INS_VMAX = 313
+    INS_VMINNM = 314
+    INS_VMIN = 315
+    INS_VMLA = 316
+    INS_VMLAL = 317
+    INS_VMLS = 318
+    INS_VMLSL = 319
+    INS_VMOVL = 320
+    INS_VMOVN = 321
+    INS_VMSR = 322
+    INS_VMUL = 323
+    INS_VMULL = 324
+    INS_VMVN = 325
+    INS_VNEG = 326
+    INS_VNMLA = 327
+    INS_VNMLS = 328
+    INS_VNMUL = 329
+    INS_VORN = 330
+    INS_VORR = 331
+    INS_VPADAL = 332
+    INS_VPADDL = 333
+    INS_VPADD = 334
+    INS_VPMAX = 335
+    INS_VPMIN = 336
+    INS_VQABS = 337
+    INS_VQADD = 338
+    INS_VQDMLAL = 339
+    INS_VQDMLSL = 340
+    INS_VQDMULH = 341
+    INS_VQDMULL = 342
+    INS_VQMOVUN = 343
+    INS_VQMOVN = 344
+    INS_VQNEG = 345
+    INS_VQRDMULH = 346
+    INS_VQRSHL = 347
+    INS_VQRSHRN = 348
+    INS_VQRSHRUN = 349
+    INS_VQSHL = 350
+    INS_VQSHLU = 351
+    INS_VQSHRN = 352
+    INS_VQSHRUN = 353
+    INS_VQSUB = 354
+    INS_VRADDHN = 355
+    INS_VRECPE = 356
+    INS_VRECPS = 357
+    INS_VREV16 = 358
+    INS_VREV32 = 359
+    INS_VREV64 = 360
+    INS_VRHADD = 361
+    INS_VRINTA = 362
+    INS_VRINTM = 363
+    INS_VRINTN = 364
+    INS_VRINTP = 365
+    INS_VRINTR = 366
+    INS_VRINTX = 367
+    INS_VRINTZ = 368
+    INS_VRSHL = 369
+    INS_VRSHRN = 370
+    INS_VRSHR = 371
+    INS_VRSQRTE = 372
+    INS_VRSQRTS = 373
+    INS_VRSRA = 374
+    INS_VRSUBHN = 375
+    INS_VSELEQ = 376
+    INS_VSELGE = 377
+    INS_VSELGT = 378
+    INS_VSELVS = 379
+    INS_VSHLL = 380
+    INS_VSHL = 381
+    INS_VSHRN = 382
+    INS_VSHR = 383
+    INS_VSLI = 384
+    INS_VSQRT = 385
+    INS_VSRA = 386
+    INS_VSRI = 387
+    INS_VST1 = 388
+    INS_VST2 = 389
+    INS_VST3 = 390
+    INS_VST4 = 391
+    INS_VSTMDB = 392
+    INS_VSTMIA = 393
+    INS_VSTR = 394
+    INS_VSUB = 395
+    INS_VSUBHN = 396
+    INS_VSUBL = 397
+    INS_VSUBW = 398
+    INS_VSWP = 399
+    INS_VTBL = 400
+    INS_VTBX = 401
+    INS_VCVTR = 402
+    INS_VTRN = 403
+    INS_VTST = 404
+    INS_VUZP = 405
+    INS_VZIP = 406
+    INS_ADDW = 407
+    INS_ASR = 408
+    INS_DCPS1 = 409
+    INS_DCPS2 = 410
+    INS_DCPS3 = 411
+    INS_IT = 412
+    INS_LSL = 413
+    INS_LSR = 414
+    INS_ORN = 415
+    INS_ROR = 416
+    INS_RRX = 417
+    INS_SUBW = 418
+    INS_TBB = 419
+    INS_TBH = 420
+    INS_CBNZ = 421
+    INS_CBZ = 422
+    INS_POP = 423
+    INS_PUSH = 424
+    INS_NOP = 425
+    INS_YIELD = 426
+    INS_WFE = 427
+    INS_WFI = 428
+    INS_SEV = 429
+    INS_SEVL = 430
+    INS_VPUSH = 431
+    INS_VPOP = 432
+    INS_ENDING = 433
+    GRP_INVALID = 0
+    GRP_JUMP = 1
+    GRP_CALL = 2
+    GRP_INT = 4
+    GRP_PRIVILEGE = 6
+    GRP_BRANCH_RELATIVE = 7
+    GRP_CRYPTO = 128
+    GRP_DATABARRIER = 129
+    GRP_DIVIDE = 130
+    GRP_FPARMV8 = 131
+    GRP_MULTPRO = 132
+    GRP_NEON = 133
+    GRP_T2EXTRACTPACK = 134
+    GRP_THUMB2DSP = 135
+    GRP_TRUSTZONE = 136
+    GRP_V4T = 137
+    GRP_V5T = 138
+    GRP_V5TE = 139
+    GRP_V6 = 140
+    GRP_V6T2 = 141
+    GRP_V7 = 142
+    GRP_V8 = 143
+    GRP_VFP2 = 144
+    GRP_VFP3 = 145
+    GRP_VFP4 = 146
+    GRP_ARM = 147
+    GRP_MCLASS = 148
+    GRP_NOTMCLASS = 149
+    GRP_THUMB = 150
+    GRP_THUMB1ONLY = 151
+    GRP_THUMB2 = 152
+    GRP_PREV8 = 153
+    GRP_FPVMLX = 154
+    GRP_MULOPS = 155
+    GRP_CRC = 156
+    GRP_DPVFP = 157
+    GRP_V6M = 158
+    GRP_VIRTUALIZATION = 159
+    GRP_ENDING = 160
+    extend Register
+  end
+end