crabstone 3.0.3 → 4.0.0

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Files changed (347) hide show
  1. checksums.yaml +5 -5
  2. data/CHANGES.md +45 -42
  3. data/README.md +16 -33
  4. data/lib/crabstone.rb +5 -557
  5. data/lib/crabstone/arch.rb +37 -0
  6. data/lib/{arch → crabstone/arch/3}/arm.rb +28 -49
  7. data/lib/crabstone/arch/3/arm64.rb +124 -0
  8. data/lib/{arch → crabstone/arch/3}/arm64_const.rb +45 -86
  9. data/lib/{arch → crabstone/arch/3}/arm_const.rb +19 -47
  10. data/lib/crabstone/arch/3/mips.rb +57 -0
  11. data/lib/{arch → crabstone/arch/3}/mips_const.rb +18 -38
  12. data/lib/crabstone/arch/3/ppc.rb +73 -0
  13. data/lib/{arch → crabstone/arch/3}/ppc_const.rb +27 -43
  14. data/lib/crabstone/arch/3/sparc.rb +60 -0
  15. data/lib/{arch → crabstone/arch/3}/sparc_const.rb +49 -67
  16. data/lib/crabstone/arch/3/sysz.rb +67 -0
  17. data/lib/{arch → crabstone/arch/3}/sysz_const.rb +11 -25
  18. data/lib/crabstone/arch/3/x86.rb +82 -0
  19. data/lib/{arch → crabstone/arch/3}/x86_const.rb +15 -36
  20. data/lib/crabstone/arch/3/xcore.rb +59 -0
  21. data/lib/{arch → crabstone/arch/3}/xcore_const.rb +10 -22
  22. data/lib/crabstone/arch/4/arm.rb +110 -0
  23. data/lib/crabstone/arch/4/arm64.rb +125 -0
  24. data/lib/crabstone/arch/4/arm64_const.rb +1016 -0
  25. data/lib/crabstone/arch/4/arm_const.rb +785 -0
  26. data/lib/crabstone/arch/4/evm.rb +20 -0
  27. data/lib/crabstone/arch/4/evm_const.rb +161 -0
  28. data/lib/crabstone/arch/4/m680x.rb +106 -0
  29. data/lib/crabstone/arch/4/m680x_const.rb +426 -0
  30. data/lib/crabstone/arch/4/m68k.rb +129 -0
  31. data/lib/crabstone/arch/4/m68k_const.rb +496 -0
  32. data/lib/crabstone/arch/4/mips.rb +57 -0
  33. data/lib/crabstone/arch/4/mips_const.rb +869 -0
  34. data/lib/crabstone/arch/4/ppc.rb +73 -0
  35. data/lib/crabstone/arch/4/ppc_const.rb +1375 -0
  36. data/lib/crabstone/arch/4/sparc.rb +60 -0
  37. data/lib/crabstone/arch/4/sparc_const.rb +439 -0
  38. data/lib/crabstone/arch/4/sysz.rb +67 -0
  39. data/lib/crabstone/arch/4/sysz_const.rb +763 -0
  40. data/lib/crabstone/arch/4/tms320c64x.rb +87 -0
  41. data/lib/crabstone/arch/4/tms320c64x_const.rb +287 -0
  42. data/lib/crabstone/arch/4/x86.rb +91 -0
  43. data/lib/crabstone/arch/4/x86_const.rb +1972 -0
  44. data/lib/crabstone/arch/4/xcore.rb +59 -0
  45. data/lib/crabstone/arch/4/xcore_const.rb +171 -0
  46. data/lib/crabstone/arch/extension.rb +27 -0
  47. data/lib/crabstone/arch/register.rb +36 -0
  48. data/lib/crabstone/binding.rb +60 -0
  49. data/lib/crabstone/binding/3/detail.rb +36 -0
  50. data/lib/crabstone/binding/3/instruction.rb +23 -0
  51. data/lib/crabstone/binding/4/detail.rb +40 -0
  52. data/lib/crabstone/binding/4/instruction.rb +23 -0
  53. data/lib/crabstone/binding/structs.rb +32 -0
  54. data/lib/crabstone/constants.rb +110 -0
  55. data/lib/crabstone/cs_version.rb +49 -0
  56. data/lib/crabstone/disassembler.rb +153 -0
  57. data/lib/crabstone/error.rb +60 -0
  58. data/lib/crabstone/instruction.rb +183 -0
  59. data/lib/crabstone/version.rb +5 -0
  60. metadata +128 -324
  61. data/MANIFEST +0 -312
  62. data/Rakefile +0 -27
  63. data/bin/genconst +0 -66
  64. data/bin/genreg +0 -99
  65. data/crabstone.gemspec +0 -27
  66. data/examples/hello_world.rb +0 -43
  67. data/lib/arch/arm64.rb +0 -167
  68. data/lib/arch/arm64_registers.rb +0 -295
  69. data/lib/arch/arm_registers.rb +0 -149
  70. data/lib/arch/mips.rb +0 -78
  71. data/lib/arch/mips_registers.rb +0 -208
  72. data/lib/arch/ppc.rb +0 -90
  73. data/lib/arch/ppc_registers.rb +0 -209
  74. data/lib/arch/sparc.rb +0 -79
  75. data/lib/arch/sparc_registers.rb +0 -121
  76. data/lib/arch/systemz.rb +0 -79
  77. data/lib/arch/sysz_registers.rb +0 -66
  78. data/lib/arch/x86.rb +0 -107
  79. data/lib/arch/x86_registers.rb +0 -265
  80. data/lib/arch/xcore.rb +0 -78
  81. data/lib/arch/xcore_registers.rb +0 -57
  82. data/test/MC/AArch64/basic-a64-instructions.s.cs +0 -2014
  83. data/test/MC/AArch64/gicv3-regs.s.cs +0 -111
  84. data/test/MC/AArch64/neon-2velem.s.cs +0 -113
  85. data/test/MC/AArch64/neon-3vdiff.s.cs +0 -143
  86. data/test/MC/AArch64/neon-aba-abd.s.cs +0 -28
  87. data/test/MC/AArch64/neon-across.s.cs +0 -40
  88. data/test/MC/AArch64/neon-add-pairwise.s.cs +0 -11
  89. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +0 -21
  90. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +0 -17
  91. data/test/MC/AArch64/neon-compare-instructions.s.cs +0 -136
  92. data/test/MC/AArch64/neon-crypto.s.cs +0 -15
  93. data/test/MC/AArch64/neon-extract.s.cs +0 -3
  94. data/test/MC/AArch64/neon-facge-facgt.s.cs +0 -13
  95. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +0 -7
  96. data/test/MC/AArch64/neon-halving-add-sub.s.cs +0 -25
  97. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +0 -37
  98. data/test/MC/AArch64/neon-max-min.s.cs +0 -37
  99. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +0 -19
  100. data/test/MC/AArch64/neon-mov.s.cs +0 -74
  101. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +0 -24
  102. data/test/MC/AArch64/neon-perm.s.cs +0 -43
  103. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +0 -13
  104. data/test/MC/AArch64/neon-rounding-shift.s.cs +0 -15
  105. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +0 -29
  106. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +0 -15
  107. data/test/MC/AArch64/neon-saturating-shift.s.cs +0 -15
  108. data/test/MC/AArch64/neon-scalar-abs.s.cs +0 -8
  109. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +0 -3
  110. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +0 -13
  111. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +0 -13
  112. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +0 -15
  113. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +0 -18
  114. data/test/MC/AArch64/neon-scalar-compare.s.cs +0 -12
  115. data/test/MC/AArch64/neon-scalar-cvt.s.cs +0 -34
  116. data/test/MC/AArch64/neon-scalar-dup.s.cs +0 -23
  117. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +0 -10
  118. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +0 -21
  119. data/test/MC/AArch64/neon-scalar-mul.s.cs +0 -13
  120. data/test/MC/AArch64/neon-scalar-neg.s.cs +0 -6
  121. data/test/MC/AArch64/neon-scalar-recip.s.cs +0 -11
  122. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +0 -3
  123. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +0 -3
  124. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +0 -25
  125. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +0 -9
  126. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +0 -9
  127. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +0 -42
  128. data/test/MC/AArch64/neon-scalar-shift.s.cs +0 -3
  129. data/test/MC/AArch64/neon-shift-left-long.s.cs +0 -13
  130. data/test/MC/AArch64/neon-shift.s.cs +0 -22
  131. data/test/MC/AArch64/neon-simd-copy.s.cs +0 -42
  132. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +0 -197
  133. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +0 -129
  134. data/test/MC/AArch64/neon-simd-misc.s.cs +0 -213
  135. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +0 -107
  136. data/test/MC/AArch64/neon-simd-shift.s.cs +0 -151
  137. data/test/MC/AArch64/neon-tbl.s.cs +0 -21
  138. data/test/MC/AArch64/trace-regs.s.cs +0 -383
  139. data/test/MC/ARM/arm-aliases.s.cs +0 -7
  140. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +0 -50
  141. data/test/MC/ARM/arm-it-block.s.cs +0 -2
  142. data/test/MC/ARM/arm-memory-instructions.s.cs +0 -138
  143. data/test/MC/ARM/arm-shift-encoding.s.cs +0 -50
  144. data/test/MC/ARM/arm-thumb-trustzone.s.cs +0 -3
  145. data/test/MC/ARM/arm-trustzone.s.cs +0 -3
  146. data/test/MC/ARM/arm_addrmode2.s.cs +0 -15
  147. data/test/MC/ARM/arm_addrmode3.s.cs +0 -9
  148. data/test/MC/ARM/arm_instructions.s.cs +0 -25
  149. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +0 -10
  150. data/test/MC/ARM/basic-arm-instructions.s.cs +0 -997
  151. data/test/MC/ARM/basic-thumb-instructions.s.cs +0 -130
  152. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +0 -1
  153. data/test/MC/ARM/basic-thumb2-instructions.s.cs +0 -1242
  154. data/test/MC/ARM/crc32-thumb.s.cs +0 -7
  155. data/test/MC/ARM/crc32.s.cs +0 -7
  156. data/test/MC/ARM/dot-req.s.cs +0 -3
  157. data/test/MC/ARM/fp-armv8.s.cs +0 -52
  158. data/test/MC/ARM/idiv-thumb.s.cs +0 -3
  159. data/test/MC/ARM/idiv.s.cs +0 -3
  160. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +0 -15
  161. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +0 -15
  162. data/test/MC/ARM/mode-switch.s.cs +0 -7
  163. data/test/MC/ARM/neon-abs-encoding.s.cs +0 -15
  164. data/test/MC/ARM/neon-absdiff-encoding.s.cs +0 -39
  165. data/test/MC/ARM/neon-add-encoding.s.cs +0 -119
  166. data/test/MC/ARM/neon-bitcount-encoding.s.cs +0 -15
  167. data/test/MC/ARM/neon-bitwise-encoding.s.cs +0 -126
  168. data/test/MC/ARM/neon-cmp-encoding.s.cs +0 -88
  169. data/test/MC/ARM/neon-convert-encoding.s.cs +0 -27
  170. data/test/MC/ARM/neon-crypto.s.cs +0 -16
  171. data/test/MC/ARM/neon-dup-encoding.s.cs +0 -13
  172. data/test/MC/ARM/neon-minmax-encoding.s.cs +0 -57
  173. data/test/MC/ARM/neon-mov-encoding.s.cs +0 -76
  174. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +0 -39
  175. data/test/MC/ARM/neon-mul-encoding.s.cs +0 -72
  176. data/test/MC/ARM/neon-neg-encoding.s.cs +0 -15
  177. data/test/MC/ARM/neon-pairwise-encoding.s.cs +0 -47
  178. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +0 -13
  179. data/test/MC/ARM/neon-reverse-encoding.s.cs +0 -13
  180. data/test/MC/ARM/neon-satshift-encoding.s.cs +0 -75
  181. data/test/MC/ARM/neon-shift-encoding.s.cs +0 -238
  182. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +0 -97
  183. data/test/MC/ARM/neon-shuffle-encoding.s.cs +0 -59
  184. data/test/MC/ARM/neon-sub-encoding.s.cs +0 -82
  185. data/test/MC/ARM/neon-table-encoding.s.cs +0 -9
  186. data/test/MC/ARM/neon-v8.s.cs +0 -38
  187. data/test/MC/ARM/neon-vld-encoding.s.cs +0 -213
  188. data/test/MC/ARM/neon-vst-encoding.s.cs +0 -120
  189. data/test/MC/ARM/neon-vswp.s.cs +0 -3
  190. data/test/MC/ARM/neont2-abs-encoding.s.cs +0 -15
  191. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +0 -39
  192. data/test/MC/ARM/neont2-add-encoding.s.cs +0 -65
  193. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +0 -15
  194. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +0 -15
  195. data/test/MC/ARM/neont2-cmp-encoding.s.cs +0 -17
  196. data/test/MC/ARM/neont2-convert-encoding.s.cs +0 -19
  197. data/test/MC/ARM/neont2-dup-encoding.s.cs +0 -19
  198. data/test/MC/ARM/neont2-minmax-encoding.s.cs +0 -57
  199. data/test/MC/ARM/neont2-mov-encoding.s.cs +0 -58
  200. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +0 -41
  201. data/test/MC/ARM/neont2-mul-encoding.s.cs +0 -31
  202. data/test/MC/ARM/neont2-neg-encoding.s.cs +0 -15
  203. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +0 -43
  204. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +0 -13
  205. data/test/MC/ARM/neont2-reverse-encoding.s.cs +0 -13
  206. data/test/MC/ARM/neont2-satshift-encoding.s.cs +0 -75
  207. data/test/MC/ARM/neont2-shift-encoding.s.cs +0 -80
  208. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +0 -97
  209. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +0 -23
  210. data/test/MC/ARM/neont2-sub-encoding.s.cs +0 -23
  211. data/test/MC/ARM/neont2-table-encoding.s.cs +0 -9
  212. data/test/MC/ARM/neont2-vld-encoding.s.cs +0 -51
  213. data/test/MC/ARM/neont2-vst-encoding.s.cs +0 -48
  214. data/test/MC/ARM/simple-fp-encoding.s.cs +0 -157
  215. data/test/MC/ARM/thumb-fp-armv8.s.cs +0 -51
  216. data/test/MC/ARM/thumb-hints.s.cs +0 -12
  217. data/test/MC/ARM/thumb-neon-crypto.s.cs +0 -16
  218. data/test/MC/ARM/thumb-neon-v8.s.cs +0 -38
  219. data/test/MC/ARM/thumb-shift-encoding.s.cs +0 -19
  220. data/test/MC/ARM/thumb.s.cs +0 -19
  221. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +0 -2
  222. data/test/MC/ARM/thumb2-branches.s.cs +0 -85
  223. data/test/MC/ARM/thumb2-mclass.s.cs +0 -41
  224. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +0 -379
  225. data/test/MC/ARM/thumb2-pldw.s.cs +0 -2
  226. data/test/MC/ARM/vfp4-thumb.s.cs +0 -13
  227. data/test/MC/ARM/vfp4.s.cs +0 -13
  228. data/test/MC/ARM/vpush-vpop-thumb.s.cs +0 -9
  229. data/test/MC/ARM/vpush-vpop.s.cs +0 -9
  230. data/test/MC/Mips/hilo-addressing.s.cs +0 -4
  231. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +0 -33
  232. data/test/MC/Mips/micromips-alu-instructions.s.cs +0 -33
  233. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +0 -11
  234. data/test/MC/Mips/micromips-branch-instructions.s.cs +0 -11
  235. data/test/MC/Mips/micromips-expansions.s.cs +0 -20
  236. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +0 -5
  237. data/test/MC/Mips/micromips-jump-instructions.s.cs +0 -6
  238. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +0 -9
  239. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +0 -9
  240. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +0 -5
  241. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +0 -5
  242. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +0 -5
  243. data/test/MC/Mips/micromips-movcond-instructions.s.cs +0 -5
  244. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +0 -5
  245. data/test/MC/Mips/micromips-multiply-instructions.s.cs +0 -5
  246. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +0 -9
  247. data/test/MC/Mips/micromips-shift-instructions.s.cs +0 -9
  248. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +0 -13
  249. data/test/MC/Mips/micromips-trap-instructions.s.cs +0 -13
  250. data/test/MC/Mips/mips-alu-instructions.s.cs +0 -53
  251. data/test/MC/Mips/mips-control-instructions-64.s.cs +0 -33
  252. data/test/MC/Mips/mips-control-instructions.s.cs +0 -33
  253. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +0 -17
  254. data/test/MC/Mips/mips-dsp-instructions.s.cs +0 -43
  255. data/test/MC/Mips/mips-expansions.s.cs +0 -20
  256. data/test/MC/Mips/mips-fpu-instructions.s.cs +0 -93
  257. data/test/MC/Mips/mips-jump-instructions.s.cs +0 -1
  258. data/test/MC/Mips/mips-memory-instructions.s.cs +0 -17
  259. data/test/MC/Mips/mips-register-names.s.cs +0 -33
  260. data/test/MC/Mips/mips64-alu-instructions.s.cs +0 -47
  261. data/test/MC/Mips/mips64-instructions.s.cs +0 -3
  262. data/test/MC/Mips/mips64-register-names.s.cs +0 -33
  263. data/test/MC/Mips/mips_directives.s.cs +0 -12
  264. data/test/MC/Mips/nabi-regs.s.cs +0 -12
  265. data/test/MC/Mips/set-at-directive.s.cs +0 -6
  266. data/test/MC/Mips/test_2r.s.cs +0 -16
  267. data/test/MC/Mips/test_2rf.s.cs +0 -33
  268. data/test/MC/Mips/test_3r.s.cs +0 -243
  269. data/test/MC/Mips/test_3rf.s.cs +0 -83
  270. data/test/MC/Mips/test_bit.s.cs +0 -49
  271. data/test/MC/Mips/test_cbranch.s.cs +0 -11
  272. data/test/MC/Mips/test_ctrlregs.s.cs +0 -33
  273. data/test/MC/Mips/test_elm.s.cs +0 -16
  274. data/test/MC/Mips/test_elm_insert.s.cs +0 -4
  275. data/test/MC/Mips/test_elm_insve.s.cs +0 -5
  276. data/test/MC/Mips/test_i10.s.cs +0 -5
  277. data/test/MC/Mips/test_i5.s.cs +0 -45
  278. data/test/MC/Mips/test_i8.s.cs +0 -11
  279. data/test/MC/Mips/test_lsa.s.cs +0 -5
  280. data/test/MC/Mips/test_mi10.s.cs +0 -24
  281. data/test/MC/Mips/test_vec.s.cs +0 -8
  282. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +0 -25
  283. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +0 -35
  284. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +0 -535
  285. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +0 -110
  286. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +0 -170
  287. data/test/MC/PowerPC/ppc64-encoding.s.cs +0 -202
  288. data/test/MC/PowerPC/ppc64-operands.s.cs +0 -32
  289. data/test/MC/README +0 -6
  290. data/test/MC/Sparc/sparc-alu-instructions.s.cs +0 -47
  291. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +0 -7
  292. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +0 -11
  293. data/test/MC/Sparc/sparc-fp-instructions.s.cs +0 -59
  294. data/test/MC/Sparc/sparc-mem-instructions.s.cs +0 -25
  295. data/test/MC/Sparc/sparc-vis.s.cs +0 -2
  296. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +0 -13
  297. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +0 -102
  298. data/test/MC/Sparc/sparcv8-instructions.s.cs +0 -7
  299. data/test/MC/Sparc/sparcv9-instructions.s.cs +0 -1
  300. data/test/MC/SystemZ/insn-good-z196.s.cs +0 -589
  301. data/test/MC/SystemZ/insn-good.s.cs +0 -2265
  302. data/test/MC/SystemZ/regs-good.s.cs +0 -45
  303. data/test/MC/X86/3DNow.s.cs +0 -29
  304. data/test/MC/X86/address-size.s.cs +0 -5
  305. data/test/MC/X86/avx512-encodings.s.cs +0 -12
  306. data/test/MC/X86/intel-syntax-encoding.s.cs +0 -30
  307. data/test/MC/X86/x86-32-avx.s.cs +0 -833
  308. data/test/MC/X86/x86-32-fma3.s.cs +0 -169
  309. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +0 -27
  310. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +0 -11
  311. data/test/MC/X86/x86_64-avx-encoding.s.cs +0 -1058
  312. data/test/MC/X86/x86_64-bmi-encoding.s.cs +0 -51
  313. data/test/MC/X86/x86_64-encoding.s.cs +0 -59
  314. data/test/MC/X86/x86_64-fma3-encoding.s.cs +0 -169
  315. data/test/MC/X86/x86_64-fma4-encoding.s.cs +0 -98
  316. data/test/MC/X86/x86_64-hle-encoding.s.cs +0 -3
  317. data/test/MC/X86/x86_64-imm-widths.s.cs +0 -27
  318. data/test/MC/X86/x86_64-rand-encoding.s.cs +0 -13
  319. data/test/MC/X86/x86_64-rtm-encoding.s.cs +0 -4
  320. data/test/MC/X86/x86_64-sse4a.s.cs +0 -1
  321. data/test/MC/X86/x86_64-tbm-encoding.s.cs +0 -40
  322. data/test/MC/X86/x86_64-xop-encoding.s.cs +0 -152
  323. data/test/README +0 -6
  324. data/test/test.rb +0 -205
  325. data/test/test.rb.SPEC +0 -235
  326. data/test/test_arm.rb +0 -202
  327. data/test/test_arm.rb.SPEC +0 -275
  328. data/test/test_arm64.rb +0 -150
  329. data/test/test_arm64.rb.SPEC +0 -116
  330. data/test/test_detail.rb +0 -228
  331. data/test/test_detail.rb.SPEC +0 -322
  332. data/test/test_exhaustive.rb +0 -80
  333. data/test/test_mips.rb +0 -118
  334. data/test/test_mips.rb.SPEC +0 -91
  335. data/test/test_ppc.rb +0 -137
  336. data/test/test_ppc.rb.SPEC +0 -84
  337. data/test/test_sanity.rb +0 -83
  338. data/test/test_skipdata.rb +0 -111
  339. data/test/test_skipdata.rb.SPEC +0 -58
  340. data/test/test_sparc.rb +0 -113
  341. data/test/test_sparc.rb.SPEC +0 -116
  342. data/test/test_sysz.rb +0 -111
  343. data/test/test_sysz.rb.SPEC +0 -61
  344. data/test/test_x86.rb +0 -189
  345. data/test/test_x86.rb.SPEC +0 -579
  346. data/test/test_xcore.rb +0 -100
  347. data/test/test_xcore.rb.SPEC +0 -75
data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs DELETED
@@ -1,107 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x00,0x70,0xc1,0x4c = ld1 {v0.16b}, [x0], x1
3
- 0xef,0x75,0xc2,0x4c = ld1 {v15.8h}, [x15], x2
4
- 0xff,0x7b,0xdf,0x4c = ld1 {v31.4s}, [sp], #16
5
- 0x00,0x7c,0xdf,0x4c = ld1 {v0.2d}, [x0], #16
6
- 0x00,0x70,0xc2,0x0c = ld1 {v0.8b}, [x0], x2
7
- 0xef,0x75,0xc3,0x0c = ld1 {v15.4h}, [x15], x3
8
- 0xff,0x7b,0xdf,0x0c = ld1 {v31.2s}, [sp], #8
9
- 0x00,0x7c,0xdf,0x0c = ld1 {v0.1d}, [x0], #8
10
- 0x00,0xa0,0xc1,0x4c = ld1 {v0.16b, v1.16b}, [x0], x1
11
- 0xef,0xa5,0xc2,0x4c = ld1 {v15.8h, v16.8h}, [x15], x2
12
- 0xff,0xab,0xdf,0x4c = ld1 {v31.4s, v0.4s}, [sp], #32
13
- 0x00,0xac,0xdf,0x4c = ld1 {v0.2d, v1.2d}, [x0], #32
14
- 0x00,0xa0,0xc2,0x0c = ld1 {v0.8b, v1.8b}, [x0], x2
15
- 0xef,0xa5,0xc3,0x0c = ld1 {v15.4h, v16.4h}, [x15], x3
16
- 0xff,0xab,0xdf,0x0c = ld1 {v31.2s, v0.2s}, [sp], #16
17
- 0x00,0xac,0xdf,0x0c = ld1 {v0.1d, v1.1d}, [x0], #16
18
- 0x00,0x60,0xc1,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1
19
- 0xef,0x65,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2
20
- 0xff,0x6b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48
21
- 0x00,0x6c,0xdf,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48
22
- 0x00,0x60,0xc2,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2
23
- 0xef,0x65,0xc3,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3
24
- 0xff,0x6b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24
25
- 0x00,0x6c,0xdf,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24
26
- 0x00,0x20,0xc1,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
27
- 0xef,0x25,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
28
- 0xff,0x2b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
29
- 0x00,0x2c,0xdf,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
30
- 0x00,0x20,0xc3,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
31
- 0xef,0x25,0xc4,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
32
- 0xff,0x2b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
33
- 0x00,0x2c,0xdf,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32
34
- 0x00,0x80,0xc1,0x4c = ld2 {v0.16b, v1.16b}, [x0], x1
35
- 0xef,0x85,0xc2,0x4c = ld2 {v15.8h, v16.8h}, [x15], x2
36
- 0xff,0x8b,0xdf,0x4c = ld2 {v31.4s, v0.4s}, [sp], #32
37
- 0x00,0x8c,0xdf,0x4c = ld2 {v0.2d, v1.2d}, [x0], #32
38
- 0x00,0x80,0xc2,0x0c = ld2 {v0.8b, v1.8b}, [x0], x2
39
- 0xef,0x85,0xc3,0x0c = ld2 {v15.4h, v16.4h}, [x15], x3
40
- 0xff,0x8b,0xdf,0x0c = ld2 {v31.2s, v0.2s}, [sp], #16
41
- 0x00,0x40,0xc1,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1
42
- 0xef,0x45,0xc2,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2
43
- 0xff,0x4b,0xdf,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48
44
- 0x00,0x4c,0xdf,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48
45
- 0x00,0x40,0xc2,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2
46
- 0xef,0x45,0xc3,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3
47
- 0xff,0x4b,0xdf,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24
48
- 0x00,0x00,0xc1,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
49
- 0xef,0x05,0xc2,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
50
- 0xff,0x0b,0xdf,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
51
- 0x00,0x0c,0xdf,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
52
- 0x00,0x00,0xc3,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
53
- 0xef,0x05,0xc4,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
54
- 0xff,0x0b,0xdf,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
55
- 0x00,0x70,0x81,0x4c = st1 {v0.16b}, [x0], x1
56
- 0xef,0x75,0x82,0x4c = st1 {v15.8h}, [x15], x2
57
- 0xff,0x7b,0x9f,0x4c = st1 {v31.4s}, [sp], #16
58
- 0x00,0x7c,0x9f,0x4c = st1 {v0.2d}, [x0], #16
59
- 0x00,0x70,0x82,0x0c = st1 {v0.8b}, [x0], x2
60
- 0xef,0x75,0x83,0x0c = st1 {v15.4h}, [x15], x3
61
- 0xff,0x7b,0x9f,0x0c = st1 {v31.2s}, [sp], #8
62
- 0x00,0x7c,0x9f,0x0c = st1 {v0.1d}, [x0], #8
63
- 0x00,0xa0,0x81,0x4c = st1 {v0.16b, v1.16b}, [x0], x1
64
- 0xef,0xa5,0x82,0x4c = st1 {v15.8h, v16.8h}, [x15], x2
65
- 0xff,0xab,0x9f,0x4c = st1 {v31.4s, v0.4s}, [sp], #32
66
- 0x00,0xac,0x9f,0x4c = st1 {v0.2d, v1.2d}, [x0], #32
67
- 0x00,0xa0,0x82,0x0c = st1 {v0.8b, v1.8b}, [x0], x2
68
- 0xef,0xa5,0x83,0x0c = st1 {v15.4h, v16.4h}, [x15], x3
69
- 0xff,0xab,0x9f,0x0c = st1 {v31.2s, v0.2s}, [sp], #16
70
- 0x00,0xac,0x9f,0x0c = st1 {v0.1d, v1.1d}, [x0], #16
71
- 0x00,0x60,0x81,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0], x1
72
- 0xef,0x65,0x82,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15], x2
73
- 0xff,0x6b,0x9f,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp], #48
74
- 0x00,0x6c,0x9f,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0], #48
75
- 0x00,0x60,0x82,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0], x2
76
- 0xef,0x65,0x83,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15], x3
77
- 0xff,0x6b,0x9f,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp], #24
78
- 0x00,0x6c,0x9f,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0], #24
79
- 0x00,0x20,0x81,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
80
- 0xef,0x25,0x82,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
81
- 0xff,0x2b,0x9f,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
82
- 0x00,0x2c,0x9f,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
83
- 0x00,0x20,0x83,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
84
- 0xef,0x25,0x84,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
85
- 0xff,0x2b,0x9f,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
86
- 0x00,0x2c,0x9f,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32
87
- 0x00,0x80,0x81,0x4c = st2 {v0.16b, v1.16b}, [x0], x1
88
- 0xef,0x85,0x82,0x4c = st2 {v15.8h, v16.8h}, [x15], x2
89
- 0xff,0x8b,0x9f,0x4c = st2 {v31.4s, v0.4s}, [sp], #32
90
- 0x00,0x8c,0x9f,0x4c = st2 {v0.2d, v1.2d}, [x0], #32
91
- 0x00,0x80,0x82,0x0c = st2 {v0.8b, v1.8b}, [x0], x2
92
- 0xef,0x85,0x83,0x0c = st2 {v15.4h, v16.4h}, [x15], x3
93
- 0xff,0x8b,0x9f,0x0c = st2 {v31.2s, v0.2s}, [sp], #16
94
- 0x00,0x40,0x81,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0], x1
95
- 0xef,0x45,0x82,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15], x2
96
- 0xff,0x4b,0x9f,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp], #48
97
- 0x00,0x4c,0x9f,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0], #48
98
- 0x00,0x40,0x82,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0], x2
99
- 0xef,0x45,0x83,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15], x3
100
- 0xff,0x4b,0x9f,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp], #24
101
- 0x00,0x00,0x81,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1
102
- 0xef,0x05,0x82,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2
103
- 0xff,0x0b,0x9f,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64
104
- 0x00,0x0c,0x9f,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
105
- 0x00,0x00,0x83,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3
106
- 0xef,0x05,0x84,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4
107
- 0xff,0x0b,0x9f,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32
data/test/MC/AArch64/neon-simd-shift.s.cs DELETED
@@ -1,151 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x20,0x04,0x0d,0x0f = sshr v0.8b, v1.8b, #3
3
- 0x20,0x04,0x1d,0x0f = sshr v0.4h, v1.4h, #3
4
- 0x20,0x04,0x3d,0x0f = sshr v0.2s, v1.2s, #3
5
- 0x20,0x04,0x0d,0x4f = sshr v0.16b, v1.16b, #3
6
- 0x20,0x04,0x1d,0x4f = sshr v0.8h, v1.8h, #3
7
- 0x20,0x04,0x3d,0x4f = sshr v0.4s, v1.4s, #3
8
- 0x20,0x04,0x7d,0x4f = sshr v0.2d, v1.2d, #3
9
- 0x20,0x04,0x0d,0x2f = ushr v0.8b, v1.8b, #3
10
- 0x20,0x04,0x1d,0x2f = ushr v0.4h, v1.4h, #3
11
- 0x20,0x04,0x3d,0x2f = ushr v0.2s, v1.2s, #3
12
- 0x20,0x04,0x0d,0x6f = ushr v0.16b, v1.16b, #3
13
- 0x20,0x04,0x1d,0x6f = ushr v0.8h, v1.8h, #3
14
- 0x20,0x04,0x3d,0x6f = ushr v0.4s, v1.4s, #3
15
- 0x20,0x04,0x7d,0x6f = ushr v0.2d, v1.2d, #3
16
- 0x20,0x14,0x0d,0x0f = ssra v0.8b, v1.8b, #3
17
- 0x20,0x14,0x1d,0x0f = ssra v0.4h, v1.4h, #3
18
- 0x20,0x14,0x3d,0x0f = ssra v0.2s, v1.2s, #3
19
- 0x20,0x14,0x0d,0x4f = ssra v0.16b, v1.16b, #3
20
- 0x20,0x14,0x1d,0x4f = ssra v0.8h, v1.8h, #3
21
- 0x20,0x14,0x3d,0x4f = ssra v0.4s, v1.4s, #3
22
- 0x20,0x14,0x7d,0x4f = ssra v0.2d, v1.2d, #3
23
- 0x20,0x14,0x0d,0x2f = usra v0.8b, v1.8b, #3
24
- 0x20,0x14,0x1d,0x2f = usra v0.4h, v1.4h, #3
25
- 0x20,0x14,0x3d,0x2f = usra v0.2s, v1.2s, #3
26
- 0x20,0x14,0x0d,0x6f = usra v0.16b, v1.16b, #3
27
- 0x20,0x14,0x1d,0x6f = usra v0.8h, v1.8h, #3
28
- 0x20,0x14,0x3d,0x6f = usra v0.4s, v1.4s, #3
29
- 0x20,0x14,0x7d,0x6f = usra v0.2d, v1.2d, #3
30
- 0x20,0x24,0x0d,0x0f = srshr v0.8b, v1.8b, #3
31
- 0x20,0x24,0x1d,0x0f = srshr v0.4h, v1.4h, #3
32
- 0x20,0x24,0x3d,0x0f = srshr v0.2s, v1.2s, #3
33
- 0x20,0x24,0x0d,0x4f = srshr v0.16b, v1.16b, #3
34
- 0x20,0x24,0x1d,0x4f = srshr v0.8h, v1.8h, #3
35
- 0x20,0x24,0x3d,0x4f = srshr v0.4s, v1.4s, #3
36
- 0x20,0x24,0x7d,0x4f = srshr v0.2d, v1.2d, #3
37
- 0x20,0x24,0x0d,0x2f = urshr v0.8b, v1.8b, #3
38
- 0x20,0x24,0x1d,0x2f = urshr v0.4h, v1.4h, #3
39
- 0x20,0x24,0x3d,0x2f = urshr v0.2s, v1.2s, #3
40
- 0x20,0x24,0x0d,0x6f = urshr v0.16b, v1.16b, #3
41
- 0x20,0x24,0x1d,0x6f = urshr v0.8h, v1.8h, #3
42
- 0x20,0x24,0x3d,0x6f = urshr v0.4s, v1.4s, #3
43
- 0x20,0x24,0x7d,0x6f = urshr v0.2d, v1.2d, #3
44
- 0x20,0x34,0x0d,0x0f = srsra v0.8b, v1.8b, #3
45
- 0x20,0x34,0x1d,0x0f = srsra v0.4h, v1.4h, #3
46
- 0x20,0x34,0x3d,0x0f = srsra v0.2s, v1.2s, #3
47
- 0x20,0x34,0x0d,0x4f = srsra v0.16b, v1.16b, #3
48
- 0x20,0x34,0x1d,0x4f = srsra v0.8h, v1.8h, #3
49
- 0x20,0x34,0x3d,0x4f = srsra v0.4s, v1.4s, #3
50
- 0x20,0x34,0x7d,0x4f = srsra v0.2d, v1.2d, #3
51
- 0x20,0x34,0x0d,0x2f = ursra v0.8b, v1.8b, #3
52
- 0x20,0x34,0x1d,0x2f = ursra v0.4h, v1.4h, #3
53
- 0x20,0x34,0x3d,0x2f = ursra v0.2s, v1.2s, #3
54
- 0x20,0x34,0x0d,0x6f = ursra v0.16b, v1.16b, #3
55
- 0x20,0x34,0x1d,0x6f = ursra v0.8h, v1.8h, #3
56
- 0x20,0x34,0x3d,0x6f = ursra v0.4s, v1.4s, #3
57
- 0x20,0x34,0x7d,0x6f = ursra v0.2d, v1.2d, #3
58
- 0x20,0x44,0x0d,0x2f = sri v0.8b, v1.8b, #3
59
- 0x20,0x44,0x1d,0x2f = sri v0.4h, v1.4h, #3
60
- 0x20,0x44,0x3d,0x2f = sri v0.2s, v1.2s, #3
61
- 0x20,0x44,0x0d,0x6f = sri v0.16b, v1.16b, #3
62
- 0x20,0x44,0x1d,0x6f = sri v0.8h, v1.8h, #3
63
- 0x20,0x44,0x3d,0x6f = sri v0.4s, v1.4s, #3
64
- 0x20,0x54,0x0b,0x2f = sli v0.8b, v1.8b, #3
65
- 0x20,0x54,0x13,0x2f = sli v0.4h, v1.4h, #3
66
- 0x20,0x54,0x23,0x2f = sli v0.2s, v1.2s, #3
67
- 0x20,0x54,0x0b,0x6f = sli v0.16b, v1.16b, #3
68
- 0x20,0x54,0x13,0x6f = sli v0.8h, v1.8h, #3
69
- 0x20,0x54,0x23,0x6f = sli v0.4s, v1.4s, #3
70
- 0x20,0x54,0x43,0x6f = sli v0.2d, v1.2d, #3
71
- 0x20,0x64,0x0b,0x2f = sqshlu v0.8b, v1.8b, #3
72
- 0x20,0x64,0x13,0x2f = sqshlu v0.4h, v1.4h, #3
73
- 0x20,0x64,0x23,0x2f = sqshlu v0.2s, v1.2s, #3
74
- 0x20,0x64,0x0b,0x6f = sqshlu v0.16b, v1.16b, #3
75
- 0x20,0x64,0x13,0x6f = sqshlu v0.8h, v1.8h, #3
76
- 0x20,0x64,0x23,0x6f = sqshlu v0.4s, v1.4s, #3
77
- 0x20,0x64,0x43,0x6f = sqshlu v0.2d, v1.2d, #3
78
- 0x20,0x74,0x0b,0x0f = sqshl v0.8b, v1.8b, #3
79
- 0x20,0x74,0x13,0x0f = sqshl v0.4h, v1.4h, #3
80
- 0x20,0x74,0x23,0x0f = sqshl v0.2s, v1.2s, #3
81
- 0x20,0x74,0x0b,0x4f = sqshl v0.16b, v1.16b, #3
82
- 0x20,0x74,0x13,0x4f = sqshl v0.8h, v1.8h, #3
83
- 0x20,0x74,0x23,0x4f = sqshl v0.4s, v1.4s, #3
84
- 0x20,0x74,0x43,0x4f = sqshl v0.2d, v1.2d, #3
85
- 0x20,0x74,0x0b,0x2f = uqshl v0.8b, v1.8b, #3
86
- 0x20,0x74,0x13,0x2f = uqshl v0.4h, v1.4h, #3
87
- 0x20,0x74,0x23,0x2f = uqshl v0.2s, v1.2s, #3
88
- 0x20,0x74,0x0b,0x6f = uqshl v0.16b, v1.16b, #3
89
- 0x20,0x74,0x13,0x6f = uqshl v0.8h, v1.8h, #3
90
- 0x20,0x74,0x23,0x6f = uqshl v0.4s, v1.4s, #3
91
- 0x20,0x74,0x43,0x6f = uqshl v0.2d, v1.2d, #3
92
- 0x20,0x84,0x0d,0x0f = shrn v0.8b, v1.8h, #3
93
- 0x20,0x84,0x1d,0x0f = shrn v0.4h, v1.4s, #3
94
- 0x20,0x84,0x3d,0x0f = shrn v0.2s, v1.2d, #3
95
- 0x20,0x84,0x0d,0x4f = shrn2 v0.16b, v1.8h, #3
96
- 0x20,0x84,0x1d,0x4f = shrn2 v0.8h, v1.4s, #3
97
- 0x20,0x84,0x3d,0x4f = shrn2 v0.4s, v1.2d, #3
98
- 0x20,0x84,0x0d,0x2f = sqshrun v0.8b, v1.8h, #3
99
- 0x20,0x84,0x1d,0x2f = sqshrun v0.4h, v1.4s, #3
100
- 0x20,0x84,0x3d,0x2f = sqshrun v0.2s, v1.2d, #3
101
- 0x20,0x84,0x0d,0x6f = sqshrun2 v0.16b, v1.8h, #3
102
- 0x20,0x84,0x1d,0x6f = sqshrun2 v0.8h, v1.4s, #3
103
- 0x20,0x84,0x3d,0x6f = sqshrun2 v0.4s, v1.2d, #3
104
- 0x20,0x8c,0x0d,0x0f = rshrn v0.8b, v1.8h, #3
105
- 0x20,0x8c,0x1d,0x0f = rshrn v0.4h, v1.4s, #3
106
- 0x20,0x8c,0x3d,0x0f = rshrn v0.2s, v1.2d, #3
107
- 0x20,0x8c,0x0d,0x4f = rshrn2 v0.16b, v1.8h, #3
108
- 0x20,0x8c,0x1d,0x4f = rshrn2 v0.8h, v1.4s, #3
109
- 0x20,0x8c,0x3d,0x4f = rshrn2 v0.4s, v1.2d, #3
110
- 0x20,0x8c,0x0d,0x2f = sqrshrun v0.8b, v1.8h, #3
111
- 0x20,0x8c,0x1d,0x2f = sqrshrun v0.4h, v1.4s, #3
112
- 0x20,0x8c,0x3d,0x2f = sqrshrun v0.2s, v1.2d, #3
113
- 0x20,0x8c,0x0d,0x6f = sqrshrun2 v0.16b, v1.8h, #3
114
- 0x20,0x8c,0x1d,0x6f = sqrshrun2 v0.8h, v1.4s, #3
115
- 0x20,0x8c,0x3d,0x6f = sqrshrun2 v0.4s, v1.2d, #3
116
- 0x20,0x94,0x0d,0x0f = sqshrn v0.8b, v1.8h, #3
117
- 0x20,0x94,0x1d,0x0f = sqshrn v0.4h, v1.4s, #3
118
- 0x20,0x94,0x3d,0x0f = sqshrn v0.2s, v1.2d, #3
119
- 0x20,0x94,0x0d,0x4f = sqshrn2 v0.16b, v1.8h, #3
120
- 0x20,0x94,0x1d,0x4f = sqshrn2 v0.8h, v1.4s, #3
121
- 0x20,0x94,0x3d,0x4f = sqshrn2 v0.4s, v1.2d, #3
122
- 0x20,0x94,0x0d,0x2f = uqshrn v0.8b, v1.8h, #3
123
- 0x20,0x94,0x1d,0x2f = uqshrn v0.4h, v1.4s, #3
124
- 0x20,0x94,0x3d,0x2f = uqshrn v0.2s, v1.2d, #3
125
- 0x20,0x94,0x0d,0x6f = uqshrn2 v0.16b, v1.8h, #3
126
- 0x20,0x94,0x1d,0x6f = uqshrn2 v0.8h, v1.4s, #3
127
- 0x20,0x94,0x3d,0x6f = uqshrn2 v0.4s, v1.2d, #3
128
- 0x20,0x9c,0x0d,0x0f = sqrshrn v0.8b, v1.8h, #3
129
- 0x20,0x9c,0x1d,0x0f = sqrshrn v0.4h, v1.4s, #3
130
- 0x20,0x9c,0x3d,0x0f = sqrshrn v0.2s, v1.2d, #3
131
- 0x20,0x9c,0x0d,0x4f = sqrshrn2 v0.16b, v1.8h, #3
132
- 0x20,0x9c,0x1d,0x4f = sqrshrn2 v0.8h, v1.4s, #3
133
- 0x20,0x9c,0x3d,0x4f = sqrshrn2 v0.4s, v1.2d, #3
134
- 0x20,0x9c,0x0d,0x2f = uqrshrn v0.8b, v1.8h, #3
135
- 0x20,0x9c,0x1d,0x2f = uqrshrn v0.4h, v1.4s, #3
136
- 0x20,0x9c,0x3d,0x2f = uqrshrn v0.2s, v1.2d, #3
137
- 0x20,0x9c,0x0d,0x6f = uqrshrn2 v0.16b, v1.8h, #3
138
- 0x20,0x9c,0x1d,0x6f = uqrshrn2 v0.8h, v1.4s, #3
139
- 0x20,0x9c,0x3d,0x6f = uqrshrn2 v0.4s, v1.2d, #3
140
- 0x20,0xe4,0x3d,0x0f = scvtf v0.2s, v1.2s, #3
141
- 0x20,0xe4,0x3d,0x4f = scvtf v0.4s, v1.4s, #3
142
- 0x20,0xe4,0x7d,0x4f = scvtf v0.2d, v1.2d, #3
143
- 0x20,0xe4,0x3d,0x2f = ucvtf v0.2s, v1.2s, #3
144
- 0x20,0xe4,0x3d,0x6f = ucvtf v0.4s, v1.4s, #3
145
- 0x20,0xe4,0x7d,0x6f = ucvtf v0.2d, v1.2d, #3
146
- 0x20,0xfc,0x3d,0x0f = fcvtzs v0.2s, v1.2s, #3
147
- 0x20,0xfc,0x3d,0x4f = fcvtzs v0.4s, v1.4s, #3
148
- 0x20,0xfc,0x7d,0x4f = fcvtzs v0.2d, v1.2d, #3
149
- 0x20,0xfc,0x3d,0x2f = fcvtzu v0.2s, v1.2s, #3
150
- 0x20,0xfc,0x3d,0x6f = fcvtzu v0.4s, v1.4s, #3
151
- 0x20,0xfc,0x7d,0x6f = fcvtzu v0.2d, v1.2d, #3
data/test/MC/AArch64/neon-tbl.s.cs DELETED
@@ -1,21 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x20,0x00,0x02,0x0e = tbl v0.8b, {v1.16b}, v2.8b
3
- 0x20,0x20,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b}, v2.8b
4
- 0x20,0x40,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
5
- 0x20,0x60,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b
6
- 0xe0,0x63,0x02,0x0e = tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b
7
- 0x20,0x00,0x02,0x4e = tbl v0.16b, {v1.16b}, v2.16b
8
- 0x20,0x20,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b}, v2.16b
9
- 0x20,0x40,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
10
- 0x20,0x60,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b
11
- 0xc0,0x63,0x02,0x4e = tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b
12
- 0x20,0x10,0x02,0x0e = tbx v0.8b, {v1.16b}, v2.8b
13
- 0x20,0x30,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b}, v2.8b
14
- 0x20,0x50,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
15
- 0x20,0x70,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b
16
- 0xe0,0x73,0x02,0x0e = tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b
17
- 0x20,0x10,0x02,0x4e = tbx v0.16b, {v1.16b}, v2.16b
18
- 0x20,0x30,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b}, v2.16b
19
- 0x20,0x50,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
20
- 0x20,0x70,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b
21
- 0xc0,0x73,0x02,0x4e = tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b
data/test/MC/AArch64/trace-regs.s.cs DELETED
@@ -1,383 +0,0 @@
1
- # CS_ARCH_ARM64, 0, None
2
- 0x08,0x03,0x31,0xd5 = mrs x8, trcstatr
3
- 0xc9,0x00,0x31,0xd5 = mrs x9, trcidr8
4
- 0xcb,0x01,0x31,0xd5 = mrs x11, trcidr9
5
- 0xd9,0x02,0x31,0xd5 = mrs x25, trcidr10
6
- 0xc7,0x03,0x31,0xd5 = mrs x7, trcidr11
7
- 0xc7,0x04,0x31,0xd5 = mrs x7, trcidr12
8
- 0xc6,0x05,0x31,0xd5 = mrs x6, trcidr13
9
- 0xfb,0x08,0x31,0xd5 = mrs x27, trcidr0
10
- 0xfd,0x09,0x31,0xd5 = mrs x29, trcidr1
11
- 0xe4,0x0a,0x31,0xd5 = mrs x4, trcidr2
12
- 0xe8,0x0b,0x31,0xd5 = mrs x8, trcidr3
13
- 0xef,0x0c,0x31,0xd5 = mrs x15, trcidr4
14
- 0xf4,0x0d,0x31,0xd5 = mrs x20, trcidr5
15
- 0xe6,0x0e,0x31,0xd5 = mrs x6, trcidr6
16
- 0xe6,0x0f,0x31,0xd5 = mrs x6, trcidr7
17
- 0x98,0x11,0x31,0xd5 = mrs x24, trcoslsr
18
- 0x92,0x15,0x31,0xd5 = mrs x18, trcpdsr
19
- 0xdc,0x7a,0x31,0xd5 = mrs x28, trcdevaff0
20
- 0xc5,0x7b,0x31,0xd5 = mrs x5, trcdevaff1
21
- 0xc5,0x7d,0x31,0xd5 = mrs x5, trclsr
22
- 0xcb,0x7e,0x31,0xd5 = mrs x11, trcauthstatus
23
- 0xcd,0x7f,0x31,0xd5 = mrs x13, trcdevarch
24
- 0xf2,0x72,0x31,0xd5 = mrs x18, trcdevid
25
- 0xf6,0x73,0x31,0xd5 = mrs x22, trcdevtype
26
- 0xee,0x74,0x31,0xd5 = mrs x14, trcpidr4
27
- 0xe5,0x75,0x31,0xd5 = mrs x5, trcpidr5
28
- 0xe5,0x76,0x31,0xd5 = mrs x5, trcpidr6
29
- 0xe9,0x77,0x31,0xd5 = mrs x9, trcpidr7
30
- 0xef,0x78,0x31,0xd5 = mrs x15, trcpidr0
31
- 0xe6,0x79,0x31,0xd5 = mrs x6, trcpidr1
32
- 0xeb,0x7a,0x31,0xd5 = mrs x11, trcpidr2
33
- 0xf4,0x7b,0x31,0xd5 = mrs x20, trcpidr3
34
- 0xf1,0x7c,0x31,0xd5 = mrs x17, trccidr0
35
- 0xe2,0x7d,0x31,0xd5 = mrs x2, trccidr1
36
- 0xf4,0x7e,0x31,0xd5 = mrs x20, trccidr2
37
- 0xe4,0x7f,0x31,0xd5 = mrs x4, trccidr3
38
- 0x0b,0x01,0x31,0xd5 = mrs x11, trcprgctlr
39
- 0x17,0x02,0x31,0xd5 = mrs x23, trcprocselr
40
- 0x0d,0x04,0x31,0xd5 = mrs x13, trcconfigr
41
- 0x17,0x06,0x31,0xd5 = mrs x23, trcauxctlr
42
- 0x09,0x08,0x31,0xd5 = mrs x9, trceventctl0r
43
- 0x10,0x09,0x31,0xd5 = mrs x16, trceventctl1r
44
- 0x04,0x0b,0x31,0xd5 = mrs x4, trcstallctlr
45
- 0x0e,0x0c,0x31,0xd5 = mrs x14, trctsctlr
46
- 0x18,0x0d,0x31,0xd5 = mrs x24, trcsyncpr
47
- 0x1c,0x0e,0x31,0xd5 = mrs x28, trcccctlr
48
- 0x0f,0x0f,0x31,0xd5 = mrs x15, trcbbctlr
49
- 0x21,0x00,0x31,0xd5 = mrs x1, trctraceidr
50
- 0x34,0x01,0x31,0xd5 = mrs x20, trcqctlr
51
- 0x42,0x00,0x31,0xd5 = mrs x2, trcvictlr
52
- 0x4c,0x01,0x31,0xd5 = mrs x12, trcviiectlr
53
- 0x50,0x02,0x31,0xd5 = mrs x16, trcvissctlr
54
- 0x48,0x03,0x31,0xd5 = mrs x8, trcvipcssctlr
55
- 0x5b,0x08,0x31,0xd5 = mrs x27, trcvdctlr
56
- 0x49,0x09,0x31,0xd5 = mrs x9, trcvdsacctlr
57
- 0x40,0x0a,0x31,0xd5 = mrs x0, trcvdarcctlr
58
- 0x8d,0x00,0x31,0xd5 = mrs x13, trcseqevr0
59
- 0x8b,0x01,0x31,0xd5 = mrs x11, trcseqevr1
60
- 0x9a,0x02,0x31,0xd5 = mrs x26, trcseqevr2
61
- 0x8e,0x06,0x31,0xd5 = mrs x14, trcseqrstevr
62
- 0x84,0x07,0x31,0xd5 = mrs x4, trcseqstr
63
- 0x91,0x08,0x31,0xd5 = mrs x17, trcextinselr
64
- 0xb5,0x00,0x31,0xd5 = mrs x21, trccntrldvr0
65
- 0xaa,0x01,0x31,0xd5 = mrs x10, trccntrldvr1
66
- 0xb4,0x02,0x31,0xd5 = mrs x20, trccntrldvr2
67
- 0xa5,0x03,0x31,0xd5 = mrs x5, trccntrldvr3
68
- 0xb1,0x04,0x31,0xd5 = mrs x17, trccntctlr0
69
- 0xa1,0x05,0x31,0xd5 = mrs x1, trccntctlr1
70
- 0xb1,0x06,0x31,0xd5 = mrs x17, trccntctlr2
71
- 0xa6,0x07,0x31,0xd5 = mrs x6, trccntctlr3
72
- 0xbc,0x08,0x31,0xd5 = mrs x28, trccntvr0
73
- 0xb7,0x09,0x31,0xd5 = mrs x23, trccntvr1
74
- 0xa9,0x0a,0x31,0xd5 = mrs x9, trccntvr2
75
- 0xa6,0x0b,0x31,0xd5 = mrs x6, trccntvr3
76
- 0xf8,0x00,0x31,0xd5 = mrs x24, trcimspec0
77
- 0xf8,0x01,0x31,0xd5 = mrs x24, trcimspec1
78
- 0xef,0x02,0x31,0xd5 = mrs x15, trcimspec2
79
- 0xea,0x03,0x31,0xd5 = mrs x10, trcimspec3
80
- 0xfd,0x04,0x31,0xd5 = mrs x29, trcimspec4
81
- 0xf2,0x05,0x31,0xd5 = mrs x18, trcimspec5
82
- 0xfd,0x06,0x31,0xd5 = mrs x29, trcimspec6
83
- 0xe2,0x07,0x31,0xd5 = mrs x2, trcimspec7
84
- 0x08,0x12,0x31,0xd5 = mrs x8, trcrsctlr2
85
- 0x00,0x13,0x31,0xd5 = mrs x0, trcrsctlr3
86
- 0x0c,0x14,0x31,0xd5 = mrs x12, trcrsctlr4
87
- 0x1a,0x15,0x31,0xd5 = mrs x26, trcrsctlr5
88
- 0x1d,0x16,0x31,0xd5 = mrs x29, trcrsctlr6
89
- 0x11,0x17,0x31,0xd5 = mrs x17, trcrsctlr7
90
- 0x00,0x18,0x31,0xd5 = mrs x0, trcrsctlr8
91
- 0x01,0x19,0x31,0xd5 = mrs x1, trcrsctlr9
92
- 0x11,0x1a,0x31,0xd5 = mrs x17, trcrsctlr10
93
- 0x15,0x1b,0x31,0xd5 = mrs x21, trcrsctlr11
94
- 0x01,0x1c,0x31,0xd5 = mrs x1, trcrsctlr12
95
- 0x08,0x1d,0x31,0xd5 = mrs x8, trcrsctlr13
96
- 0x18,0x1e,0x31,0xd5 = mrs x24, trcrsctlr14
97
- 0x00,0x1f,0x31,0xd5 = mrs x0, trcrsctlr15
98
- 0x22,0x10,0x31,0xd5 = mrs x2, trcrsctlr16
99
- 0x3d,0x11,0x31,0xd5 = mrs x29, trcrsctlr17
100
- 0x36,0x12,0x31,0xd5 = mrs x22, trcrsctlr18
101
- 0x26,0x13,0x31,0xd5 = mrs x6, trcrsctlr19
102
- 0x3a,0x14,0x31,0xd5 = mrs x26, trcrsctlr20
103
- 0x3a,0x15,0x31,0xd5 = mrs x26, trcrsctlr21
104
- 0x24,0x16,0x31,0xd5 = mrs x4, trcrsctlr22
105
- 0x2c,0x17,0x31,0xd5 = mrs x12, trcrsctlr23
106
- 0x21,0x18,0x31,0xd5 = mrs x1, trcrsctlr24
107
- 0x20,0x19,0x31,0xd5 = mrs x0, trcrsctlr25
108
- 0x31,0x1a,0x31,0xd5 = mrs x17, trcrsctlr26
109
- 0x28,0x1b,0x31,0xd5 = mrs x8, trcrsctlr27
110
- 0x2a,0x1c,0x31,0xd5 = mrs x10, trcrsctlr28
111
- 0x39,0x1d,0x31,0xd5 = mrs x25, trcrsctlr29
112
- 0x2c,0x1e,0x31,0xd5 = mrs x12, trcrsctlr30
113
- 0x2b,0x1f,0x31,0xd5 = mrs x11, trcrsctlr31
114
- 0x52,0x10,0x31,0xd5 = mrs x18, trcssccr0
115
- 0x4c,0x11,0x31,0xd5 = mrs x12, trcssccr1
116
- 0x43,0x12,0x31,0xd5 = mrs x3, trcssccr2
117
- 0x42,0x13,0x31,0xd5 = mrs x2, trcssccr3
118
- 0x55,0x14,0x31,0xd5 = mrs x21, trcssccr4
119
- 0x4a,0x15,0x31,0xd5 = mrs x10, trcssccr5
120
- 0x56,0x16,0x31,0xd5 = mrs x22, trcssccr6
121
- 0x57,0x17,0x31,0xd5 = mrs x23, trcssccr7
122
- 0x57,0x18,0x31,0xd5 = mrs x23, trcsscsr0
123
- 0x53,0x19,0x31,0xd5 = mrs x19, trcsscsr1
124
- 0x59,0x1a,0x31,0xd5 = mrs x25, trcsscsr2
125
- 0x51,0x1b,0x31,0xd5 = mrs x17, trcsscsr3
126
- 0x53,0x1c,0x31,0xd5 = mrs x19, trcsscsr4
127
- 0x4b,0x1d,0x31,0xd5 = mrs x11, trcsscsr5
128
- 0x45,0x1e,0x31,0xd5 = mrs x5, trcsscsr6
129
- 0x49,0x1f,0x31,0xd5 = mrs x9, trcsscsr7
130
- 0x61,0x10,0x31,0xd5 = mrs x1, trcsspcicr0
131
- 0x6c,0x11,0x31,0xd5 = mrs x12, trcsspcicr1
132
- 0x75,0x12,0x31,0xd5 = mrs x21, trcsspcicr2
133
- 0x6b,0x13,0x31,0xd5 = mrs x11, trcsspcicr3
134
- 0x63,0x14,0x31,0xd5 = mrs x3, trcsspcicr4
135
- 0x69,0x15,0x31,0xd5 = mrs x9, trcsspcicr5
136
- 0x65,0x16,0x31,0xd5 = mrs x5, trcsspcicr6
137
- 0x62,0x17,0x31,0xd5 = mrs x2, trcsspcicr7
138
- 0x9a,0x14,0x31,0xd5 = mrs x26, trcpdcr
139
- 0x08,0x20,0x31,0xd5 = mrs x8, trcacvr0
140
- 0x0f,0x22,0x31,0xd5 = mrs x15, trcacvr1
141
- 0x13,0x24,0x31,0xd5 = mrs x19, trcacvr2
142
- 0x08,0x26,0x31,0xd5 = mrs x8, trcacvr3
143
- 0x1c,0x28,0x31,0xd5 = mrs x28, trcacvr4
144
- 0x03,0x2a,0x31,0xd5 = mrs x3, trcacvr5
145
- 0x19,0x2c,0x31,0xd5 = mrs x25, trcacvr6
146
- 0x18,0x2e,0x31,0xd5 = mrs x24, trcacvr7
147
- 0x26,0x20,0x31,0xd5 = mrs x6, trcacvr8
148
- 0x23,0x22,0x31,0xd5 = mrs x3, trcacvr9
149
- 0x38,0x24,0x31,0xd5 = mrs x24, trcacvr10
150
- 0x23,0x26,0x31,0xd5 = mrs x3, trcacvr11
151
- 0x2c,0x28,0x31,0xd5 = mrs x12, trcacvr12
152
- 0x29,0x2a,0x31,0xd5 = mrs x9, trcacvr13
153
- 0x2e,0x2c,0x31,0xd5 = mrs x14, trcacvr14
154
- 0x23,0x2e,0x31,0xd5 = mrs x3, trcacvr15
155
- 0x55,0x20,0x31,0xd5 = mrs x21, trcacatr0
156
- 0x5a,0x22,0x31,0xd5 = mrs x26, trcacatr1
157
- 0x48,0x24,0x31,0xd5 = mrs x8, trcacatr2
158
- 0x56,0x26,0x31,0xd5 = mrs x22, trcacatr3
159
- 0x46,0x28,0x31,0xd5 = mrs x6, trcacatr4
160
- 0x5d,0x2a,0x31,0xd5 = mrs x29, trcacatr5
161
- 0x45,0x2c,0x31,0xd5 = mrs x5, trcacatr6
162
- 0x52,0x2e,0x31,0xd5 = mrs x18, trcacatr7
163
- 0x62,0x20,0x31,0xd5 = mrs x2, trcacatr8
164
- 0x73,0x22,0x31,0xd5 = mrs x19, trcacatr9
165
- 0x6d,0x24,0x31,0xd5 = mrs x13, trcacatr10
166
- 0x79,0x26,0x31,0xd5 = mrs x25, trcacatr11
167
- 0x72,0x28,0x31,0xd5 = mrs x18, trcacatr12
168
- 0x7d,0x2a,0x31,0xd5 = mrs x29, trcacatr13
169
- 0x69,0x2c,0x31,0xd5 = mrs x9, trcacatr14
170
- 0x72,0x2e,0x31,0xd5 = mrs x18, trcacatr15
171
- 0x9d,0x20,0x31,0xd5 = mrs x29, trcdvcvr0
172
- 0x8f,0x24,0x31,0xd5 = mrs x15, trcdvcvr1
173
- 0x8f,0x28,0x31,0xd5 = mrs x15, trcdvcvr2
174
- 0x8f,0x2c,0x31,0xd5 = mrs x15, trcdvcvr3
175
- 0xb3,0x20,0x31,0xd5 = mrs x19, trcdvcvr4
176
- 0xb6,0x24,0x31,0xd5 = mrs x22, trcdvcvr5
177
- 0xbb,0x28,0x31,0xd5 = mrs x27, trcdvcvr6
178
- 0xa1,0x2c,0x31,0xd5 = mrs x1, trcdvcvr7
179
- 0xdd,0x20,0x31,0xd5 = mrs x29, trcdvcmr0
180
- 0xc9,0x24,0x31,0xd5 = mrs x9, trcdvcmr1
181
- 0xc1,0x28,0x31,0xd5 = mrs x1, trcdvcmr2
182
- 0xc2,0x2c,0x31,0xd5 = mrs x2, trcdvcmr3
183
- 0xe5,0x20,0x31,0xd5 = mrs x5, trcdvcmr4
184
- 0xf5,0x24,0x31,0xd5 = mrs x21, trcdvcmr5
185
- 0xe5,0x28,0x31,0xd5 = mrs x5, trcdvcmr6
186
- 0xe1,0x2c,0x31,0xd5 = mrs x1, trcdvcmr7
187
- 0x15,0x30,0x31,0xd5 = mrs x21, trccidcvr0
188
- 0x18,0x32,0x31,0xd5 = mrs x24, trccidcvr1
189
- 0x18,0x34,0x31,0xd5 = mrs x24, trccidcvr2
190
- 0x0c,0x36,0x31,0xd5 = mrs x12, trccidcvr3
191
- 0x0a,0x38,0x31,0xd5 = mrs x10, trccidcvr4
192
- 0x09,0x3a,0x31,0xd5 = mrs x9, trccidcvr5
193
- 0x06,0x3c,0x31,0xd5 = mrs x6, trccidcvr6
194
- 0x14,0x3e,0x31,0xd5 = mrs x20, trccidcvr7
195
- 0x34,0x30,0x31,0xd5 = mrs x20, trcvmidcvr0
196
- 0x34,0x32,0x31,0xd5 = mrs x20, trcvmidcvr1
197
- 0x3a,0x34,0x31,0xd5 = mrs x26, trcvmidcvr2
198
- 0x21,0x36,0x31,0xd5 = mrs x1, trcvmidcvr3
199
- 0x2e,0x38,0x31,0xd5 = mrs x14, trcvmidcvr4
200
- 0x3b,0x3a,0x31,0xd5 = mrs x27, trcvmidcvr5
201
- 0x3d,0x3c,0x31,0xd5 = mrs x29, trcvmidcvr6
202
- 0x31,0x3e,0x31,0xd5 = mrs x17, trcvmidcvr7
203
- 0x4a,0x30,0x31,0xd5 = mrs x10, trccidcctlr0
204
- 0x44,0x31,0x31,0xd5 = mrs x4, trccidcctlr1
205
- 0x49,0x32,0x31,0xd5 = mrs x9, trcvmidcctlr0
206
- 0x4b,0x33,0x31,0xd5 = mrs x11, trcvmidcctlr1
207
- 0x96,0x70,0x31,0xd5 = mrs x22, trcitctrl
208
- 0xd7,0x78,0x31,0xd5 = mrs x23, trcclaimset
209
- 0xce,0x79,0x31,0xd5 = mrs x14, trcclaimclr
210
- 0x9c,0x10,0x11,0xd5 = msr trcoslar, x28
211
- 0xce,0x7c,0x11,0xd5 = msr trclar, x14
212
- 0x0a,0x01,0x11,0xd5 = msr trcprgctlr, x10
213
- 0x1b,0x02,0x11,0xd5 = msr trcprocselr, x27
214
- 0x18,0x04,0x11,0xd5 = msr trcconfigr, x24
215
- 0x08,0x06,0x11,0xd5 = msr trcauxctlr, x8
216
- 0x10,0x08,0x11,0xd5 = msr trceventctl0r, x16
217
- 0x1b,0x09,0x11,0xd5 = msr trceventctl1r, x27
218
- 0x1a,0x0b,0x11,0xd5 = msr trcstallctlr, x26
219
- 0x00,0x0c,0x11,0xd5 = msr trctsctlr, x0
220
- 0x0e,0x0d,0x11,0xd5 = msr trcsyncpr, x14
221
- 0x08,0x0e,0x11,0xd5 = msr trcccctlr, x8
222
- 0x06,0x0f,0x11,0xd5 = msr trcbbctlr, x6
223
- 0x37,0x00,0x11,0xd5 = msr trctraceidr, x23
224
- 0x25,0x01,0x11,0xd5 = msr trcqctlr, x5
225
- 0x40,0x00,0x11,0xd5 = msr trcvictlr, x0
226
- 0x40,0x01,0x11,0xd5 = msr trcviiectlr, x0
227
- 0x41,0x02,0x11,0xd5 = msr trcvissctlr, x1
228
- 0x40,0x03,0x11,0xd5 = msr trcvipcssctlr, x0
229
- 0x47,0x08,0x11,0xd5 = msr trcvdctlr, x7
230
- 0x52,0x09,0x11,0xd5 = msr trcvdsacctlr, x18
231
- 0x58,0x0a,0x11,0xd5 = msr trcvdarcctlr, x24
232
- 0x9c,0x00,0x11,0xd5 = msr trcseqevr0, x28
233
- 0x95,0x01,0x11,0xd5 = msr trcseqevr1, x21
234
- 0x90,0x02,0x11,0xd5 = msr trcseqevr2, x16
235
- 0x90,0x06,0x11,0xd5 = msr trcseqrstevr, x16
236
- 0x99,0x07,0x11,0xd5 = msr trcseqstr, x25
237
- 0x9d,0x08,0x11,0xd5 = msr trcextinselr, x29
238
- 0xb4,0x00,0x11,0xd5 = msr trccntrldvr0, x20
239
- 0xb4,0x01,0x11,0xd5 = msr trccntrldvr1, x20
240
- 0xb6,0x02,0x11,0xd5 = msr trccntrldvr2, x22
241
- 0xac,0x03,0x11,0xd5 = msr trccntrldvr3, x12
242
- 0xb4,0x04,0x11,0xd5 = msr trccntctlr0, x20
243
- 0xa4,0x05,0x11,0xd5 = msr trccntctlr1, x4
244
- 0xa8,0x06,0x11,0xd5 = msr trccntctlr2, x8
245
- 0xb0,0x07,0x11,0xd5 = msr trccntctlr3, x16
246
- 0xa5,0x08,0x11,0xd5 = msr trccntvr0, x5
247
- 0xbb,0x09,0x11,0xd5 = msr trccntvr1, x27
248
- 0xb5,0x0a,0x11,0xd5 = msr trccntvr2, x21
249
- 0xa8,0x0b,0x11,0xd5 = msr trccntvr3, x8
250
- 0xe6,0x00,0x11,0xd5 = msr trcimspec0, x6
251
- 0xfb,0x01,0x11,0xd5 = msr trcimspec1, x27
252
- 0xf7,0x02,0x11,0xd5 = msr trcimspec2, x23
253
- 0xef,0x03,0x11,0xd5 = msr trcimspec3, x15
254
- 0xed,0x04,0x11,0xd5 = msr trcimspec4, x13
255
- 0xf9,0x05,0x11,0xd5 = msr trcimspec5, x25
256
- 0xf3,0x06,0x11,0xd5 = msr trcimspec6, x19
257
- 0xfb,0x07,0x11,0xd5 = msr trcimspec7, x27
258
- 0x04,0x12,0x11,0xd5 = msr trcrsctlr2, x4
259
- 0x00,0x13,0x11,0xd5 = msr trcrsctlr3, x0
260
- 0x15,0x14,0x11,0xd5 = msr trcrsctlr4, x21
261
- 0x08,0x15,0x11,0xd5 = msr trcrsctlr5, x8
262
- 0x14,0x16,0x11,0xd5 = msr trcrsctlr6, x20
263
- 0x0b,0x17,0x11,0xd5 = msr trcrsctlr7, x11
264
- 0x12,0x18,0x11,0xd5 = msr trcrsctlr8, x18
265
- 0x18,0x19,0x11,0xd5 = msr trcrsctlr9, x24
266
- 0x0f,0x1a,0x11,0xd5 = msr trcrsctlr10, x15
267
- 0x15,0x1b,0x11,0xd5 = msr trcrsctlr11, x21
268
- 0x04,0x1c,0x11,0xd5 = msr trcrsctlr12, x4
269
- 0x1c,0x1d,0x11,0xd5 = msr trcrsctlr13, x28
270
- 0x03,0x1e,0x11,0xd5 = msr trcrsctlr14, x3
271
- 0x14,0x1f,0x11,0xd5 = msr trcrsctlr15, x20
272
- 0x2c,0x10,0x11,0xd5 = msr trcrsctlr16, x12
273
- 0x31,0x11,0x11,0xd5 = msr trcrsctlr17, x17
274
- 0x2a,0x12,0x11,0xd5 = msr trcrsctlr18, x10
275
- 0x2b,0x13,0x11,0xd5 = msr trcrsctlr19, x11
276
- 0x23,0x14,0x11,0xd5 = msr trcrsctlr20, x3
277
- 0x32,0x15,0x11,0xd5 = msr trcrsctlr21, x18
278
- 0x3a,0x16,0x11,0xd5 = msr trcrsctlr22, x26
279
- 0x25,0x17,0x11,0xd5 = msr trcrsctlr23, x5
280
- 0x39,0x18,0x11,0xd5 = msr trcrsctlr24, x25
281
- 0x25,0x19,0x11,0xd5 = msr trcrsctlr25, x5
282
- 0x24,0x1a,0x11,0xd5 = msr trcrsctlr26, x4
283
- 0x34,0x1b,0x11,0xd5 = msr trcrsctlr27, x20
284
- 0x25,0x1c,0x11,0xd5 = msr trcrsctlr28, x5
285
- 0x2a,0x1d,0x11,0xd5 = msr trcrsctlr29, x10
286
- 0x38,0x1e,0x11,0xd5 = msr trcrsctlr30, x24
287
- 0x34,0x1f,0x11,0xd5 = msr trcrsctlr31, x20
288
- 0x57,0x10,0x11,0xd5 = msr trcssccr0, x23
289
- 0x5b,0x11,0x11,0xd5 = msr trcssccr1, x27
290
- 0x5b,0x12,0x11,0xd5 = msr trcssccr2, x27
291
- 0x46,0x13,0x11,0xd5 = msr trcssccr3, x6
292
- 0x43,0x14,0x11,0xd5 = msr trcssccr4, x3
293
- 0x4c,0x15,0x11,0xd5 = msr trcssccr5, x12
294
- 0x47,0x16,0x11,0xd5 = msr trcssccr6, x7
295
- 0x46,0x17,0x11,0xd5 = msr trcssccr7, x6
296
- 0x54,0x18,0x11,0xd5 = msr trcsscsr0, x20
297
- 0x51,0x19,0x11,0xd5 = msr trcsscsr1, x17
298
- 0x4b,0x1a,0x11,0xd5 = msr trcsscsr2, x11
299
- 0x44,0x1b,0x11,0xd5 = msr trcsscsr3, x4
300
- 0x4e,0x1c,0x11,0xd5 = msr trcsscsr4, x14
301
- 0x56,0x1d,0x11,0xd5 = msr trcsscsr5, x22
302
- 0x43,0x1e,0x11,0xd5 = msr trcsscsr6, x3
303
- 0x4b,0x1f,0x11,0xd5 = msr trcsscsr7, x11
304
- 0x62,0x10,0x11,0xd5 = msr trcsspcicr0, x2
305
- 0x63,0x11,0x11,0xd5 = msr trcsspcicr1, x3
306
- 0x65,0x12,0x11,0xd5 = msr trcsspcicr2, x5
307
- 0x67,0x13,0x11,0xd5 = msr trcsspcicr3, x7
308
- 0x6b,0x14,0x11,0xd5 = msr trcsspcicr4, x11
309
- 0x6d,0x15,0x11,0xd5 = msr trcsspcicr5, x13
310
- 0x71,0x16,0x11,0xd5 = msr trcsspcicr6, x17
311
- 0x77,0x17,0x11,0xd5 = msr trcsspcicr7, x23
312
- 0x83,0x14,0x11,0xd5 = msr trcpdcr, x3
313
- 0x06,0x20,0x11,0xd5 = msr trcacvr0, x6
314
- 0x14,0x22,0x11,0xd5 = msr trcacvr1, x20
315
- 0x19,0x24,0x11,0xd5 = msr trcacvr2, x25
316
- 0x01,0x26,0x11,0xd5 = msr trcacvr3, x1
317
- 0x1c,0x28,0x11,0xd5 = msr trcacvr4, x28
318
- 0x0f,0x2a,0x11,0xd5 = msr trcacvr5, x15
319
- 0x19,0x2c,0x11,0xd5 = msr trcacvr6, x25
320
- 0x0c,0x2e,0x11,0xd5 = msr trcacvr7, x12
321
- 0x25,0x20,0x11,0xd5 = msr trcacvr8, x5
322
- 0x39,0x22,0x11,0xd5 = msr trcacvr9, x25
323
- 0x2d,0x24,0x11,0xd5 = msr trcacvr10, x13
324
- 0x2a,0x26,0x11,0xd5 = msr trcacvr11, x10
325
- 0x33,0x28,0x11,0xd5 = msr trcacvr12, x19
326
- 0x2a,0x2a,0x11,0xd5 = msr trcacvr13, x10
327
- 0x33,0x2c,0x11,0xd5 = msr trcacvr14, x19
328
- 0x22,0x2e,0x11,0xd5 = msr trcacvr15, x2
329
- 0x4f,0x20,0x11,0xd5 = msr trcacatr0, x15
330
- 0x4d,0x22,0x11,0xd5 = msr trcacatr1, x13
331
- 0x48,0x24,0x11,0xd5 = msr trcacatr2, x8
332
- 0x41,0x26,0x11,0xd5 = msr trcacatr3, x1
333
- 0x4b,0x28,0x11,0xd5 = msr trcacatr4, x11
334
- 0x48,0x2a,0x11,0xd5 = msr trcacatr5, x8
335
- 0x58,0x2c,0x11,0xd5 = msr trcacatr6, x24
336
- 0x46,0x2e,0x11,0xd5 = msr trcacatr7, x6
337
- 0x77,0x20,0x11,0xd5 = msr trcacatr8, x23
338
- 0x65,0x22,0x11,0xd5 = msr trcacatr9, x5
339
- 0x6b,0x24,0x11,0xd5 = msr trcacatr10, x11
340
- 0x6b,0x26,0x11,0xd5 = msr trcacatr11, x11
341
- 0x63,0x28,0x11,0xd5 = msr trcacatr12, x3
342
- 0x7c,0x2a,0x11,0xd5 = msr trcacatr13, x28
343
- 0x79,0x2c,0x11,0xd5 = msr trcacatr14, x25
344
- 0x64,0x2e,0x11,0xd5 = msr trcacatr15, x4
345
- 0x86,0x20,0x11,0xd5 = msr trcdvcvr0, x6
346
- 0x83,0x24,0x11,0xd5 = msr trcdvcvr1, x3
347
- 0x85,0x28,0x11,0xd5 = msr trcdvcvr2, x5
348
- 0x8b,0x2c,0x11,0xd5 = msr trcdvcvr3, x11
349
- 0xa9,0x20,0x11,0xd5 = msr trcdvcvr4, x9
350
- 0xae,0x24,0x11,0xd5 = msr trcdvcvr5, x14
351
- 0xaa,0x28,0x11,0xd5 = msr trcdvcvr6, x10
352
- 0xac,0x2c,0x11,0xd5 = msr trcdvcvr7, x12
353
- 0xc8,0x20,0x11,0xd5 = msr trcdvcmr0, x8
354
- 0xc8,0x24,0x11,0xd5 = msr trcdvcmr1, x8
355
- 0xd6,0x28,0x11,0xd5 = msr trcdvcmr2, x22
356
- 0xd6,0x2c,0x11,0xd5 = msr trcdvcmr3, x22
357
- 0xe5,0x20,0x11,0xd5 = msr trcdvcmr4, x5
358
- 0xf0,0x24,0x11,0xd5 = msr trcdvcmr5, x16
359
- 0xfb,0x28,0x11,0xd5 = msr trcdvcmr6, x27
360
- 0xf5,0x2c,0x11,0xd5 = msr trcdvcmr7, x21
361
- 0x08,0x30,0x11,0xd5 = msr trccidcvr0, x8
362
- 0x06,0x32,0x11,0xd5 = msr trccidcvr1, x6
363
- 0x09,0x34,0x11,0xd5 = msr trccidcvr2, x9
364
- 0x08,0x36,0x11,0xd5 = msr trccidcvr3, x8
365
- 0x03,0x38,0x11,0xd5 = msr trccidcvr4, x3
366
- 0x15,0x3a,0x11,0xd5 = msr trccidcvr5, x21
367
- 0x0c,0x3c,0x11,0xd5 = msr trccidcvr6, x12
368
- 0x07,0x3e,0x11,0xd5 = msr trccidcvr7, x7
369
- 0x24,0x30,0x11,0xd5 = msr trcvmidcvr0, x4
370
- 0x23,0x32,0x11,0xd5 = msr trcvmidcvr1, x3
371
- 0x29,0x34,0x11,0xd5 = msr trcvmidcvr2, x9
372
- 0x31,0x36,0x11,0xd5 = msr trcvmidcvr3, x17
373
- 0x2e,0x38,0x11,0xd5 = msr trcvmidcvr4, x14
374
- 0x2c,0x3a,0x11,0xd5 = msr trcvmidcvr5, x12
375
- 0x2a,0x3c,0x11,0xd5 = msr trcvmidcvr6, x10
376
- 0x23,0x3e,0x11,0xd5 = msr trcvmidcvr7, x3
377
- 0x4e,0x30,0x11,0xd5 = msr trccidcctlr0, x14
378
- 0x56,0x31,0x11,0xd5 = msr trccidcctlr1, x22
379
- 0x48,0x32,0x11,0xd5 = msr trcvmidcctlr0, x8
380
- 0x4f,0x33,0x11,0xd5 = msr trcvmidcctlr1, x15
381
- 0x81,0x70,0x11,0xd5 = msr trcitctrl, x1
382
- 0xc7,0x78,0x11,0xd5 = msr trcclaimset, x7
383
- 0xdd,0x79,0x11,0xd5 = msr trcclaimclr, x29