badline 0.12.1 → 0.14.0

data/lib/badline/time_of_day.rb

@@ -1,228 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class TimeOfDay
-    # The TOD pin is fed from the AC supply. A CIA passes its region's
-    # clock and mains frequency, and these are PAL's.
-    CLOCK_HZ = Region::PAL.clock_hz
-    MAINS_HZ = Region::PAL.mains_hz
-
-    FIELDS = %i[tenths seconds minutes hours].freeze
-
-    def initialize(clock_hz: CLOCK_HZ, mains_hz: MAINS_HZ)
-      # The accumulator advances mains_hz per cycle, so a TOD pin pulse has
-      # arrived when it reaches clock_hz. Integer math keeps it exact.
-      @cycles_per_pulse = clock_hz
-      @mains_hz = mains_hz
-      @accumulator = 0
-      @pulses = 0
-      @clock = { tenths: 0x00, seconds: 0x00, minutes: 0x00, hours: 0x01 }
-      @alarm = { tenths: 0x00, seconds: 0x00, minutes: 0x00, hours: 0x00 }
-      @latch = nil
-      @stopped = true
-      @alarm_pending = false
-      self.fifty_hz = false
-    end
-
-    # CRA bit 7 divides the TOD pin by 5 instead of 6. The divider has to
-    # match the pin frequency to keep time, so PAL software selects 50 Hz.
-    def fifty_hz=(enabled)
-      @match = enabled ? 4 : 5
-    end
-
-    # The clock and the alarm, field by field in FIELDS order, the latch,
-    # and the divider's phase.
-    def save_state(out)
-      out.int(@accumulator).int(@pulses).int(@match).boolean(@stopped).boolean(@alarm_pending)
-      FIELDS.each { |field| out.int(@clock[field]).int(@alarm[field]) }
-      out.boolean(!@latch.nil?)
-      FIELDS.each { |field| out.int(@latch[field]) } if @latch
-    end
-
-    def load_state(input)
-      @accumulator = input.int
-      @pulses = input.int
-      @match = input.int
-      @stopped = input.boolean?
-      @alarm_pending = input.boolean?
-      FIELDS.each do |field|
-        @clock[field] = input.int
-        @alarm[field] = input.int
-      end
-      @latch = input.boolean? ? FIELDS.to_h { |field| [field, input.int] } : nil
-    end
-
-    # Whether the clock is stopped, or gets no pulses on its pin, with no
-    # alarm to raise, so its cycles move only the divider's phase.
-    def quiet? = (@stopped || @mains_hz.zero?) && !@alarm_pending
-
-    # Runs +cycles+ quiet cycles at once.
-    def fast_forward(cycles)
-      @accumulator = (@accumulator + (cycles * @mains_hz)) % @cycles_per_pulse
-    end
-
-    def cycle!
-      @accumulator += @mains_hz
-      pulse! if @accumulator >= @cycles_per_pulse
-      return unless @alarm_pending
-
-      @alarm_pending = false
-      yield if block_given?
-    end
-
-    def tenths
-      value = (@latch || @clock)[:tenths]
-      @latch = nil
-      value
-    end
-
-    def seconds = (@latch || @clock)[:seconds]
-    def minutes = (@latch || @clock)[:minutes]
-
-    def hours
-      @latch ||= @clock.dup
-      @latch[:hours]
-    end
-
-    attr_reader :pulses
-
-    # The clock as a read of the tenths would see it: the latch while the
-    # clock is latched. In FIELDS order.
-    def latched_fields = FIELDS.map { |field| (@latch || @clock)[field] }
-
-    # The cycles until the clock next steps a tenth, as VICE counts them.
-    def cycles_to_tenth
-      to_pulse = (@cycles_per_pulse - @accumulator + @mains_hz - 1) / @mains_hz
-      to_pulse + ([@match - @pulses, 0].max * @cycles_per_pulse / @mains_hz)
-    end
-
-    # Sets the clock, the alarm and the latch from VICE's fields, in FIELDS
-    # order, the latch nil while unlatched.
-    def restore_fields(clock, alarm, latch)
-      FIELDS.each_with_index do |field, i|
-        @clock[field] = clock[i]
-        @alarm[field] = alarm[i]
-      end
-      @latch = latch && FIELDS.each_with_index.to_h { |field, i| [field, latch[i]] }
-    end
-
-    # Sets whether the clock is stopped, the pulses counted towards the
-    # next tenth and the cycles until it, placing the divider so the tenth
-    # lands then.
-    def restore_divider(stopped, pulses, cycles_to_tenth)
-      @stopped = stopped
-      @pulses = pulses
-      to_pulse = cycles_to_tenth - ([@match - pulses, 0].max * @cycles_per_pulse / @mains_hz)
-      @accumulator = (@cycles_per_pulse - (to_pulse * @mains_hz)).clamp(0, @cycles_per_pulse - 1)
-    end
-
-    # The clock and alarm as stored, read without latching the clock.
-    def registers
-      [@clock[:tenths], @clock[:seconds], @clock[:minutes], @clock[:hours],
-       @alarm[:tenths], @alarm[:seconds], @alarm[:minutes], @alarm[:hours],
-       @stopped ? 1 : 0, @latch ? 1 : 0]
-    end
-
-    def write(field, value, alarm:)
-      # The frequency counter is held clear while the clock is stopped, and
-      # starts counting again from the write to tenths that restarts it.
-      if field == :tenths && !alarm && @stopped
-        @pulses = 0
-        @stopped = false
-      end
-      store(field, value & (field == :tenths ? 0x0f : 0x7f), alarm: alarm)
-    end
-
-    # 12-hour BCD value, bit 7 is the AM/PM flag.
-    def write_hours(value, alarm:)
-      value &= 0x9f
-      # Writing 12 to the hour register flips the AM/PM bit, the same way a
-      # carry into 12 does. Writing the alarm hours does not.
-      value ^= 0x80 if !alarm && (value & 0x1f) == 0x12
-      # Halt the clock when writing hours, so that it doesn't
-      # advance mid-update.
-      @stopped = true unless alarm
-      store(:hours, value, alarm: alarm)
-    end
-
-    private
-
-    def store(field, value, alarm:)
-      target = alarm ? @alarm : @clock
-      return if target[field] == value
-
-      target[field] = value
-      @alarm_pending = true if alarm?
-    end
-
-    def pulse!
-      @accumulator -= @cycles_per_pulse
-      return if @stopped
-
-      # A three-bit ring counter with six states, compared against the
-      # divider on each pin pulse rather than on its way past it.
-      if @pulses == @match
-        @pulses = 0
-        advance
-      else
-        @pulses += 1
-        @pulses = 0 if @pulses > 5
-      end
-    end
-
-    def advance
-      tenths = (@clock[:tenths] + 1) & 0x0f
-      @clock[:tenths] = tenths == 10 ? 0 : tenths
-      carry_seconds if tenths == 10
-      @alarm_pending = true if alarm?
-    end
-
-    def carry_seconds
-      return unless advance_pair(:seconds)
-      return unless advance_pair(:minutes)
-
-      advance_hours
-    end
-
-    # Seconds and minutes hold a four-bit low digit that carries at ten into
-    # a three-bit high digit that carries out at six. Both are plain binary
-    # counters, so out-of-range BCD counts up from where it was written.
-    def advance_pair(field)
-      low = ((@clock[field] & 0x0f) + 1) & 0x0f
-      high = (@clock[field] >> 4) & 0x07
-      carry = false
-
-      if low == 10
-        low = 0
-        high = (high + 1) & 0x07
-        if high == 6
-          high = 0
-          carry = true
-        end
-      end
-
-      @clock[field] = (high << 4) | low
-      carry
-    end
-
-    # The hour runs 9 -> 10 and 12 -> 1 by swapping its two digits, and the
-    # AM/PM bit flips as it passes through 12.
-    def advance_hours
-      pm = @clock[:hours] & 0x80
-      high = (@clock[:hours] >> 4) & 0x01
-      low = @clock[:hours] & 0x0f
-
-      if (high == 1 && low == 2) || (high.zero? && low == 9)
-        low = high
-        high ^= 1
-      else
-        low = (low + 1) & 0x0f
-        pm ^= 0x80 if high == 1 && low == 2
-      end
-
-      @clock[:hours] = pm | (high << 4) | low
-    end
-
-    def alarm? = @clock == @alarm
-  end
-end

data/lib/badline/traps.rb

@@ -1,19 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Traps
-    def install_trap(addr, &handler)
-      (@traps ||= {})[addr] = handler
-    end
-
-    def remove_trap(addr)
-      @traps&.delete(addr)
-    end
-
-    private
-
-    def run_traps
-      @traps[@program_counter]&.call if @traps
-    end
-  end
-end

data/lib/badline/via/control_lines.rb

@@ -1,122 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIA
-    # One port's pair of control lines, CA1 and CA2 or CB1 and CB2, set up
-    # by a nibble of the peripheral control register, and their two
-    # interrupt flags. Bit 0 picks the active edge of C1, rising when set.
-    # Bits 3-1 pick the C2 mode:
-    #
-    #   000 input, falling edge    100 handshake output
-    #   001 independent, falling   101 pulse output
-    #   010 input, rising edge     110 low output
-    #   011 independent, rising    111 high output
-    #
-    # A port access clears both flags, but an independent input keeps C2's.
-    # In handshake mode C2 goes low on a port access and back high on the
-    # next active C1 edge. In pulse mode it goes low for the cycle after the
-    # access. Port A handshakes on reads and writes, port B on writes only.
-    class ControlLines
-      attr_reader :control, :c1_high, :c2_high
-
-      # The level driven on C2, high while it is an input.
-      attr_reader :c2_output
-
-      def initialize(interrupts, c1_flag:, c2_flag:, handshake_on_read:)
-        @interrupts = interrupts
-        @c1_flag = c1_flag
-        @c2_flag = c2_flag
-        @handshake_on_read = handshake_on_read
-        @c1_high = @c2_high = true
-        reset!
-      end
-
-      # Back to input mode with both handshake outputs released. The input
-      # levels carry over.
-      def reset!
-        @control = 0
-        @handshake_low = false
-        @pulse = 0
-        drive
-      end
-
-      def control=(nibble)
-        @control = nibble & 0x0f
-        drive
-      end
-
-      # Only the pulse output needs the clock.
-      def pulsing? = @pulse.positive?
-
-      def cycle!
-        @pulse -= 1
-        drive if @pulse.zero?
-      end
-
-      def active_c1_edge?(high) = high == @control.anybits?(0x01)
-
-      # The lines' levels and mode. Which flags they set, and whether reads
-      # handshake, are the port's wiring.
-      def save_state(out)
-        out.int(@control).boolean(@c1_high).boolean(@c2_high).boolean(@handshake_low).int(@pulse).boolean(@c2_output)
-      end
-
-      def load_state(input)
-        @control = input.int
-        @c1_high = input.boolean?
-        @c2_high = input.boolean?
-        @handshake_low = input.boolean?
-        @pulse = input.int
-        @c2_output = input.boolean?
-      end
-
-      # Everything the lines hold, for comparing them at two points.
-      def state = [@control, @c1_high, @c2_high, @handshake_low, @pulse, @c2_output]
-
-      # A new C1 level. An active edge sets the flag and ends a handshake.
-      def c1=(high)
-        return if high == @c1_high
-
-        @c1_high = high
-        return unless active_c1_edge?(high)
-
-        @handshake_low = false
-        drive
-        @interrupts.set(@c1_flag)
-      end
-
-      # A new C2 level. An active edge sets the flag while C2 is an input.
-      def c2=(high)
-        return if high == @c2_high
-
-        @c2_high = high
-        @interrupts.set(@c2_flag) if @control.nobits?(0x08) && high == @control.anybits?(0x04)
-      end
-
-      # A read or write of the handshaking port register.
-      def access!(write)
-        @interrupts.clear(independent? ? @c1_flag : @c1_flag | @c2_flag)
-        return unless write || @handshake_on_read
-
-        case @control >> 1
-        when 4 then @handshake_low = true
-        when 5 then @pulse = 2
-        end
-        drive
-      end
-
-      private
-
-      def independent? = @control & 0x0a == 0x02
-
-      def drive
-        @c2_output = case @control >> 1
-                     when 4 then !@handshake_low
-                     when 5 then @pulse.zero?
-                     when 6 then false
-                     else true
-                     end
-      end
-    end
-  end
-end

data/lib/badline/via/fast_forward.rb

@@ -1,53 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIA
-    # Running a VIA a stretch of cycles at once while nothing but its
-    # counters would change, for Drive::Idle.
-    module FastForward
-      # quiet_cycles for a VIA that will never set a flag of its own.
-      QUIET = 1 << 40
-
-      # How many cycles the VIA can run with nothing but its counters
-      # changing: no flag set, no pulse on a control line and no bit
-      # shifted. See Drive::Idle.
-      def quiet_cycles
-        return 0 if @sr_uses_t2 || @shift_register.clocking? || @ca.pulsing? || @cb.pulsing?
-
-        [@t1.quiet_cycles, @t2.quiet_cycles].min
-      end
-
-      # Runs +cycles+ cycles at once, as many as quiet_cycles allows, which
-      # moves only the counters.
-      def fast_forward(cycles)
-        return if cycles.zero?
-
-        @t1.fast_forward(cycles)
-        @t2.fast_forward(cycles)
-      end
-
-      # The counters an orbit (see Drive::Idle) has to bring back: those
-      # of the armed timers, and of the timers +touched+ names (bit 0 for
-      # timer 1, bit 1 for timer 2). The others only count.
-      def counter_state(touched)
-        [(@t1.count_state if @t1.armed? || touched.anybits?(1)),
-         (@t2.count_state if @t2.armed? || touched.anybits?(2))]
-      end
-
-      # Runs +cycles+ cycles of whole orbits at once: the counters
-      # counter_state leaves out move on, and the rest come back round.
-      def skip_orbits(cycles, touched)
-        @t1.fast_forward(cycles) unless @t1.armed? || touched.anybits?(1)
-        @t2.fast_forward(cycles) unless @t2.armed? || touched.anybits?(2)
-      end
-
-      # Everything the VIA holds but its counters, for comparing it at two
-      # points. Timer 1's PB7 level counts only while ACR bit 7 puts it on
-      # the pin: nothing reads it otherwise.
-      def idle_state
-        [@ora, @orb, @ddra, @ddrb, @latch_a, @latch_b, @acr, @pcr, @pb6_high, @ifr.flags, @ifr.enable,
-         @acr.anybits?(0x80) && @t1.pb7, *@t1.state, *@t2.state, *@ca.state, *@cb.state, *@shift_register.state]
-      end
-    end
-  end
-end

data/lib/badline/via/interrupt_register.rb

@@ -1,67 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIA
-    # The interrupt flag and enable registers. Each source has a flag bit,
-    # and IRQ is pulled low while any flag is set with its enable bit.
-    class InterruptRegister
-      CA2 = 0x01
-      CA1 = 0x02
-      SR = 0x04
-      CB2 = 0x08
-      CB1 = 0x10
-      TIMER2 = 0x20
-      TIMER1 = 0x40
-
-      attr_reader :flags, :enable
-
-      def initialize
-        reset!
-      end
-
-      def reset!
-        @flags = 0x00
-        @enable = 0x00
-      end
-
-      def save_state(out)
-        out.int(@flags).int(@enable)
-      end
-
-      def load_state(input)
-        @flags = input.int
-        @enable = input.int
-      end
-
-      def set(bits)
-        @flags |= bits
-      end
-
-      def clear(bits)
-        @flags &= ~bits
-      end
-
-      def irq? = @flags.anybits?(@enable)
-
-      # Bit 7 reads the IRQ output.
-      def read = irq? ? @flags | 0x80 : @flags
-
-      # Writing 1s clears the flags; bit 7 is ignored.
-      def write(value)
-        clear(value & 0x7f)
-      end
-
-      # Bit 7 reads as 1.
-      def read_enable = @enable | 0x80
-
-      # Bit 7 picks between setting and clearing the enable bits given.
-      def write_enable(value)
-        if value.anybits?(0x80)
-          @enable |= value & 0x7f
-        else
-          @enable &= ~value & 0x7f
-        end
-      end
-    end
-  end
-end

data/lib/badline/via/shift_register.rb

@@ -1,180 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class VIA
-    # The 6522's shift register, with the CB1 clock and CB2 data lines it
-    # takes over in every mode but the first.
-    #
-    # ACR bits 4-2 pick the mode. Modes 1 to 3 shift in, left, with the new
-    # bit taken from CB2 into bit 0 on each rising CB1 edge. Modes 4 to 7
-    # shift out: each falling CB1 edge puts bit 7 on CB2 and rotates it back
-    # round into bit 0, so after eight bits the byte is back where it
-    # started. Modes 1, 4 and 5 clock off timer 2, modes 2 and 6 off φ2, and
-    # modes 3 and 7 off whatever drives CB1 from outside.
-    #
-    # Under its own clock the register drives CB1, idling high. Reading or
-    # writing the data register starts a byte, but only while the register
-    # is idle and enabled: an access in mode 0, or one before the eighth bit
-    # is in, leaves the count alone. CB1 falls on the first clock tick of
-    # the byte and rises on the second, and so on, so a byte is eight pulses
-    # over sixteen ticks. The interrupt flag is set on the tick that raises
-    # CB1 over the eighth bit, and CB1 then stays high until the next
-    # access.
-    #
-    # In modes 2 and 6 a tick is a φ2 cycle, from the second cycle after
-    # the access on, which makes a byte sixteen cycles. In modes 1, 4 and 5
-    # it comes two cycles after each timer 2 low byte underflow, on the
-    # cycle after the low byte reloads, which makes a byte sixteen
-    # underflows. Mode 4 never stops and never interrupts: its counter is
-    # disabled, and the byte goes round and round.
-    #
-    # Under an external clock the register shifts on every CB1 edge, access
-    # or not. The access only arms the counter: the flag is set on the eighth
-    # rising edge after it, and the counter then waits for the next access.
-    class ShiftRegister
-      DISABLED = 0
-      IN_T2 = 1
-      IN_PHI2 = 2
-      IN_EXTERNAL = 3
-      OUT_FREE_RUNNING = 4
-      OUT_T2 = 5
-      OUT_PHI2 = 6
-      OUT_EXTERNAL = 7
-
-      attr_reader :mode, :data
-      attr_accessor :cb2_input
-
-      def initialize
-        @mode = DISABLED
-        @data = 0x00
-        # Bits still to count before the flag, zero when the counter is idle.
-        @bits = 0
-        # The clock's last two cycles, newest in bit 0: timer 2 low byte
-        # underflows in modes 1, 4 and 5, and whether the byte has started
-        # in modes 2 and 6.
-        @delay = 0
-        @clock = true
-        @cb2 = true
-        # Nothing drives CB2 from outside, so it floats high.
-        @cb2_input = true
-      end
-
-      def mode=(value)
-        @mode = value & 0x07
-      end
-
-      def data=(value)
-        @data = value & 0xff
-      end
-
-      # A read or write of the data register, which starts a byte if the
-      # register is idle and enabled.
-      def access!
-        return if @mode == DISABLED || @bits.nonzero?
-
-        @bits = 8
-        @delay = 0 if @mode == IN_PHI2 || @mode == OUT_PHI2
-      end
-
-      # Whether the register is counting bits off its own clock, which
-      # changes it from cycle to cycle.
-      def clocking? = @bits.nonzero? && internal_clock?
-
-      def save_state(out)
-        out.int(@mode).int(@data).int(@bits).int(@delay).boolean(@clock).boolean(@cb2).boolean(@cb2_input)
-      end
-
-      def load_state(input)
-        @mode = input.int
-        @data = input.int
-        @bits = input.int
-        @delay = input.schema > 4 ? input.int : 0
-        @clock = input.boolean?
-        @cb2 = input.boolean?
-        @cb2_input = input.boolean?
-      end
-
-      # Everything the register holds, for comparing it at two points.
-      def state = [@mode, @data, @bits, @delay, @clock, @cb2, @cb2_input]
-
-      # The CB1 level the register drives, or nil when CB1 is an input.
-      def cb1_output
-        internal_clock? ? @clock : nil
-      end
-
-      # The CB2 level the register drives, or nil when it doesn't.
-      def cb2_output
-        @mode >= OUT_FREE_RUNNING ? @cb2 : nil
-      end
-
-      # Clocked once per φ2 cycle, with whether timer 2's low byte underflowed
-      # on it. Returns true on the cycle that sets the interrupt flag.
-      def cycle!(t2_low_underflow)
-        case @mode
-        when IN_PHI2, OUT_PHI2 then @bits.nonzero? && phi2_tick
-        when IN_T2, OUT_T2, OUT_FREE_RUNNING then t2_tick(t2_low_underflow)
-        else false
-        end
-      end
-
-      # A level change on CB1 from outside. Only the external clock modes
-      # listen: shifting in samples CB2 as CB1 rises, and shifting out puts
-      # the next bit on CB2 as it falls. Returns true when the edge sets the
-      # interrupt flag.
-      def cb1_edge!(rising)
-        return false unless @mode == IN_EXTERNAL || @mode == OUT_EXTERNAL
-
-        shift_in if rising && @mode == IN_EXTERNAL
-        shift_out if !rising && @mode == OUT_EXTERNAL
-        rising && eighth_bit?
-      end
-
-      private
-
-      def internal_clock?
-        @mode != DISABLED && @mode != IN_EXTERNAL && @mode != OUT_EXTERNAL
-      end
-
-      # A φ2 cycle of a byte: every one but the first ticks.
-      def phi2_tick
-        started = @delay.nonzero?
-        @delay = 1
-        started && tick
-      end
-
-      # Ticks on the underflow from two cycles back, while a byte is under
-      # way.
-      def t2_tick(underflow)
-        due = @delay.anybits?(2)
-        @delay = ((@delay << 1) & 2) | (underflow ? 1 : 0)
-        due && @bits.nonzero? && tick
-      end
-
-      # One half period of the register's own clock: a falling edge puts a
-      # bit out, and a rising one takes a bit in and counts it.
-      def tick
-        @clock = !@clock
-        shift_out if !@clock && @mode >= OUT_FREE_RUNNING
-        shift_in if @clock && @mode < IN_EXTERNAL
-        @clock && @mode != OUT_FREE_RUNNING && eighth_bit?
-      end
-
-      # Counts a bit, and says whether it was the eighth since the access.
-      def eighth_bit?
-        return false if @bits.zero?
-
-        @bits -= 1
-        @bits.zero?
-      end
-
-      def shift_in
-        @data = ((@data << 1) | (@cb2_input ? 1 : 0)) & 0xff
-      end
-
-      def shift_out
-        @cb2 = @data.anybits?(0x80)
-        @data = ((@data << 1) | (@cb2 ? 1 : 0)) & 0xff
-      end
-    end
-  end
-end