badline 0.12.1 → 0.14.0

data/lib/badline/c128.rb

@@ -2,23 +2,25 @@
 
 require "badline/c128/model"
 require "badline/c128/mmu"
-require "badline/c128/vdc"
+require "badline/chips/vdc"
 require "badline/c128/mmu_pages"
 require "badline/c128/io_pages"
 require "badline/c128/z80_pages"
 require "badline/c128/color_lines"
 require "badline/c128/banks"
-require "badline/c128/bus_state"
+require "badline/c128/bus/keyed_state"
 require "badline/c128/bus"
 require "badline/c128/cpu"
 require "badline/c128/z80"
 require "badline/c128/z80_turns"
-require "badline/c128/saved_state"
+require "badline/snapshot/c128_setup"
+require "badline/c128/keyed_state"
+require "badline/c128/keyed_modules"
 require "badline/c128/keys"
 require "badline/c128/modes"
 require "badline/c128/drives"
 require "badline/c128/fast_serial"
-require "badline/drive1571"
+require "badline/drives/model1571"
 
 module Badline
   # The Commodore 128: the 8502 on the VIC-IIe's clock, two CIAs, the SID,
@@ -43,11 +45,12 @@ module Badline
   # mirrors, and $D500-$D7FF holds the hidden MMU, the VDC and open bus.
   class C128
     include IntegerHelper
-    include KeyboardBuffer
+    include Machine::KeyboardBuffer
     include Machine::Clocking
-    include Computer::Common
-    include Computer::Attachments
-    include Computer::KernalTraps
+    include Machine::Settling
+    include C64::Common
+    include C64::Attachments
+    include C64::KernalTraps
     include Keys
     include Modes
     include Drives
@@ -56,7 +59,7 @@ module Badline
 
     # The C64's 8x8 matrix and the three rows K0-K2 select, in port B
     # column order.
-    KEYBOARD_MATRIX = (Keyboard::C64_MATRIX + [
+    KEYBOARD_MATRIX = (Input::Keyboard::C64_MATRIX + [
       %i[help keypad8 keypad5 tab keypad2 keypad4 keypad7 keypad1],
       %i[esc keypad_plus keypad_minus line_feed keypad_enter keypad6 keypad9 keypad3],
       %i[alt keypad0 keypad_period crsr_up crsr_down crsr_left crsr_right no_scroll]
@@ -67,10 +70,6 @@ module Badline
     # BASIC 7.0's, which is READY by then.
     C128_INIT_THRESHOLD = 2_000_000
 
-    # The C128 KERNAL's keyboard buffer and its count.
-    C128_KEYBOARD_BUFFER = 0x034a
-    C128_KEYBOARD_COUNT = 0xd0
-
     attr_reader :cpu, :cycles, :drive1541, :model, :init_threshold
 
     def family = :c128
@@ -93,6 +92,11 @@ module Badline
 
     def ram = @bus.ram
 
+    # Reads and writes memory as the CPU sees it, through the bus.
+    def peek(addr) = @bus.peek(addr)
+
+    def poke(addr, value) = @bus.poke(addr, value)
+
     def keyboard = @bus.keyboard
 
     def joystick1 = @bus.joystick1
@@ -116,7 +120,7 @@ module Badline
 
       @model = Model.named(model)
       @c64_built = mode == :c64
-      @init_threshold = @c64_built ? Computer::INIT_THRESHOLD : C128_INIT_THRESHOLD
+      @init_threshold = @c64_built ? C64::INIT_THRESHOLD : C128_INIT_THRESHOLD
       @holding_commodore = false
       @bus = Bus.new(@model, sid_model: sid_model || @model.sid_model, mode:)
       @cpu = CPU.new(@bus, debug:)
@@ -135,6 +139,7 @@ module Badline
       @restore_pulse = false
       @init_handlers = []
       @pending_keys = nil
+      @typist = Input::MatrixTypist.new(@bus.keyboard)
       @capture_output = nil
       init_drives
       enter_c64_mode if @c64_built
@@ -149,7 +154,7 @@ module Badline
       return z80_cycle! if @z80_turn
 
       handle_init if @cycles == @init_threshold
-      feed_keyboard if @pending_keys
+      type_pending if @pending_keys
 
       clock_bits = @clock_bits
       @clock_bits = @vic.clock_bits
@@ -209,7 +214,7 @@ module Badline
       @cia2.reset!
       @sid.reset!
       @bus.cartridge&.reset
-      @drive&.reset!
+      @dos&.reset!
       @drive1541&.reset!
       @drive1571&.reset!
       @drive1581&.reset!

data/lib/badline/c64/attachments.rb

@@ -0,0 +1,42 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    # What plugs into the machine besides its chips, the cartridge, its
+    # true drives (TrueDrives) and an REU, and their state for a snapshot.
+    # The disk device 8 serves through the traps is KernalTraps'.
+    module Attachments
+      include TrueDrives
+
+      # Puts the cartridge in the expansion port and wires its clock and NMI
+      # line to the machine, leaving the machine's state as it is. A
+      # restored snapshot's cartridge comes back through here.
+      def connect_cartridge(cartridge)
+        cartridge.clock = -> { @cycles }
+        cartridge.on_nmi_change { |level| @cartridge_nmi = level }
+        address_bus.attach_cartridge(cartridge)
+      end
+
+      # The serial bus, which CIA 2's port A drives through the C64's own
+      # inverters and reads back on PA6 and PA7, with or without a drive on
+      # it.
+      attr_reader :iec_bus
+
+      private
+
+      # CIA 2's port A drives the serial bus, which reads CLK and DATA back
+      # into it.
+      def plug_serial_bus
+        @iec_bus = Drives::SerialBus.new
+        @cia2.peripheral = @iec_bus
+        @cia2.on_port_a_write { push_serial_lines }
+        push_serial_lines
+      end
+
+      # Pushes the lines CIA 2's port A pulls into the serial bus.
+      def push_serial_lines
+        @iec_bus.host_lines = @cia2.port_a_lines
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram/banking.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The register and page mapping the expansions share. #map lays the
+      # selected banks out in the address bus's page tables, and #map_io puts
+      # the register over the VIC's I/O page at $D100.
+      module Banking
+        attr_reader :low_ram, :high_ram, :video_ram
+
+        # The block runs whenever the register moves a bank.
+        def on_change(&block)
+          @on_change = block
+        end
+
+        def peek(_addr) = 0xff
+
+        def map(read_pages, write_pages)
+          [read_pages, write_pages].each do |pages|
+            pages.fill(@low_ram, 0x00, 0x10)
+            pages.fill(@high_ram, 0x10, 0xf0)
+          end
+        end
+
+        def map_io(read_pages, write_pages)
+          read_pages[0xd1] = write_pages[0xd1] = self
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram/plus256k.rb

@@ -0,0 +1,64 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The +256K: four 64K banks, the first of them the machine's own RAM.
+      # $D100 picks one for $0000-$0FFF (bits 0-1), one for the VIC (bits 2-3)
+      # and one for $1000-$FFFF (bits 6-7). Setting bit 4 locks the register
+      # until the next reset.
+      class Plus256k
+        include Banking
+
+        def initialize(ram)
+          @banks = [ram, Memory.new, Memory.new, Memory.new]
+          @on_change = nil
+          reset!
+        end
+
+        def poke(_addr, value)
+          return if @locked
+
+          @low_ram = @banks[value & 0b11]
+          @video_ram = @banks[(value >> 2) & 0b11]
+          @high_ram = @banks[value >> 6]
+          @locked = value.anybits?(0x10)
+          @on_change&.call
+        end
+
+        def reset!
+          @low_ram = @video_ram = @high_ram = @banks[0]
+          @locked = false
+        end
+
+        def type = :plus256k
+
+        # $D100 as the banks it picks give it, whether it is locked, and
+        # banks 1 to 3, in a keyed snapshot module.
+        def save_fields(out)
+          low = @banks.index(@low_ram).to_i
+          video = @banks.index(@video_ram).to_i
+          out.int("d100", low | (video << 2) | (@banks.index(@high_ram).to_i << 6)).bool("locked", @locked)
+          @banks[1].save_fields(out, "bank1")
+          @banks[2].save_fields(out, "bank2")
+          @banks[3].save_fields(out, "bank3")
+        end
+
+        def load_fields(input)
+          value = input.byte("d100", 0)
+          @low_ram = @banks[value & 0b11]
+          @video_ram = @banks[(value >> 2) & 0b11]
+          @high_ram = @banks[value >> 6]
+          @locked = input.bool("locked", @locked)
+          @banks[1].load_fields(input, "bank1")
+          @banks[2].load_fields(input, "bank2")
+          @banks[3].load_fields(input, "bank3")
+        end
+
+        def power_on!
+          @banks.drop(1).each(&:clear!)
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram/plus60k.rb

@@ -0,0 +1,47 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The +60K: a second bank of RAM behind $1000-$FFFF, selected by bit 7
+      # of $D100. $0000-$0FFF stays the machine's own RAM, and so does all of
+      # what the VIC sees.
+      class Plus60k
+        include Banking
+
+        def initialize(ram)
+          @low_ram = @video_ram = @high_ram = ram
+          @banks = [ram, Memory.new]
+          @on_change = nil
+        end
+
+        def poke(_addr, value)
+          @high_ram = @banks[value >> 7]
+          @on_change&.call
+        end
+
+        def reset!
+          @high_ram = @banks[0]
+        end
+
+        def type = :plus60k
+
+        # $D100 as bit 7 picks the bank above $1000, and bank 1, in a
+        # keyed snapshot module.
+        def save_fields(out)
+          out.int("d100", @banks.index(@high_ram).to_i << 7)
+          @banks[1].save_fields(out, "bank1")
+        end
+
+        def load_fields(input)
+          @high_ram = @banks[(input.byte("d100", @banks.index(@high_ram).to_i << 7) >> 7) & 1]
+          @banks[1].load_fields(input, "bank1")
+        end
+
+        def power_on!
+          @banks[1].clear!
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram/unexpanded.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    module BankedRAM
+      # The machine with no expansion fitted: its own RAM everywhere, and
+      # $D100 left to the VIC.
+      class Unexpanded
+        include Banking
+
+        def initialize(ram)
+          @low_ram = @video_ram = @high_ram = ram
+          @on_change = nil
+        end
+
+        def type = nil
+
+        def map_io(_read_pages, _write_pages); end
+
+        def save_fields(_out); end
+
+        def load_fields(_input); end
+
+        def reset!; end
+
+        def power_on!; end
+      end
+    end
+  end
+end

data/lib/badline/c64/banked_ram.rb

@@ -0,0 +1,23 @@
+# frozen_string_literal: true
+
+require "badline/c64/banked_ram/banking"
+require "badline/c64/banked_ram/unexpanded"
+require "badline/c64/banked_ram/plus60k"
+require "badline/c64/banked_ram/plus256k"
+
+module Badline
+  class C64
+    # RAM expansions that bank extra memory in under the CPU through a
+    # register at $D100, in the VIC's I/O page. Any write to $D100-$D1FF
+    # sets the register, which reads back as $FF.
+    module BankedRAM
+      TYPES = { plus60k: Plus60k, plus256k: Plus256k }.freeze
+
+      def self.build(type, ram, &)
+        expansion = type ? TYPES.fetch(type).new(ram) : Unexpanded.new(ram)
+        expansion.on_change(&)
+        expansion
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/debug_register.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The VICE debug cartridge register, mapped at $D7FF on the C64. It is a
+      # VICE facility rather than real hardware, enabled there with -debugcart:
+      # writing a byte ends the run with that value as the exit code. The VICE
+      # test suites write $00 for success and $ff for failure.
+      #
+      # Wraps the SID's top mirror page, so every other access falls through.
+      class DebugRegister
+        ADDRESS = 0xd7ff
+
+        def initialize(sid, &handler)
+          @sid = sid
+          @handler = handler
+        end
+
+        def peek(addr)
+          @sid.peek(addr)
+        end
+
+        def poke(addr, value)
+          return @handler.call(value) if addr == ADDRESS
+
+          @sid.poke(addr, value)
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/extra_sids.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The second and third SIDs the SID player fits for a tune written for
+      # them, each over its 32 bytes of the I/O area (SIDSlots). The SID
+      # player's machine has nothing else in I/O 1 and 2, so the rest of a
+      # page there reads the open bus.
+      module ExtraSIDs
+        # Fits a SID at the address it was built at, where it takes its 32
+        # bytes over from whatever maps there.
+        def add_sid(sid)
+          page = sid.start >> 8
+          slots = @sid_slots.find { |candidate| candidate.page == page }
+          if slots.nil?
+            slots = SIDSlots.new(page, @sid, @open_bus)
+            @sid_slots << slots
+          end
+          slots.place(sid)
+          update_overlays!
+        end
+
+        private
+
+        def map_extra_sids
+          @sid_slots.each { |slots| @read_pages[slots.page] = @write_pages[slots.page] = slots }
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/fittings.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # What a model fits around the chips: its KERNAL, a datasette or none,
+      # and the board and case they sit in.
+      module Fittings
+        # The keywords #fit takes.
+        NAMES = %i[kernal datasette board].freeze
+
+        # The C64's board and case, the PET 64's, whose built-in monitor
+        # shows the VIC's output in shades of green, the C64GS's, which has
+        # no keyboard, or the MAX Machine's (:max): 2K of RAM, no ROMs, CIA 1
+        # alone at $DC00-$DFFF and the cartridge port in Ultimax mode.
+        BOARDS = %i[c64 pet64 gs max].freeze
+
+        attr_reader :board
+
+        # Fits the KERNAL ROM ROMs::KERNALS names, leaves the cassette port
+        # empty unless `datasette`, and puts the chips in the board BOARDS
+        # names.
+        def fit(kernal: :c64, datasette: true, board: :c64)
+          self.kernal = kernal unless kernal == :c64
+          @datasette.disconnect! unless datasette
+          self.board = board unless board == :c64
+        end
+
+        def board=(name)
+          raise ArgumentError, "no board named #{name}" unless BOARDS.include?(name)
+
+          @board = name
+          vic.palette = name == :pet64 ? Chips::VIC::GREEN_PALETTE : Chips::VIC::PALETTE
+          keyboard.connected = name != :gs
+          update_overlays!
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/keyed_state.rb

@@ -0,0 +1,41 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The 6510's port under port.* in a keyed snapshot module
+      # (Snapshot::Keyed, BL-CPU), and the bus once its memories, the port
+      # and the cartridge are loaded: the banks the CPU and the VIC see are
+      # worked out again.
+      module KeyedState
+        # The RAM expansion fitted, or an Unexpanded stand-in.
+        attr_reader :ram_expansion
+
+        # Takes the cartridge out of the expansion port, as a restore does for
+        # a snapshot without one.
+        def detach_cartridge
+          @cartridge = nil
+          update_overlays!
+        end
+
+        # The 6510 port's direction and output registers, and the charge left
+        # on its floating bits.
+        def port_state = [@cpu_port.ddr, @cpu_port.data, @cpu_port.floating]
+
+        # Sets the port as port_state reads it, as a snapshot restores it,
+        # leaving the RAM under $00 and $01 alone.
+        def restore_port(ddr, out, floating)
+          @cpu_port.restore(ddr, out, floating)
+        end
+
+        def save_port_fields(out) = @cpu_port.save_fields(out, "port.")
+
+        def load_port_fields(input) = @cpu_port.load_fields(input, "port.")
+
+        def restored! = update_overlays!
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/c64/bus/pla.rb

@@ -0,0 +1,149 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The C64's PLA: what each page of the CPU's view maps to, from the
+      # CPU port's LORAM, HIRAM and CHAREN lines and the cartridge's EXROM
+      # and GAME. The bus that includes it supplies the page tables, the
+      # ROMs, the chips, #map_ram_pages, which lays out the RAM that the
+      # ROMs, the cartridge and I/O map over, and #map_io_pages, which lays
+      # out the chips at $D000-$DFFF, with #map_cartridge_io for I/O 1 and 2.
+      module PLA
+        # A chip's registers seen at another page, which reads and writes
+        # them as at the page the chip starts at.
+        class Mirror
+          def initialize(chip, start)
+            @chip = chip
+            @start = start
+          end
+
+          def peek(addr) = @chip.peek(@start | (addr & 0xff))
+          def poke(addr, value) = @chip.poke(@start | (addr & 0xff), value)
+        end
+
+        private
+
+        def map_pla_pages
+          map_ram_pages
+          @ultimax ? map_ultimax_pages : map_banked_pages
+        end
+
+        def map_banked_pages
+          map_rom_overlays
+          map_cartridge_ram
+          @write_pages.fill(@cartridge.romh_writes, 0xe0, 0x20) if @cartridge&.romh_writes
+
+          if io?
+            map_io_pages
+          elsif character?
+            @read_pages.fill(character_rom, 0xd0, 0x10)
+          end
+        end
+
+        # Ultimax mode ignores the $01 lines: 4K of RAM, ROML/ROMH windows,
+        # I/O always visible and open address space everywhere else. The ROML
+        # and ROMH selects fire on writes as well, so cartridge RAM or flash in
+        # either window takes the writes there. The MAX has 2K of RAM, and is
+        # in Ultimax mode with no cartridge too.
+        def map_ultimax_pages
+          first = @board == :max ? 0x08 : 0x10
+          @read_pages.fill(@open_bus, first, 0x100 - first)
+          @write_pages.fill(@open_bus, first, 0x100 - first)
+          map_ultimax_cartridge if @cartridge
+          map_io_pages
+          map_max_io if @board == :max
+        end
+
+        def map_ultimax_cartridge
+          @read_pages.fill(@cartridge.roml, 0x80, 0x20) if @cartridge.roml
+          map_ultimax_writes(@cartridge.roml, 0x80)
+          @read_pages.fill(@cartridge.romh, 0xe0, 0x20) if @cartridge.romh
+          map_ultimax_writes(@cartridge.romh, 0xe0)
+          map_ultimax_a000
+        end
+
+        def map_ultimax_writes(bank, first_page)
+          @write_pages.fill(bank, first_page, 0x20) if bank.respond_to?(:poke)
+        end
+
+        def map_ultimax_a000
+          return unless (window = @cartridge.ultimax_a000)
+
+          @read_pages.fill(window, 0xa0, 0x20)
+          @write_pages.fill(window, 0xa0, 0x20)
+        end
+
+        # The MAX has no CIA 2 and no I/O 2: CIA 1 answers all through
+        # $DC00-$DFFF, but for the I/O 1 page a cartridge takes.
+        def map_max_io
+          @cia1_mirror ||= Mirror.new(cia1, 0xdc00)
+          (0xdd..0xdf).each { |page| @read_pages[page] = @write_pages[page] = @cia1_mirror }
+          return unless @cartridge
+
+          @write_pages[0xde] = @cartridge
+          @read_pages[0xde] = @cartridge if @cartridge.readable_io_pages.include?(0xde)
+        end
+
+        # EXROM and GAME select the cartridge whether or not it has a chip
+        # there, and an empty socket leaves the bus floating.
+        def map_rom_overlays
+          @read_pages.fill(@cartridge.roml || @open_bus, 0x80, 0x20) if roml?
+          if romh?
+            @read_pages.fill(@cartridge.romh || @open_bus, 0xa0, 0x20)
+          elsif basic?
+            @read_pages.fill(basic_rom, 0xa0, 0x20)
+          end
+          @read_pages.fill(kernal_rom, 0xe0, 0x20) if kernal?
+        end
+
+        # Cartridge RAM in the ROML or ROMH window decodes writes itself,
+        # whatever the $01 lines say.
+        def map_cartridge_ram
+          return unless @cartridge&.exrom&.zero?
+
+          map_cartridge_ram_bank(@cartridge.roml, 0x80)
+          map_cartridge_ram_bank(@cartridge.romh, 0xa0) if @cartridge.game.zero?
+        end
+
+        def map_cartridge_ram_bank(bank, first_page)
+          @write_pages.fill(bank, first_page, 0x20) if bank.is_a?(Cartridge::RAMBank)
+        end
+
+        def map_cartridge_io
+          @write_pages.fill(@cartridge, 0xde, 2)
+          @cartridge.readable_io_pages.each { |p| @read_pages[p] = @cartridge }
+        end
+
+        def basic?
+          io_port.kernal? && io_port.basic? && game_high?
+        end
+
+        def game_high?
+          @cartridge.nil? || @cartridge.game == 1
+        end
+
+        def roml?
+          @cartridge&.exrom&.zero? && io_port.kernal? && io_port.basic?
+        end
+
+        def romh?
+          @cartridge&.exrom&.zero? && @cartridge.game.zero? && io_port.kernal?
+        end
+
+        # In 16K mode LORAM alone leaves $d000 as RAM, where it still maps I/O.
+        def character?
+          (io_port.kernal? || (io_port.basic? && game_high?)) && !io_port.io?
+        end
+
+        def io?
+          (io_port.basic? || io_port.kernal?) && io_port.io?
+        end
+
+        def kernal?
+          io_port.kernal?
+        end
+      end
+    end
+  end
+end

data/lib/badline/c64/bus/roms.rb

@@ -0,0 +1,41 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    class Bus
+      # The BASIC, character and KERNAL ROMs, and which KERNAL is fitted.
+      module ROMs
+        # The KERNAL ROMs a machine can be fitted with, by name: the C64's,
+        # the SX-64's, the PET 64's and the C64GS's. The C64GS's is a 16K
+        # image of its BASIC and its KERNAL, and fits both.
+        KERNALS = {
+          c64: "kernal.rom", sx64: "kernal-sx64.rom", pet64: "kernal-pet64.rom", gs: "c64gs.rom"
+        }.freeze
+
+        attr_reader :basic_rom, :character_rom, :kernal_rom, :kernal
+
+        # Fits the KERNAL ROM KERNALS names `name`, in place of the one before,
+        # with the BASIC of a 16K image or else the C64's.
+        def kernal=(name)
+          raise ArgumentError, "no KERNAL named #{name}" unless KERNALS.key?(name)
+
+          @kernal = name
+          data = ROM.read(KERNALS[name])
+          basic = data.length == 0x4000 ? data[0, 0x2000] : ROM.read("basic.rom")
+          @basic_rom = ROM.new(basic, length: 0x2000, start: 0xa000)
+          @kernal_rom = ROM.new(data[-0x2000, 0x2000], length: 0x2000, start: 0xe000)
+          update_overlays!
+        end
+
+        private
+
+        def load_roms
+          @basic_rom = ROM.load("basic.rom", 0xa000)
+          @character_rom = ROM.load("character.rom", 0xd000)
+          @kernal = :c64
+          @kernal_rom = ROM.load(KERNALS[:c64], 0xe000)
+        end
+      end
+    end
+  end
+end