badline 0.12.1 → 0.14.0

data/lib/badline/chips/cpu/operations.rb

@@ -0,0 +1,90 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      # Steps that read or write an instruction's operand once its address is
+      # known, plus the branch and JAM steps.
+      module Operations
+        private
+
+        def op_mem_read
+          send(@operation, @address, @memory.peek(@address))
+          end_instruction
+        end
+
+        def op_mem_write
+          send(@operation, @address, nil)
+          end_instruction
+        end
+
+        # Read-modify-write instructions (ASL, INC and the like) take three
+        # cycles here: read the value and compute the result, write the
+        # original value back, then write the result. The instruction method
+        # hands the result over through #write_modified.
+        def op_rmw_read
+          @value = @memory.peek(@address)
+          send(@operation, @address, @value)
+        end
+
+        def op_rmw_write_original
+          @memory.poke(@address, @value)
+        end
+
+        def op_rmw_write_result
+          @memory.poke(@address, @rmw_result)
+          end_instruction
+        end
+
+        def op_relative
+          offset = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 1) & 0xffff
+          @address = (@program_counter + signed_int8(offset)) & 0xffff
+          @branch_taken = false
+          send(@operation, @address, nil)
+          if @branch_taken
+            # A taken branch within the same page doesn't poll on its last cycle.
+            @skip_poll = true if same_page?
+          else
+            end_instruction
+          end
+        end
+
+        def op_branch
+          @memory.peek(@program_counter)
+          return unless same_page?
+
+          @program_counter = @address
+          end_instruction
+        end
+
+        # A branch to another page spends an extra cycle reading from the target's low byte on the old page.
+        def op_branch_fixup
+          @memory.peek((@program_counter & 0xff00) | (@address & 0xff))
+          @program_counter = @address
+          end_instruction
+        end
+
+        def same_page?
+          @address >> 8 == @program_counter >> 8
+        end
+
+        # Runs once for each address in JAM_ADDRESSES. By the time a step runs, @index already points at the next one.
+        def op_jam
+          position = @index - 2
+          @memory.peek(JAM_ADDRESSES[position - 1])
+          return unless position == JAM_ADDRESSES.length
+
+          @plan = JAMMED_PLAN
+          @writes = JAMMED_WRITES
+          @index = 0
+        end
+
+        def op_jammed
+          @index = 0
+          @memory.peek(0xffff)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/port.rb

@@ -0,0 +1,133 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      # The I/O port of the 6510 and the 8502 at $00 (direction) and $01
+      # (data). An input pin reads its pull-up, P4 reads the datasette's sense
+      # line, and a pin without a pull-up holds the charge last driven onto
+      # it. P5 drives the datasette motor through an inverter: low runs it,
+      # and P3 drives its write line.
+      #
+      # The 6510 has pull-ups on P0-P2 and P4 and leaves P3, P6 and P7
+      # floating. The 8502 adds a CAPS LOCK pin on P6, high while the key is
+      # up.
+      class Port
+        TAPE_SENSE = 0b0001_0000
+
+        # The direction and output registers, and the charge on the floating
+        # pins.
+        attr_reader :ddr, :data, :floating
+
+        # The port as the banking logic reads it (PortStatus).
+        attr_reader :status
+
+        # Whether CAPS LOCK is down, holding its pin low.
+        attr_reader :caps_lock
+
+        # +pullups+ and +floating+ are the masks of the pins with a pull-up and
+        # of the floating ones, and +caps_lock+ the CAPS LOCK pin's, 0 where
+        # there is none.
+        def initialize(datasette, pullups:, floating:, caps_lock: 0)
+          @datasette = datasette
+          @pullups = pullups
+          @floating_mask = floating
+          @caps_lock_pin = caps_lock
+          @caps_lock = false
+          @ddr = 0x00
+          @data = 0x00
+          @floating = 0x00
+          @change_handler = nil
+          @status = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: input_value)
+          @datasette.write_level = @status.tape_out?
+        end
+
+        # Calls the block after every write to the port, for the bus to remap
+        # its banks.
+        def on_change(&handler)
+          @change_handler = handler
+        end
+
+        # What a read of $01 sees.
+        def value = @status.value
+
+        def write_ddr(value)
+          @ddr = value
+          update
+        end
+
+        def write_data(value)
+          @data = value
+          update
+        end
+
+        # The RES line clears the direction and output registers. The floating
+        # pins keep their charge.
+        def reset!
+          @ddr = 0x00
+          @data = 0x00
+          update
+        end
+
+        # Sets the registers and the charge, as a snapshot restores them, and
+        # drives the datasette and calls the change handler as a write does.
+        def restore(ddr, data, floating)
+          load(ddr, data, floating)
+          update
+        end
+
+        # Sets the registers and the charge, as a snapshot loads them, without
+        # driving the datasette or calling the change handler. The write
+        # line takes P3's level without recording an edge.
+        def load(ddr, data, floating)
+          @ddr = ddr
+          @data = data
+          @floating = floating
+          refresh
+          @datasette.write_level = @status.tape_out?
+        end
+
+        # The registers and the charge in a keyed snapshot module
+        # (Snapshot::Keyed), under `prefix`. What a read sees is worked out
+        # again on load, and the bus maps its banks afterwards.
+        def save_fields(out, prefix)
+          out.int("#{prefix}ddr", @ddr).int("#{prefix}data", @data).int("#{prefix}floating", @floating)
+        end
+
+        def load_fields(input, prefix)
+          load(input.byte("#{prefix}ddr", @ddr), input.byte("#{prefix}data", @data),
+               input.byte("#{prefix}floating", @floating))
+        end
+
+        # Holds CAPS LOCK down, or lets it up.
+        def caps_lock=(down)
+          @caps_lock = down
+          refresh
+        end
+
+        # Reads the inputs again, after the datasette's sense line changes.
+        def refresh
+          @status.value = input_value
+        end
+
+        private
+
+        def update
+          driven = @ddr & @floating_mask
+          @floating = (@floating & ~driven) | (@data & driven)
+          refresh
+          @datasette.motor = !@status.tape_motor?
+          @datasette.write_line = @status.tape_out?
+          @change_handler&.call
+        end
+
+        def input_value
+          input = @pullups | (@floating & @floating_mask)
+          input |= @caps_lock_pin unless @caps_lock
+          input &= ~TAPE_SENSE if @datasette.sense_low?
+          (@data & @ddr) | (input & ~@ddr & 0xff)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/stack_operations.rb

@@ -0,0 +1,84 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      # Steps that use the stack: PHA, PHP, PLA, PLP, JSR, RTS and RTI.
+      module StackOperations
+        private
+
+        def op_push_exec
+          send(@operation, nil, nil)
+          end_instruction
+        end
+
+        def op_pull_dummy
+          @memory.peek(stack_address)
+        end
+
+        def op_pull_exec
+          send(@operation, nil, nil)
+          end_instruction
+        end
+
+        def op_pull_low
+          @stack_pointer = (@stack_pointer + 1) & 0xff
+          @address = @memory.peek(stack_address)
+        end
+
+        def op_pull_high
+          @stack_pointer = (@stack_pointer + 1) & 0xff
+          @address |= @memory.peek(stack_address) << 8
+        end
+
+        def op_rts_fixup
+          @memory.peek(@address)
+          @program_counter = (@address + 1) & 0xffff
+          end_instruction
+        end
+
+        def op_rti_pull_status
+          @stack_pointer = (@stack_pointer + 1) & 0xff
+          @status.value = @memory.peek(stack_address)
+          @status.break = false
+        end
+
+        def op_rti_pull_high
+          @stack_pointer = (@stack_pointer + 1) & 0xff
+          @program_counter = @address | (@memory.peek(stack_address) << 8)
+          end_instruction
+        end
+
+        def op_jsr_low
+          @address = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 2) & 0xffff
+        end
+
+        def op_jsr_dummy
+          @memory.peek(stack_address)
+        end
+
+        def op_jsr_push_high
+          @memory.poke(stack_address, high_byte(return_address))
+        end
+
+        def op_jsr_push_low
+          @memory.poke(stack_address(-1), low_byte(return_address))
+          @stack_pointer = (@stack_pointer - 2) & 0xff
+        end
+
+        # JSR reads its target's high byte after pushing the return address.
+        # A JSR running from the stack page can overwrite its own operand
+        # with that push, and then jumps to the overwritten address.
+        def op_jsr_high
+          @program_counter = @address | (@memory.peek(return_address) << 8)
+          end_instruction
+        end
+
+        def return_address
+          (@program_counter - 1) & 0xffff
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/traps.rb

@@ -0,0 +1,23 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module Traps
+        def install_trap(addr, &handler)
+          (@traps ||= {})[addr] = handler
+        end
+
+        def remove_trap(addr)
+          @traps&.delete(addr)
+        end
+
+        private
+
+        def run_traps
+          @traps[@program_counter]&.call if @traps
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu.rb

@@ -0,0 +1,17 @@
+# frozen_string_literal: true
+
+require "badline/chips/cpu/port"
+require "badline/chips/cpu/instruction"
+require "badline/chips/cpu/instruction_set"
+require "badline/chips/cpu/interrupts"
+require "badline/chips/cpu/traps"
+require "badline/chips/cpu/core"
+
+module Badline
+  module Chips
+    # The C64's 6510, on the C64::Bus.
+    class CPU
+      include Core
+    end
+  end
+end

data/lib/badline/chips/sid/catch_up.rb

@@ -0,0 +1,122 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class SID
+      # Running the DSP over the cycles that have passed since it last caught
+      # up, in spans that fast-forward the voices and end on a whole cycle.
+      module CatchUp
+        private
+
+        # Runs the cycles that have passed, landing each queued write on the
+        # cycle the CPU wrote it on.
+        def catch_up
+          replayed = 0
+          i = 0
+          while i < @deferred_writes.length
+            cycle = @deferred_writes[i]
+            run(cycle - replayed)
+            replayed = cycle
+            apply_write(@deferred_writes[i + 1], @deferred_writes[i + 2])
+            i += 3
+          end
+          run(@pending_cycles - replayed)
+          @deferred_writes.clear
+          @pending_cycles = 0
+        end
+
+        def run(cycles)
+          while cycles != 0
+            span = span(cycles)
+            fast_forward(span - 1) if span > 1
+            clock!(span)
+            cycles -= span
+          end
+        end
+
+        # The longest stretch that can be fast-forwarded. A combined waveform
+        # feeding back into its own oscillator steps cycle by cycle, and a span
+        # never runs past an MSB rise that hard-syncs the next voice, so both
+        # land on a whole cycle.
+        def span(cycles)
+          return 1 if @stepped
+
+          span = @synthesizing ? synthesis_span(cycles) : cycles
+          return span unless @synced
+
+          span = sync_span(@waveform1, span)
+          span = sync_span(@waveform2, span)
+          sync_span(@waveform3, span)
+        end
+
+        # The filter steps at most @filter_chunk cycles at a time, and never
+        # across the end of a recorded sample.
+        def synthesis_span(cycles)
+          span = [cycles, @filter_chunk].min
+          return span unless @decimator
+
+          [@decimator.cycles_to_close, span].min
+        end
+
+        # Whether a span has to step, or watch for hard sync, only changes with
+        # a voice's control register.
+        def update_span_rules
+          @stepped = @voices.any? { |voice| voice.waveform.stepped?(@synthesizing) }
+          @synced = @voices.any? { |voice| voice.waveform.sync? }
+        end
+
+        def sync_span(waveform, span)
+          return span unless waveform.sync_dest.sync?
+
+          rise = waveform.cycles_to_msb_rise
+          rise && rise < span ? rise : span
+        end
+
+        # Unrolled over the three voices: the per-cycle block calls cost
+        # measurably on the synthesis path.
+        def fast_forward(cycles)
+          @voice1.fast_forward(cycles)
+          @voice2.fast_forward(cycles)
+          @voice3.fast_forward(cycles)
+        end
+
+        # The last cycle of a span, run whole. The filter integrates the span
+        # from the voices' output at its end.
+        def clock!(span)
+          @voice1.cycle!
+          @voice2.cycle!
+          @voice3.cycle!
+          @waveform1.synchronize!
+          @waveform2.synchronize!
+          @waveform3.synchronize!
+          return unless @synthesizing
+
+          @filter.cycle!(@voices, span)
+          record_sample(span) if @decimator
+        end
+
+        def record_sample(span)
+          sample = @decimator.push(current_sample, span)
+          return unless sample
+
+          @samples << sample
+          record_voices if @voice_samples
+        end
+
+        def record_voices
+          voice_samples = @voice_samples
+          voice_samples << (@voice1.output >> 7)
+          voice_samples << (@voice2.output >> 7)
+          voice_samples << (@voice3.output >> 7)
+        end
+
+        def current_sample
+          sample = @filter.output / SAMPLE_DIVISOR
+          return sample unless sample < -0x8000 || sample > 0x7fff
+
+          sample.clamp(-0x8000, 0x7fff)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/sid/decimator.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class SID
+      # Reduces the SID's one-sample-per-cycle stream to an audio rate by
+      # averaging each window. Point sampling would be cheaper, but the pulse
+      # and noise waveforms carry enough energy above the output Nyquist to
+      # alias audibly.
+      #
+      # A sample can stand for several cycles at once, when the DSP has run
+      # them as one step.
+      class Decimator
+        def initialize(clock_hz:, rate:)
+          @clock_hz = clock_hz
+          @rate = rate
+          @phase = 0
+          @sum = 0
+          @count = 0
+          @cycles_to_close = window_cycles
+        end
+
+        # Cycles until the current window closes, counting the next one as 1.
+        attr_reader :cycles_to_close
+
+        # How far the current window has got, in a keyed snapshot module
+        # (Snapshot::Keyed) under `prefix`. The clock and the rate are the
+        # host's.
+        def save_fields(out, prefix)
+          out.int("#{prefix}phase", @phase).int("#{prefix}sum", @sum).int("#{prefix}count", @count)
+          out.int("#{prefix}cycles_to_close", @cycles_to_close)
+        end
+
+        def load_fields(input, prefix)
+          @phase = input.int("#{prefix}phase", @phase)
+          @sum = input.int("#{prefix}sum", @sum)
+          @count = input.int("#{prefix}count", @count)
+          @cycles_to_close = input.int("#{prefix}cycles_to_close", @cycles_to_close)
+        end
+
+        # Returns the averaged sample when these cycles close a window, and
+        # nil otherwise. They must not run past the window's end.
+        def push(sample, cycles = 1)
+          @sum += sample * cycles
+          @count += cycles
+          @phase += @rate * cycles
+          @cycles_to_close -= cycles
+          return unless @phase >= @clock_hz
+
+          @phase -= @clock_hz
+          @cycles_to_close = window_cycles
+          average
+        end
+
+        private
+
+        def window_cycles = (@clock_hz - @phase + @rate - 1) / @rate
+
+        def average
+          value = @sum.fdiv(@count).round
+          @sum = 0
+          @count = 0
+          value
+        end
+      end
+    end
+  end
+end