badline 0.12.1 → 0.14.0

data/lib/badline/vic20/keyed_state.rb

@@ -0,0 +1,45 @@
+# frozen_string_literal: true
+
+module Badline
+  class Vic20
+    # The machine's own fields in a keyed snapshot module (Snapshot::Keyed,
+    # BL-MACHINE): the family, its RAM expansion by name, the cycle count,
+    # the RESTORE key's NMI, and the host's typing still to feed and on_init
+    # handlers still to run under host.*.
+    module KeyedState
+      # How many more on_init handlers the machine a snapshot was taken of had
+      # yet to run than this one has. Nil until the machine is restored.
+      attr_reader :init_handlers_lost
+
+      # Whether a snapshot saves now (Machine::Settling): the CPU between
+      # instructions or jammed.
+      def settled_for_snapshot? = @cpu.boundary? || @cpu.jammed?
+
+      # The sound's voices, run up to this cycle.
+      def settle_chips_for_snapshot = @sound.catch_up!
+
+      def save_machine_fields(out)
+        out.text("family", "vic20").text("written_by", VERSION)
+        Snapshot::Vic20Setup.new(ram: @ram_configuration).write_fields(out)
+        out.int("cycles", @cycles).bool("nmi_asserted", @nmi_asserted)
+        pending = @pending_keys
+        out.ints("host.pending_keys", pending) if pending
+        out.int("host.init_pending", @cycles <= @init_threshold ? @init_handlers.length : 0)
+      end
+
+      def load_machine_fields(input)
+        @cycles = input.int("cycles", @cycles)
+        @nmi_asserted = input.bool("nmi_asserted", @nmi_asserted)
+        pending = input.ints("host.pending_keys", [])
+        @pending_keys = pending.empty? ? nil : pending.dup
+        @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
+      end
+
+      # The serial bus's lines and the datasette's motor and write line from
+      # the VIAs, once they are loaded.
+      def machine_restored! = via_written
+    end
+
+    include KeyedState
+  end
+end

data/lib/badline/vic20/port_wiring.rb

@@ -16,12 +16,12 @@ module Badline
     # on VIA 1's PA6, its motor runs while VIA 1's CA2 is low, and VIA 2's
     # PB3 drives its write line, the same pin as a keyboard column.
     module PortWiring
-      # The lines the machine pulls, as IECBus host lines.
+      # The lines the machine pulls, as Drives::SerialBus host lines.
       def serial_lines
         lines = 0
-        lines |= IECBus::HOST_ATN_OUT if @via1.port_a_output.anybits?(0x80)
-        lines |= IECBus::HOST_CLK_OUT if @via2.ca2_output
-        lines |= IECBus::HOST_DATA_OUT if @via2.cb2_output
+        lines |= Drives::SerialBus::HOST_ATN_OUT if @via1.port_a_output.anybits?(0x80)
+        lines |= Drives::SerialBus::HOST_CLK_OUT if @via2.ca2_output
+        lines |= Drives::SerialBus::HOST_DATA_OUT if @via2.cb2_output
         lines
       end
 

data/lib/badline/vic20/user_via_ports.rb

@@ -38,8 +38,8 @@ module Badline
       def serial_inputs
         low = @serial_bus.low_lines
         value = 0x03
-        value &= ~0x01 if low.anybits?(IECBus::CLK)
-        value &= ~0x02 if low.anybits?(IECBus::DATA)
+        value &= ~0x01 if low.anybits?(Drives::SerialBus::CLK)
+        value &= ~0x02 if low.anybits?(Drives::SerialBus::DATA)
         value
       end
     end

data/lib/badline/vic20.rb

@@ -6,9 +6,9 @@ require "badline/vic20/cpu"
 require "badline/vic20/keyboard_via_ports"
 require "badline/vic20/port_wiring"
 require "badline/vic20/user_via_ports"
-require "badline/vic20/vic"
-require "badline/vic20/sound"
-require "badline/vic20/saved_state"
+require "badline/snapshot/vic20_setup"
+require "badline/vic20/keyed_state"
+require "badline/vic20/keyed_modules"
 
 module Badline
   # The Commodore VIC-20 with the PAL 6561: a 6502 at the VIC's clock, the
@@ -22,11 +22,11 @@ module Badline
   # serves disks through the KERNAL traps or a true 1541.
   class Vic20
     include IntegerHelper
-    include KeyboardBuffer
+    include Machine::KeyboardBuffer
     include Machine::Clocking
+    include Machine::Settling
     include Attachments
     include PortWiring
-    include SavedState
 
     attr_reader :bus, :cpu, :vic, :via1, :via2, :keyboard, :joystick1, :cycles, :init_threshold, :sound,
                 :drive1541, :iec_bus, :datasette
@@ -36,6 +36,11 @@ module Badline
 
     def ram = @bus.ram
 
+    # Reads and writes memory as the CPU sees it, through the bus.
+    def peek(addr) = @bus.peek(addr)
+
+    def poke(addr, value) = @bus.poke(addr, value)
+
     def family = :vic20
 
     # The one control port's joystick, which the front end's second
@@ -48,26 +53,26 @@ module Badline
     # +ram+ names the RAM expansion, one of Bus::RAM_CONFIGURATIONS.
     def initialize(ram: :unexpanded, debug: false)
       @ram_configuration = ram
-      @vic = VIC.new
-      @keyboard = Keyboard.new(matrix: KeyboardVIAPorts::MATRIX)
-      @joystick1 = Joystick.new
-      @iec_bus = IECBus.new
-      @datasette = Datasette.new
-      @via1 = VIA.new(start: 0x9000, peripheral: UserVIAPorts.new(joystick: @joystick1, serial_bus: @iec_bus,
-                                                                  datasette: @datasette))
+      @vic = Chips::VICI.new
+      @keyboard = Input::Keyboard.new(matrix: KeyboardVIAPorts::MATRIX)
+      @joystick1 = Input::Joystick.new
+      @iec_bus = Drives::SerialBus.new
+      @datasette = Drives::Datasette.new
+      @via1 = Chips::VIA.new(start: 0x9000, peripheral: UserVIAPorts.new(joystick: @joystick1, serial_bus: @iec_bus,
+                                                                         datasette: @datasette))
       keyboard_ports = KeyboardVIAPorts.new(keyboard: @keyboard, joystick: @joystick1)
-      @via2 = VIA.new(start: 0x9000, peripheral: keyboard_ports)
+      @via2 = Chips::VIA.new(start: 0x9000, peripheral: keyboard_ports)
       keyboard_ports.connect(@via2)
       @bus = Bus.new(vic: @vic, via1: @via1, via2: @via2, blocks: Bus::RAM_CONFIGURATIONS.fetch(ram))
       @vic.connect(@bus)
       @cpu = CPU.new(@bus, debug:)
       @cycles = 0
-      @sound = Sound.new(self, @vic.profile.clock_hz)
+      @sound = Chips::VICI::Sound.new(self, @vic.profile.clock_hz)
       @vic.sound = @sound
       @nmi_asserted = false
       @init_handlers = []
       @pending_keys = nil
-      @drive = nil
+      @dos = nil
       @serial_trap = nil
       @save_trap = nil
       @capture_output = nil
@@ -111,7 +116,7 @@ module Badline
     # xvic draws them.
     def timing
       profile = @vic.profile
-      width = profile.cycles_per_line * VIC::PIXELS_PER_CYCLE
+      width = profile.cycles_per_line * Chips::VICI::PIXELS_PER_CYCLE
       blanked = profile.blanked_lines
       Timing.new(clock_hz: profile.clock_hz, cycles_per_line: profile.cycles_per_line,
                  lines_per_frame: profile.lines_per_frame,
@@ -148,7 +153,7 @@ module Badline
       @via1.reset!
       @via2.reset!
       via_written
-      @drive&.reset!
+      @dos&.reset!
       @drive1541&.reset!
       @drive1581&.reset!
       @nmi_asserted = false

data/lib/badline.rb

@@ -2,6 +2,7 @@
 
 require "badline/core"
 require "badline/c128"
+require "badline/plus4"
 require "badline/options"
 require "badline/data_path"
 require "badline/snapshot"