badline 0.12.1 → 0.14.0

data/lib/badline/chips/sid/waveform/noise_writeback.rb

@@ -0,0 +1,124 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class SID
+      class Waveform
+        # Noise combined with other waveforms: the output lines write back into
+        # the LFSR, and what they write is not always what OSC3 reads.
+        module NoiseWriteback
+          # The LFSR bits the noise shaper reads, paired with the output bit each
+          # one drives (Dag Lem's diagram in SID/noise-reset_new). A combined
+          # waveform drives the same lines, so a bit held low there is written
+          # back into the register.
+          NOISE_TAPS = [[0x100000, 0x800], [0x040000, 0x400], [0x004000, 0x200],
+                        [0x000800, 0x100], [0x000200, 0x080], [0x000020, 0x040],
+                        [0x000004, 0x020], [0x000001, 0x010]].freeze
+
+          # Pulse+noise with the pulse high: the noise lines next to the four
+          # below them, which nothing drives, are pulled low. The OSC3 read and
+          # the LFSR writeback see the same lines against different thresholds,
+          # so they lose a different number of bits. The 8580's pair is the one
+          # that reproduces SID/wf12nsr's pulse+noise row (it reads $f8, and the
+          # writeback leaves $fc behind), and SID/wb_testsuite's C->9 and C->E
+          # rows need that same $fc written at release. The 6581 reads $00 of a
+          # full register (SID/wf12nsr's pulse+noise row) and pulls nothing
+          # while the register holds: wb_testsuite's 8->C and C->C rows run
+          # pulse+noise and leave the register alone. Its lines only land
+          # part way through a shift (#write_back_shift).
+          PULSE_NOISE_READ = { mos6581: 0x000, mos8580: 0xf80 }.freeze
+          PULSE_NOISE_WRITE = { mos6581: 0xff0, mos8580: 0xfc0 }.freeze
+
+          # What a 6581 writes back when the test bit falls with only pulse+noise
+          # common to the old waveform and the new one (SID/wb_testsuite's D->C,
+          # E->C, F->C and D->E rows).
+          PULSE_NOISE_RELEASE = 0xf80
+
+          private
+
+          # What the lines write into the LFSR, against a lower threshold than
+          # OSC3 reads them by: a line left high between two low ones reads high
+          # (SID/noisewriteback's noise_writeback_test2) but is written low
+          # (SID/wf12nsr's noise+triangle and noise+sawtooth rows).
+          def write_back(selected, value)
+            return value & ((value << 1) | (value >> 1)) unless selected == 0xc
+            return 0x000 if @pulse.zero?
+
+            noise & @pulse_noise_write
+          end
+
+          # What the lines write while the register is part way through a
+          # shift, where the 6581's pulse+noise writes its output as read.
+          def write_back_mid_shift(selected, value)
+            return value if pulse_noise_mid_shift?(selected)
+
+            write_back(selected, value)
+          end
+
+          def pulse_noise_mid_shift?(selected) = @topbit_feedback && selected == 0xc
+
+          def write_shift_register(value)
+            NOISE_TAPS.each { |bit, line| @shift_register &= ~bit if value.nobits?(line) }
+          end
+
+          # The second phase of a shift writes back by the test bit release
+          # rule with the waveform left alone. The 6581's pulse+noise, which
+          # that rule leaves out, writes its lines too (SID/wf12nsr's
+          # pulse+noise row).
+          def write_back_shift
+            return unless pulse_noise_mid_shift?(@selected) || release_writes_back?(@selected, @selected)
+
+            write_shift_register(write_back_mid_shift(@selected, @output))
+          end
+
+          # Setting the test bit starts the bleed, and stalls the register part
+          # way through a shift, where a noise combination writes its output
+          # back first, from the accumulator it had. SID/noiselfsrinit's
+          # $f8/$80 pairs set the bit onto all four from noise alone, and
+          # SID/wf12nsr's pulse+noise row sets it onto pulse+noise.
+          def raise_test
+            @shift_register_reset = @shift_register_reset_delay
+            return unless @selected.anybits?(0x8) && combined?(@selected) && @shift_pipeline != 1
+
+            write_shift_register(write_back_mid_shift(@selected, shape(@selected)))
+          end
+
+          # Releasing the test bit finishes the shift it interrupted: the old
+          # waveform's output may be written back first, then a bit clocks in
+          # over the forced-high bit 22.
+          def release_test(previous)
+            value = release_write(previous)
+            write_shift_register(value) if value
+            shift_noise(1)
+          end
+
+          # What the release writes over the taps, or nil. On the 6581, a change
+          # that keeps only pulse+noise of the old waveform writes the lowest
+          # noise lines low. On the 8580, a change from pulse+noise to all four
+          # writes every line low.
+          def release_write(previous)
+            if @topbit_feedback
+              return noise & PULSE_NOISE_RELEASE if previous != 0xc && (previous & @selected) == 0xc
+            elsif previous == 0xc && @selected == 0xf
+              return 0x000
+            end
+            write_back(previous, shape(previous)) if release_writes_back?(previous, @selected)
+          end
+
+          # Which waveform changes write the old output back as the test bit
+          # falls (SID/wb_testsuite, after libresidfp's do_writeback). Noise has
+          # to have been combined before and still be combined after. Nothing
+          # is written back on changing to pulse+noise or from pulse+noise to
+          # sawtooth+noise, nor, on the 6581, on trading triangle for sawtooth
+          # or back.
+          def release_writes_back?(previous, selected)
+            return false if previous <= 0x8 || selected <= 0x8
+            return false if selected == 0xc || (previous == 0xc && selected == 0xa)
+
+            !(@topbit_feedback && [previous & 0x3, selected & 0x3].sort == [0x1, 0x2])
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/sid/waveform.rb

@@ -0,0 +1,305 @@
+# frozen_string_literal: true
+
+require "badline/chips/sid/waveform/combined"
+require "badline/chips/sid/waveform/fast_forward"
+require "badline/chips/sid/waveform/noise_writeback"
+
+module Badline
+  module Chips
+    class SID
+      # Waveform generator: a 24-bit phase accumulator and the shapers that
+      # read it.
+      #
+      # The accumulator advances by the 16-bit frequency every cycle, so every
+      # waveform is a pure function of the phase. Bit 23 drives hard sync and
+      # the triangle fold, bit 19 clocks the noise LFSR.
+      #
+      # Selecting more than one waveform shorts the shapers onto the lines the
+      # oscillator itself reads back, so a combined waveform is not only a
+      # shape: a low top bit reaches the accumulator MSB through the sawtooth
+      # switch, and noise in the mix is written back into the LFSR. The shape
+      # itself comes from Combined's model of the lines pulling on each other.
+      #
+      # The pulse comparator's output reaches the lines a cycle after the
+      # accumulator it compared.
+      #
+      # With nothing selected the DAC input floats, holding the last value
+      # driven onto it until the charge drains away.
+      class Waveform
+        include FastForward
+        include NoiseWriteback
+
+        # All bits high at power up, odd ones stored inverted (SID/oscinit).
+        POWER_ON_ACCUMULATOR = 0x555555
+
+        # Holding the test bit bleeds every LFSR bit high; the power-on state is
+        # one shift further on, which is what releasing the bit leaves behind.
+        SHIFT_REGISTER_RESET = 0x7fffff
+        NOISE_SEED = 0x7ffffe
+
+        # Cycles the test bit needs to bleed the LFSR high. SID/bitfade's
+        # delaynoise measures ~$950000 on a real 8580. Nothing measures the
+        # 6581: SID/resid-test's oscsample dumps show it holding its bits
+        # through the ~$8800 cycles between runs, and the slow reset
+        # (SID/noise-reset_old) allows it a second.
+        SHIFT_REGISTER_RESET_DELAY = { mos6581: 0x80000, mos8580: 0x950000 }.freeze
+
+        # Cycles the floating DAC input holds its charge (SID/osc3-wave0).
+        FLOATING_OUTPUT_TTL = 0x4000
+
+        MSB = 0x800000
+
+        attr_accessor :sync_source, :sync_dest
+        attr_reader :accumulator, :shift_register, :frequency, :pulse_width, :pulse
+
+        def initialize(model: :mos6581)
+          use_model(model)
+          @tri_saw_delay = model == :mos8580
+          @accumulator = POWER_ON_ACCUMULATOR
+          @sync_source = @sync_dest = self
+          reset!
+        end
+
+        # The running state carries over. A 6581 never delays its shapers, so
+        # the 8580's delayed triangle and sawtooth start from the current phase.
+        def model=(model)
+          use_model(model)
+          if model == :mos8580 && !@tri_saw_delay
+            @delayed_sawtooth = sawtooth
+            @delayed_triangle = triangle
+          end
+          @tri_saw_delay = model == :mos8580
+        end
+
+        # The RES line clears the registers and reseeds the LFSR, but leaves
+        # the accumulator alone (SID/oscinit).
+        def reset!
+          @delayed_sawtooth = @delayed_triangle = 0x000
+          @shift_register = NOISE_SEED
+          @shift_register_reset = 0
+          @shift_pipeline = 0
+          @frequency = 0x0000
+          @pulse_width = 0x000
+          @selected = 0x0
+          @test = false
+          @ring = false
+          @sync = false
+          @msb_rising = false
+          @floating = 0x000
+          @floating_ttl = 0
+          @pulse = 0xfff
+          @output = 0x000
+          @stale = true
+        end
+
+        def sync? = @sync
+        def msb_rising? = @msb_rising
+
+        def frequency_low=(value)
+          @frequency = (@frequency & 0xff00) | value
+        end
+
+        def frequency_high=(value)
+          @frequency = (value << 8) | (@frequency & 0x00ff)
+        end
+
+        def pulse_width_low=(value)
+          @pulse_width = (@pulse_width & 0xf00) | value
+          @stale = true
+        end
+
+        def pulse_width_high=(value)
+          @pulse_width = ((value & 0x0f) << 8) | (@pulse_width & 0x0ff)
+          @stale = true
+        end
+
+        # The test bit clears the accumulator and stalls the LFSR half way
+        # through a shift, holding bit 22 high while its bits bleed up.
+        def control=(value)
+          previous = @selected
+          @selected = (value >> 4) & 0x0f
+          @ring = value.anybits?(0x04)
+          @sync = value.anybits?(0x02)
+          test = value.anybits?(0x08)
+          if test
+            raise_test unless @test
+            @accumulator = 0x000000
+            @pulse = 0xfff
+            @shift_pipeline = 0
+          elsif @test
+            release_test(previous)
+          end
+          @test = test
+          @stale = true
+        end
+
+        def cycle!
+          latch_output
+          compare_pulse
+          @test ? bleed_shift_register : advance
+          @stale = true
+        end
+
+        # Hard sync resets the next voice's accumulator when ours wraps. A
+        # source that is itself synced on the cycle its own MSB rises does not
+        # pass the sync on.
+        def synchronize!
+          return unless @msb_rising && @sync_dest.sync? &&
+                        !(@sync && @sync_source.msb_rising?)
+
+          @sync_dest.reset_accumulator
+        end
+
+        def reset_accumulator
+          @accumulator = 0x000000
+          @stale = true
+        end
+
+        # Held for the rest of the cycle once computed, so the filter, OSC3 and
+        # the oscillator's own feedback all see one value per cycle.
+        def output
+          return @output unless @stale
+
+          @stale = false
+          @output = @selected.zero? ? @floating : shape(@selected)
+        end
+
+        # What OSC3 reads. The 8580 delays the triangle and sawtooth shapers
+        # by half a cycle, which OSC3 latches as a whole cycle late; pulse and
+        # noise still reach the lines on time.
+        def osc3
+          return output unless @tri_saw_delay && @selected.anybits?(0x3)
+
+          shape(@selected, @delayed_sawtooth, @delayed_triangle)
+        end
+
+        def sawtooth = @accumulator >> 12
+
+        # The upper half of the ramp is folded back down, shifted left one bit
+        # to keep the full 12-bit range.
+        def triangle(selected = @selected)
+          folded = inverted?(selected) ? @accumulator ^ 0xffffff : @accumulator
+          (folded >> 11) & 0xfff
+        end
+
+        # Eight taps off the 23-bit LFSR, gathered into a 12-bit sample.
+        def noise
+          ((@shift_register & 0x100000) >> 9) |
+            ((@shift_register & 0x040000) >> 8) |
+            ((@shift_register & 0x004000) >> 5) |
+            ((@shift_register & 0x000800) >> 3) |
+            ((@shift_register & 0x000200) >> 2) |
+            ((@shift_register & 0x000020) << 1) |
+            ((@shift_register & 0x000004) << 3) |
+            ((@shift_register & 0x000001) << 4)
+        end
+
+        private
+
+        def use_model(model)
+          @topbit_feedback = model != :mos8580
+          @pulse_noise_read = PULSE_NOISE_READ.fetch(model)
+          @pulse_noise_write = PULSE_NOISE_WRITE.fetch(model)
+          @combined = Combined.tables(model)
+          @shift_register_reset_delay = SHIFT_REGISTER_RESET_DELAY.fetch(model)
+        end
+
+        def shape(selected, saw = sawtooth, tri = triangle(selected))
+          case selected
+          when 0x1 then tri
+          when 0x2 then saw
+          when 0x4 then @pulse
+          when 0x8 then noise
+          else combined(selected, saw, tri)
+          end
+        end
+
+        # A low pulse grounds every line. Noise with pulse alone loses its
+        # lowest lines; noise with triangle or sawtooth is ANDed over the rest
+        # of the mix.
+        def combined(selected, saw, tri)
+          return 0x000 if selected.anybits?(0x4) && @pulse.zero?
+          return noise & @pulse_noise_read if selected == 0xc
+
+          rest = selected & 0x7
+          value = case rest
+                  when 0x1 then tri
+                  when 0x2 then saw
+                  when 0x4 then 0xfff
+                  else @combined[rest][rest == 0x5 ? tri : saw]
+                  end
+          selected.anybits?(0x8) ? value & noise : value
+        end
+
+        def compare_pulse(phase = @accumulator >> 12) = (@pulse = @test || phase >= @pulse_width ? 0xfff : 0x000)
+
+        # More than one bit set in the selection.
+        def combined?(selected) = selected & (selected - 1) != 0
+
+        # The one point in the cycle where the waveform selector drives the DAC:
+        # either it latches a fresh value, or nothing drives the line and the
+        # charge already on it drains a little further.
+        def latch_output
+          value = output
+          if @tri_saw_delay
+            @delayed_sawtooth = sawtooth
+            @delayed_triangle = triangle
+          end
+          if @selected.zero?
+            drain_floating(1)
+            return
+          end
+
+          @floating = value
+          @floating_ttl = FLOATING_OUTPUT_TTL
+          feed_back(value) if combined?(@selected) && !@test
+        end
+
+        # A zero on the shared output lines travels back into the oscillator:
+        # through the sawtooth switch it clears the accumulator MSB on the next
+        # cycle, and with noise selected it lands in the LFSR, where a bit
+        # pulled low can never come back. The 8580 buffers the top bit behind a
+        # flip-flop before the sawtooth switch, so only the LFSR sees it. In the
+        # first phase of a shift the register bits float, so nothing is pulled
+        # down: the output is latched instead, for the second phase to write.
+        def feed_back(value)
+          @accumulator &= ~MSB if @topbit_feedback && @selected.anybits?(0x2) && value.nobits?(0x800)
+          write_shift_register(write_back(@selected, value)) if @selected.anybits?(0x8) && @shift_pipeline != 1
+        end
+
+        # A rise of bit 19 starts a shift that takes two more cycles
+        # (SID/noisewriteback's noise_writeback_test2, after libresidfp's shift
+        # pipeline). The first phase latches the output, and the second writes
+        # it over the taps before the register shifts.
+        def advance
+          previous = @accumulator
+          @accumulator = (previous + @frequency) & 0xffffff
+          @msb_rising = @accumulator & ~previous & MSB != 0
+          if @accumulator & ~previous & 0x080000 != 0
+            @shift_pipeline = 2
+          elsif @shift_pipeline != 0 && (@shift_pipeline -= 1).zero?
+            write_back_shift
+            shift_noise
+          end
+        end
+
+        # Bit 0 feeds back bits 22 and 17, with the test bit forcing bit 22 high.
+        def shift_noise(forced = 0)
+          bit0 = ((@shift_register >> 22) | forced) ^ (@shift_register >> 17)
+          @shift_register = ((@shift_register << 1) & 0x7fffff) | (bit0 & 0x1)
+        end
+
+        # TriXOR = !Saw & ((!V3 & Ring) ^ bit23), where V3 is the modulating
+        # voice's MSB (SID/ringmod).
+        def inverted?(selected)
+          return false if selected & 0x2 != 0
+
+          msb = @accumulator & MSB != 0
+          return msb unless @ring
+
+          msb == (@sync_source.accumulator & MSB != 0)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/sid.rb

@@ -0,0 +1,264 @@
+# frozen_string_literal: true
+
+require "badline/chips/sid/waveform"
+require "badline/chips/sid/envelope"
+require "badline/chips/sid/voice"
+require "badline/chips/sid/filter"
+require "badline/chips/sid/decimator"
+require "badline/chips/sid/catch_up"
+require "badline/chips/sid/keyed_parts"
+
+module Badline
+  module Chips
+    # SID (Sound Interface Device) chip, in either the 6581 or the 8580
+    # revision.
+    #
+    # $D400-$D418 - Voices, filter and volume   - write only
+    # $D419-$D41A - POTX/POTY paddle inputs     - read only
+    # $D41B-$D41C - Voice 3 oscillator/envelope - read only
+    # $D41D-$D41F - Unconnected
+    #
+    # The register file mirrors every 32 bytes up to $D7FF. A second or
+    # third SID, which only the SID player fits, is built `at` another
+    # address and decodes just the 32 bytes there.
+    #
+    # Reading a write-only or unconnected register returns the last byte the
+    # SID saw on the data bus. That value fades to $00 as the capacitance
+    # holding it drains. Paddles and the 1351 mouse attach as a pots source
+    # responding to #pot_x and #pot_y; with none attached the lines read $FF.
+    #
+    # Three voices feed the filter and the master volume; #output and #sample
+    # read out the mixed result, and #record collects it at an audio rate for
+    # #drain_samples. The DSP is clocked lazily and catches up when something
+    # asks for its state.
+    #
+    # The 6581 drives its voices well above ground, so the mix carries a large
+    # DC offset that the RC network on the C64 board filters out.
+    class SID
+      include Addressable
+      include CatchUp
+
+      VOICES = 3
+
+      # Cycles the data bus holds a value, measured through SID/bitfade.
+      BUS_TTL = { mos6581: 0x1d00, mos8580: 0xa2000 }.freeze
+
+      # Scales the filter's 20-bit mix down to a signed 16-bit sample, as
+      # reSID 0.16 does: three voices at full swing and volume 15 span the
+      # whole range, on either chip.
+      SAMPLE_DIVISOR = ((0xfff * 0xff) >> 7) * 3 * 15 * 2 / (2**16)
+
+      # Writes the DSP queues between catch-ups. A full queue catches up
+      # there and then, so no write loses its timing.
+      DEFERRED_WRITES = 0x400
+
+      # Cycles the filter integrates in one step while synthesizing, after
+      # reSID's delta_t_flt. 1 makes the audio exact, at a per-cycle cost.
+      FILTER_CHUNK = 4
+
+      attr_accessor :pots
+      attr_reader :model
+
+      def initialize(model: :mos6581, pots: nil, filter_chunk: FILTER_CHUNK, at: 0xd400)
+        addressable_at(at, length: at == 0xd400 ? 2**10 : 2**5)
+        @model = model
+        @pots = pots
+        @bus_ttl_reset = BUS_TTL.fetch(model)
+        @filter = Filter.new(model:)
+        @synthesizing = false
+        @stepped = @synced = false
+        @pending_cycles = 0
+        @deferred_writes = []
+        @decimator = nil
+        @samples = []
+        @voice_samples = nil
+        @filter_chunk = filter_chunk
+        @voices = Voice.linked(VOICES, model:)
+        @voice1, @voice2, @voice3 = @voices
+        @waveform1, @waveform2, @waveform3 = @voices.map(&:waveform)
+        reset!
+      end
+
+      # Switches the chip, its filter and its voices to the other model's
+      # values. The cycles already passed run on the old model first, and the
+      # running state carries over.
+      def model=(model)
+        catch_up
+        @model = model
+        @bus_ttl_reset = BUS_TTL.fetch(model)
+        @filter.model = model
+        @voices.each { |voice| voice.model = model }
+        update_span_rules
+      end
+
+      # The RES line clears the registers, the data bus, the filter and the
+      # voices, all but their accumulators. Recording carries on across it.
+      def reset!
+        catch_up
+        @registers = Memory.new(length: 2**5)
+        @bus_value = 0x00
+        @bus_ttl = 0
+        @voices.each(&:reset!)
+        @filter.reset
+        update_span_rules
+      end
+
+      # The DSP only counts cycles as they pass. Whatever asks for its state
+      # catches it up, a span at a time: each span fast-forwards the voices
+      # and ends on one whole cycle, so everything the CPU can read stays
+      # exact. The filter only runs once something wants audio.
+      def synthesizing? = @synthesizing
+
+      def synthesize!
+        return if @synthesizing
+
+        @synthesizing = true
+        update_span_rules
+        catch_up
+      end
+
+      # Starts collecting the output, averaged down to `rate` samples a
+      # second, for #drain_samples. `filter_chunk` overrides the one the SID
+      # was built with, for a machine that built its own. `clock_hz` is the
+      # rate the SID's cycles are taken to run at.
+      def record(rate:, filter_chunk: @filter_chunk, clock_hz: Region::PAL.clock_hz)
+        synthesize!
+        catch_up
+        @filter_chunk = filter_chunk
+        @decimator = Decimator.new(clock_hz:, rate:)
+        @samples = []
+      end
+
+      # Also keeps each voice's own output, before the filter and the volume,
+      # as each recorded sample closes, for #drain_voice_samples.
+      def record_voices!
+        @voice_samples = [] if @voice_samples.nil?
+      end
+
+      # The voices' outputs since the last drain, three to a sample, in voice
+      # order, or nothing unless #record_voices! asked for them.
+      def drain_voice_samples
+        return [] if @voice_samples.nil?
+
+        catch_up
+        samples = @voice_samples
+        @voice_samples = []
+        samples
+      end
+
+      # The samples recorded since the last drain.
+      def drain_samples
+        catch_up
+        samples = @samples
+        @samples = []
+        samples
+      end
+
+      def voices
+        catch_up
+        @voices
+      end
+
+      # Runs the DSP up to the current cycle.
+      def catch_up! = catch_up
+
+      # The byte the data bus holds and the cycles until it fades.
+      def bus_state = [@bus_value, @bus_ttl]
+
+      def restore_bus(value, ttl)
+        @bus_value = value
+        @bus_ttl = ttl
+      end
+
+      def filter
+        catch_up
+        @filter
+      end
+
+      # Voice 3's oscillator and envelope, the only synthesis state the CPU
+      # can see. Programs poll OSC3 with the noise waveform selected for
+      # random numbers, and ENV3 to time hard restarts.
+      def osc3
+        catch_up
+        @waveform3.osc3 >> 4
+      end
+
+      def env3
+        catch_up
+        @voice3.envelope.env3
+      end
+
+      def output
+        synthesize!
+        catch_up
+        @filter.output
+      end
+
+      def sample
+        output
+        current_sample
+      end
+
+      def cycle!
+        age_bus if @bus_ttl != 0
+        @pending_cycles += 1
+      end
+
+      def peek(addr)
+        case offset_of(addr) % (2**5)
+        when 0x19 then latch(pots ? pots.pot_x : 0xff)
+        when 0x1a then latch(pots ? pots.pot_y : 0xff)
+        when 0x1b then latch(osc3)
+        when 0x1c then latch(env3)
+        else @bus_value
+        end
+      end
+
+      def poke(addr, value)
+        reg = offset_of(addr) % (2**5)
+        write_register(reg, value) if reg <= 0x18
+        latch(value)
+      end
+
+      # Register contents as written, for save states and debugging.
+      def register(reg) = @registers.peek(reg)
+
+      private
+
+      def latch(value)
+        @bus_ttl = @bus_ttl_reset
+        @bus_value = value
+      end
+
+      def age_bus
+        @bus_ttl -= 1
+        @bus_value = 0x00 if @bus_ttl.zero?
+      end
+
+      def write_register(reg, value)
+        @registers.poke(reg, value)
+        catch_up if @deferred_writes.length == DEFERRED_WRITES * 3
+        @deferred_writes.push(@pending_cycles, reg, value)
+      end
+
+      def apply_write(reg, value)
+        reg < 0x15 ? write_voice(reg, value) : @filter.write(reg, value)
+      end
+
+      def write_voice(reg, value)
+        voice = @voices[reg / 7]
+        case reg % 7
+        when 0 then voice.waveform.frequency_low = value
+        when 1 then voice.waveform.frequency_high = value
+        when 2 then voice.waveform.pulse_width_low = value
+        when 3 then voice.waveform.pulse_width_high = value
+        when 4
+          voice.control = value
+          update_span_rules
+        when 5 then voice.envelope.attack_decay = value
+        when 6 then voice.envelope.sustain_release = value
+        end
+      end
+    end
+  end
+end