badline 0.12.1 → 0.14.0

data/lib/badline/chips/cpu/instruction_set/transfer.rb

@@ -0,0 +1,141 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Transfer
+          # +begin_src ruby
+          # Load accumulator with memory.
+          #
+          # Opcodes:
+          #   $A1 - indirect_x - 6 cycles
+          #   $A5 - zeropage   - 3 cycles
+          #   $A9 - immediate  - 2 cycles
+          #   $AD - absolute   - 4 cycles
+          #   $B1 - indirect_y - 5+ cycles
+          #   $B5 - zeropage_x - 4 cycles
+          #   $B9 - absolute_y - 4+ cycles
+          #   $BD - absolute_x - 4+ cycles
+          def lda(_addr, value)
+            @a = value
+            update_number_flags(@a)
+          end
+
+          # Load X register with memory.
+          #
+          # Opcodes:
+          #   $A2 - immediate  - 2 cycles
+          #   $A6 - zeropage   - 3 cycles
+          #   $AE - absolute   - 4 cycles
+          #   $B6 - zeropage_y - 4 cycles
+          #   $BE - absolute_y - 4+ cycles
+          def ldx(_addr, value)
+            @x = value
+            update_number_flags(@x)
+          end
+
+          # Load Y register with memory.
+          #
+          # Opcodes:
+          #   $A0 - immediate  - 2 cycles
+          #   $A4 - zeropage   - 3 cycles
+          #   $AC - absolute   - 4 cycles
+          #   $B4 - zeropage_x - 4 cycles
+          #   $BC - absolute_x - 4+ cycles
+          def ldy(_addr, value)
+            @y = value
+            update_number_flags(@y)
+          end
+
+          # Store accumulator in memory.
+          #
+          # Opcodes:
+          #   $81 - indirect_x - 6 cycles
+          #   $85 - zeropage   - 3 cycles
+          #   $8D - absolute   - 4 cycles
+          #   $91 - indirect_y - 6 cycles
+          #   $95 - zeropage_x - 4 cycles
+          #   $99 - absolute_y - 5 cycles
+          #   $9D - absolute_x - 5 cycles
+          def sta(addr, _value)
+            write_byte(addr, @a)
+          end
+
+          # Store X register in memory.
+          #
+          # Opcodes:
+          #   $86 - zeropage   - 3 cycles
+          #   $8E - absolute   - 4 cycles
+          #   $96 - zeropage_y - 4 cycles
+          def stx(addr, _value)
+            write_byte(addr, @x)
+          end
+
+          # Store Y register in memory.
+          #
+          # Opcodes:
+          #   $84 - zeropage   - 3 cycles
+          #   $8C - absolute   - 4 cycles
+          #   $94 - zeropage_x - 4 cycles
+          def sty(addr, _value)
+            write_byte(addr, @y)
+          end
+
+          # Transfer accumulator to X register.
+          #
+          # Opcodes:
+          #   $AA - implied - 2 cycles
+          def tax(_addr, _value)
+            @x = a
+            update_number_flags(@x)
+          end
+
+          # Transfer accumulator to Y register.
+          #
+          # Opcodes:
+          #   $A8 - implied - 2 cycles
+          def tay(_addr, _value)
+            @y = a
+            update_number_flags(@y)
+          end
+
+          # Transfer stack pointer to X register.
+          #
+          # Opcodes:
+          #   $BA - implied - 2 cycles
+          def tsx(_addr, _value)
+            @x = stack_pointer
+            update_number_flags(@x)
+          end
+
+          # Transfer X register to accumulator.
+          #
+          # Opcodes:
+          #   $8A - implied - 2 cycles
+          def txa(_addr, _operand)
+            @a = x
+            update_number_flags(@a)
+          end
+
+          # Transfer X register to stack pointer.
+          #
+          # Opcodes:
+          #   $9A - implied - 2 cycles
+          def txs(_addr, _operand)
+            @stack_pointer = x
+          end
+
+          # Transfer Y register to accumulator.
+          #
+          # Opcodes:
+          #   $98 - implied - 2 cycles
+          def tya(_addr, _operand)
+            @a = y
+            update_number_flags(@a)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+require "badline/chips/cpu/instruction_set/arithmetic"
+require "badline/chips/cpu/instruction_set/bitwise"
+require "badline/chips/cpu/instruction_set/branch"
+require "badline/chips/cpu/instruction_set/inc_dec"
+require "badline/chips/cpu/instruction_set/flag"
+require "badline/chips/cpu/instruction_set/illegal"
+require "badline/chips/cpu/instruction_set/stack"
+require "badline/chips/cpu/instruction_set/transfer"
+
+module Badline
+  module Chips
+    class CPU
+      # http://www.6502.org/tutorials/6502opcodes.html
+      # http://www.e-tradition.net/bytes/6502/6502_instruction_set.html
+      module InstructionSet
+        include InstructionSet::Arithmetic
+        include InstructionSet::Bitwise
+        include InstructionSet::Branch
+        include InstructionSet::IncDec
+        include InstructionSet::Flag
+        include InstructionSet::Illegal
+        include InstructionSet::Stack
+        include InstructionSet::Transfer
+
+        # No operation. The illegal forms with an operand still read it, in
+        # the steps before this is called.
+        #
+        # Opcodes:
+        #   $EA                          - implied    - 2 cycles
+        #   $04, $44, $64                - zeropage   - 3 cycles  (illegal)
+        #   $14, $34, $54, $74, $D4, $F4 - zeropage_x - 4 cycles  (illegal)
+        #   $0C                          - absolute   - 4 cycles  (illegal)
+        #   $1C, $3C, $5C, $7C, $DC, $FC - absolute_x - 4+ cycles (illegal)
+        #   $1A, $3A, $5A, $7A, $DA, $FA - implied    - 2 cycles  (illegal)
+        def nop(_addr, _value); end
+
+        private
+
+        def update_number_flags(value)
+          status.zero = value.zero?
+          status.negative = value & 0x80 != 0
+          value
+        end
+
+        # Stores a read-modify-write result. For memory, the write happens in
+        # the steps that follow (see Operations#op_rmw_read).
+        def write_modified(addr, result)
+          if addr == :accumulator
+            @a = result
+          else
+            @rmw_result = result
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/interrupts.rb

@@ -0,0 +1,108 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module Interrupts
+        BREAK_MASK = 0x10
+
+        private
+
+        # Samples the IRQ line and the NMI latch once per cycle. An instruction
+        # boundary commits the sample taken on its second-to-last cycle.
+        def poll
+          if @skip_poll
+            @skip_poll = false
+            return
+          end
+          @irq_pending = @irq_sample
+          @nmi_pending = @nmi_sample
+          @irq_sample = @irq && !@status.interrupt?
+          @nmi_sample = @nmi
+        end
+
+        # A cycle the VIC stalls through BA keeps sampling the lines, OR-ed with
+        # the sample it already holds, but the boundary pipeline doesn't advance
+        # and a skipped poll stays owed to the next real cycle.
+        def sample_while_stalled
+          @irq_sample ||= @irq && !interrupt_disabled_after_stall?
+          @nmi_sample = true if @nmi
+        end
+
+        # A stalled CLI or SEI execute cycle masks with the I it is about to
+        # set. Every other step masks with the current I, PLP included: its
+        # pulled I only arrives with the stalled stack read.
+        def interrupt_disabled_after_stall?
+          return @status.interrupt? unless @plan.equal?(CPU::IMPLIED_PLAN)
+
+          case @operation
+          when :cli then false
+          when :sei then true
+          else @status.interrupt?
+          end
+        end
+
+        # Runs in the opcode fetch cycle in place of the fetch, with no bus
+        # access, and switches to the interrupt plan.
+        def start_interrupt
+          @interrupt = @boundary_nmi ? 0xfffa : 0xfffe
+          @brk = false
+          @plan = CPU::INTERRUPT_PLAN
+          @writes = CPU::INTERRUPT_WRITES
+          @index = 1
+        end
+
+        # BRK reads the byte after its opcode and ignores it, and selects the
+        # IRQ vector.
+        def op_brk_dummy
+          @memory.peek(@program_counter)
+          @interrupt = 0xfffe
+          @brk = true
+        end
+
+        def op_int_push_pch
+          @address = @brk ? (@program_counter + 1) & 0xffff : @program_counter
+          @memory.poke(stack_address, high_byte(@address))
+          @stack_pointer = (@stack_pointer - 1) & 0xff
+        end
+
+        def op_int_push_pcl
+          @memory.poke(stack_address, low_byte(@address))
+          @stack_pointer = (@stack_pointer - 1) & 0xff
+        end
+
+        def op_int_push_status
+          value = @brk ? @status.value | BREAK_MASK : @status.value & ~BREAK_MASK
+          @memory.poke(stack_address, value)
+          @stack_pointer = (@stack_pointer - 1) & 0xff
+          @status.interrupt = true
+          # An NMI that arrives before cycle 4 of a BRK or IRQ takes it over:
+          # the sequence finishes with the NMI vector.
+          @interrupt = 0xfffa if @interrupt == 0xfffe && @nmi_pending
+          @nmi = false if @interrupt == 0xfffa
+        end
+
+        def op_int_vector_low
+          @address = @memory.peek(@interrupt)
+        end
+
+        # Clears any interrupt that is pending, so the handler's first
+        # instruction always runs before the next interrupt. This applies to
+        # BRK too.
+        def op_int_vector_high
+          high = @memory.peek((@interrupt + 1) & 0xffff)
+          @program_counter = @address | (high << 8)
+          @irq_sample = @irq_pending = false
+          @nmi_sample = @nmi_pending = false
+          @interrupt = nil
+          if @brk
+            @status.break = false
+            end_instruction
+          else
+            end_sequence
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/keyed_state.rb

@@ -0,0 +1,177 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      # Where a CPU caught inside an instruction is, as a snapshot names it:
+      # an opcode's instruction, an IRQ or NMI sequence, or jammed.
+      POSITIONS = %w[boundary op interrupt jam].freeze
+
+      # The CPU's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers, the interrupt lines' pipeline, the counts and, inside an
+      # instruction, where it is in hardware terms (pos.*), rather than as
+      # the microcode lays it out.
+      module KeyedState
+        def save_fields(out)
+          out.int("pc", @program_counter).int("sp", @stack_pointer).int("a", @a).int("x", @x).int("y", @y)
+          out.int("p", @status.value).bool("nmi", @nmi).bool("so_high", @so_high)
+          out.bool("irq.sample", @irq_sample).bool("irq.pending", @irq_pending).bool("irq.boundary", @boundary_irq)
+          out.bool("nmi.sample", @nmi_sample).bool("nmi.pending", @nmi_pending).bool("nmi.boundary", @boundary_nmi)
+          out.bool("skip_poll", @skip_poll).optional_int("stalled", stalled_ago)
+          out.int("cycles", @cycles).int("instructions", @instructions)
+          save_position(out) unless boundary?
+          out
+        end
+
+        def load_fields(input)
+          @program_counter = input.word("pc", @program_counter)
+          @stack_pointer = input.byte("sp", @stack_pointer)
+          @a = input.byte("a", @a)
+          @x = input.byte("x", @x)
+          @y = input.byte("y", @y)
+          @status.value = input.byte("p", @status.value)
+          load_lines(input)
+          @cycles = input.int("cycles", @cycles)
+          @instructions = input.int("instructions", @instructions)
+          stalled = input.optional_int("stalled")
+          @stalled_at = stalled.nil? ? nil : @cycles - stalled
+          load_position(input)
+        end
+
+        # What the fields leave to be worked out: whether the next step
+        # writes.
+        def restored!
+          @pending_write = @writes[@index]
+        end
+
+        private
+
+        # Cycles since the CPU last stalled, when that was this cycle or the
+        # one before, the only ones an instruction looks back at.
+        def stalled_ago
+          stalled_at = @stalled_at
+          return nil if stalled_at.nil?
+
+          ago = @cycles - stalled_at
+          ago.between?(0, 1) ? ago : nil
+        end
+
+        def load_lines(input)
+          @nmi = input.bool("nmi", @nmi)
+          @so_high = input.bool("so_high", @so_high)
+          @irq_sample = input.bool("irq.sample", @irq_sample)
+          @irq_pending = input.bool("irq.pending", @irq_pending)
+          @boundary_irq = input.bool("irq.boundary", @boundary_irq)
+          @nmi_sample = input.bool("nmi.sample", @nmi_sample)
+          @nmi_pending = input.bool("nmi.pending", @nmi_pending)
+          @boundary_nmi = input.bool("nmi.boundary", @boundary_nmi)
+          @skip_poll = input.bool("skip_poll", @skip_poll)
+        end
+
+        def save_position(out)
+          source = plan_source
+          if source == JAMMED
+            out.text("pos.seq", "jam")
+            return
+          end
+
+          out.text("pos.seq", source == INTERRUPT ? "interrupt" : "op")
+          out.int("pos.op", source) unless source == INTERRUPT
+          out.int("pos.t", position_t(source)).bool("pos.crossed", @boundary_crossed)
+          out.bool("pos.branch_taken", @branch_taken == true).bool("pos.brk", @brk)
+          out.optional_int("pos.vector", @interrupt)
+          out.optional_int("pos.address", @address).optional_int("pos.dummy_address", @dummy_address)
+          out.optional_int("pos.value", @value).optional_int("pos.rmw", @rmw_result)
+          out.optional_int("pos.pointer", @pointer)
+        end
+
+        # The cycles of the instruction or sequence run so far, counting the
+        # opcode fetch as 1 and leaving out stalled cycles.
+        def position_t(source)
+          return @index if source == INTERRUPT
+
+          MICROCODE.fetch(source).t_at(@index, @boundary_crossed)
+        end
+
+        def load_position(input)
+          case input.choice("pos.seq", POSITIONS, "boundary")
+          when "op" then load_instruction(input)
+          when "interrupt" then load_interrupt(input)
+          when "jam" then load_jam
+          else load_boundary
+          end
+        end
+
+        def load_instruction(input)
+          micro = MICROCODE.fetch(input.byte("pos.op", 0xea))
+          use_plan(micro.plan, micro.writes)
+          @operation = micro.operation
+          @optional_dummy = micro.optional_dummy
+          @boundary_crossed = input.bool("pos.crossed", false)
+          @index = micro.index_at(input.int("pos.t", 1), @boundary_crossed).clamp(1, micro.plan.length - 1)
+          load_latches(input)
+        end
+
+        def load_interrupt(input)
+          use_plan(INTERRUPT_PLAN, INTERRUPT_WRITES)
+          @boundary_crossed = input.bool("pos.crossed", false)
+          @index = input.int("pos.t", 1).clamp(1, INTERRUPT_PLAN.length - 1)
+          load_latches(input)
+        end
+
+        def load_jam
+          use_plan(JAMMED_PLAN, JAMMED_WRITES)
+          @index = 0
+          clear_latches
+        end
+
+        def load_boundary
+          use_plan(FETCH_PLAN, FETCH_WRITES)
+          @index = 0
+          clear_latches
+        end
+
+        def load_latches(input)
+          @branch_taken = input.bool("pos.branch_taken", false)
+          @brk = input.bool("pos.brk", false)
+          @interrupt = input.optional_int("pos.vector")
+          @address = input.optional_int("pos.address")
+          @dummy_address = input.optional_int("pos.dummy_address")
+          @value = input.optional_int("pos.value")
+          @rmw_result = input.optional_int("pos.rmw")
+          @pointer = input.optional_int("pos.pointer")
+        end
+
+        # The working registers no step reads before the next instruction
+        # sets them.
+        def clear_latches
+          @boundary_crossed = false
+          @branch_taken = false
+          @brk = false
+          @interrupt = nil
+          @address = nil
+          @dummy_address = nil
+          @value = nil
+          @rmw_result = nil
+          @pointer = nil
+        end
+
+        # Where the plan running comes from: an opcode's microcode, or FETCH,
+        # INTERRUPT or JAMMED below it.
+        def plan_source
+          return FETCH if @plan.equal?(FETCH_PLAN)
+          return INTERRUPT if @plan.equal?(INTERRUPT_PLAN)
+          return JAMMED if @plan.equal?(JAMMED_PLAN)
+
+          MICROCODE.index { |micro| micro.plan.equal?(@plan) && micro.operation == @operation } ||
+            MICROCODE.index { |micro| micro.plan.equal?(@plan) }
+        end
+
+        def use_plan(plan, writes)
+          @plan = plan
+          @writes = writes
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/microcode.rb

@@ -0,0 +1,195 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      class InvalidOpcodeError < StandardError; end
+
+      # Steps that write to memory. The CPU keeps running through BA on
+      # cycles that write, so C64#cycle! asks before each cycle whether
+      # the next step is one of these.
+      WRITE_STEPS = %i[
+        op_mem_write op_rmw_write_original op_rmw_write_result op_push_exec op_jsr_push_high op_jsr_push_low
+        op_int_push_pch op_int_push_pcl op_int_push_status
+      ].freeze
+
+      # The steps each addressing mode takes to work out the address an
+      # instruction operates on. They run after the opcode fetch.
+      ADDRESSING_STEPS = {
+        zeropage: %i[op_zp],
+        zeropage_x: %i[op_zp op_zp_x],
+        zeropage_y: %i[op_zp op_zp_y],
+        absolute: %i[op_abs_low op_abs_high],
+        absolute_x: %i[op_abs_low op_abs_high_x op_idx_dummy],
+        absolute_y: %i[op_abs_low op_abs_high_y op_idx_dummy],
+        indirect_x: %i[op_zp_pointer op_pointer_x op_pointer_low op_pointer_high],
+        indirect_y: %i[op_zp_pointer op_pointer_low op_pointer_high_y op_idx_dummy]
+      }.freeze
+
+      # The steps that read or write that address, once it is known.
+      OPERATION_STEPS = {
+        read: %i[op_mem_read],
+        write: %i[op_mem_write],
+        rmw: %i[op_rmw_read op_rmw_write_original op_rmw_write_result]
+      }.freeze
+
+      STORES = %i[sta stx sty sax sha shx shy tas].freeze
+      READ_MODIFY_WRITES = %i[asl lsr rol ror inc dec slo sre rla rra isc dcp].freeze
+      BRANCHES = %i[bcc bcs beq bmi bne bpl bvc bvs].freeze
+
+      # The addresses a 6502 reads after a JAM opcode, before it settles into
+      # JAMMED_PLAN.
+      JAM_ADDRESSES = [0xffff, 0xfffe, 0xfffe].freeze
+
+      # The plan between instructions: the next cycle fetches an opcode.
+      FETCH_PLAN = %i[op_fetch].freeze
+
+      IMPLIED_PLAN = %i[op_fetch op_implied_exec].freeze
+      ACCUMULATOR_PLAN = %i[op_fetch op_accumulator_exec].freeze
+      IMMEDIATE_PLAN = %i[op_fetch op_immediate_read].freeze
+
+      # $10, $30, $50, $70, $90, $B0, $D0, $F0 - relative - 2+ cycles.
+      # A branch that is not taken takes 2 cycles. A taken branch takes 3,
+      # or 4 when the target is on another page.
+      BRANCH_PLAN = %i[op_fetch op_relative op_branch op_branch_fixup].freeze
+
+      # $4C - absolute - 3 cycles
+      JMP_ABSOLUTE_PLAN = %i[op_fetch op_abs_low op_jmp_high].freeze
+
+      # $6C - indirect - 5 cycles
+      JMP_INDIRECT_PLAN = %i[op_fetch op_abs_low op_abs_high op_indirect_low op_indirect_high].freeze
+
+      # $20 - absolute - 6 cycles
+      JSR_PLAN = %i[op_fetch op_jsr_low op_jsr_dummy op_jsr_push_high op_jsr_push_low op_jsr_high].freeze
+
+      # $60 - implied - 6 cycles
+      RTS_PLAN = %i[op_fetch op_implied_dummy op_pull_dummy op_pull_low op_pull_high op_rts_fixup].freeze
+
+      # $40 - implied - 6 cycles
+      RTI_PLAN = %i[op_fetch op_implied_dummy op_pull_dummy op_rti_pull_status op_pull_low op_rti_pull_high].freeze
+
+      # $08, $48 - implied - 3 cycles
+      PUSH_PLAN = %i[op_fetch op_implied_dummy op_push_exec].freeze
+
+      # $28, $68 - implied - 4 cycles
+      PULL_PLAN = %i[op_fetch op_implied_dummy op_pull_dummy op_pull_exec].freeze
+
+      # $02, $12, $22, $32, $42, $52, $62, $72, $92, $B2, $D2, $F2 - illegal
+      JAM_PLAN = [:op_fetch, :op_implied_dummy, *Array.new(JAM_ADDRESSES.length, :op_jam)].freeze
+
+      # A jammed CPU reads $FFFF on every cycle until reset. It never reaches
+      # an instruction boundary, so a pending IRQ or NMI never starts.
+      JAMMED_PLAN = %i[op_jammed].freeze
+
+      # BRK and hardware interrupts push the return address and status, then
+      # read the new PC from a vector. Only the second step differs: BRK's
+      # selects the IRQ vector and sets the break flag it pushes.
+      #
+      # $00 - implied - 7 cycles (BRK)
+      INTERRUPT_PLAN = %i[
+        op_fetch op_implied_dummy op_int_push_pch op_int_push_pcl op_int_push_status
+        op_int_vector_low op_int_vector_high
+      ].freeze
+      BRK_PLAN = %i[
+        op_fetch op_brk_dummy op_int_push_pch op_int_push_pcl op_int_push_status
+        op_int_vector_low op_int_vector_high
+      ].freeze
+
+      SPECIAL_PLANS = {
+        brk: BRK_PLAN, jam: JAM_PLAN, jsr: JSR_PLAN, rts: RTS_PLAN,
+        rti: RTI_PLAN, pha: PUSH_PLAN, php: PUSH_PLAN,
+        pla: PULL_PLAN, plp: PULL_PLAN
+      }.freeze
+
+      # Everything the CPU needs to run one opcode:
+      # - +operation+: the instruction method to call, such as :lda
+      # - +plan+: the step to run on each cycle
+      # - +writes+: which of those steps write to memory
+      # - +optional_dummy+: true for indexed reads, which skip the extra
+      #   cycle unless indexing crosses a page
+      Microcode = Struct.new(:operation, :plan, :writes, :optional_dummy) do
+        def self.table
+          Array.new(256) do |opcode|
+            instruction = Instruction.find(opcode)
+            raise InvalidOpcodeError, format("$%02x", opcode) unless instruction
+
+            build(instruction)
+          end.freeze
+        end
+
+        # The plan step that follows `cycles` cycles of the instruction, counting
+        # the opcode fetch as 1: one further on once an indexed read has
+        # skipped its dummy read, which it does when the index add didn't
+        # cross a page.
+        def index_at(cycles, crossed) = skips_dummy?(cycles, crossed) ? cycles + 1 : cycles
+
+        # The cycles run before plan step `index`, as index_at counts them.
+        def t_at(index, crossed) = skips_dummy?(index - 1, crossed) ? index - 1 : index
+
+        def skips_dummy?(cycles, crossed)
+          return false unless optional_dummy && !crossed
+
+          dummy = plan.index(:op_idx_dummy)
+          !dummy.nil? && cycles >= dummy
+        end
+
+        def self.write_mask(plan)
+          plan.map { |step| WRITE_STEPS.include?(step) }.freeze
+        end
+
+        def self.build(instruction)
+          plan = plan_for(instruction)
+          new(instruction.name, plan, write_mask(plan),
+              instruction.boundary_cycle?)
+        end
+
+        def self.plan_for(instruction)
+          case instruction.name
+          when :jmp
+            if instruction.addressing_mode == :indirect
+              JMP_INDIRECT_PLAN
+            else
+              JMP_ABSOLUTE_PLAN
+            end
+          when *BRANCHES then BRANCH_PLAN
+          else SPECIAL_PLANS[instruction.name] || addressed_plan(instruction)
+          end
+        end
+
+        def self.addressed_plan(instruction)
+          mode = instruction.addressing_mode
+          case mode
+          when :implied then IMPLIED_PLAN
+          when :accumulator then ACCUMULATOR_PLAN
+          when :immediate then IMMEDIATE_PLAN
+          else
+            [:op_fetch, *ADDRESSING_STEPS.fetch(mode),
+             *OPERATION_STEPS.fetch(operation_kind(instruction.name))].freeze
+          end
+        end
+
+        def self.operation_kind(name)
+          return :write if STORES.include?(name)
+          return :rmw if READ_MODIFY_WRITES.include?(name)
+
+          :read
+        end
+
+        private_class_method :build, :plan_for, :addressed_plan, :operation_kind
+      end
+
+      FETCH_WRITES = Microcode.write_mask(FETCH_PLAN)
+      INTERRUPT_WRITES = Microcode.write_mask(INTERRUPT_PLAN)
+      JAMMED_WRITES = Microcode.write_mask(JAMMED_PLAN)
+      MICROCODE = Microcode.table
+
+      # The instruction methods, in a fixed order a snapshot names them by.
+      OPERATIONS = MICROCODE.map(&:operation).uniq.freeze
+
+      # The plans a snapshot names that aren't an opcode's.
+      FETCH = -1
+      INTERRUPT = -2
+      JAMMED = -3
+    end
+  end
+end