badline 0.12.1 → 0.14.0

data/lib/badline/chips/z80/jumps.rb

@@ -0,0 +1,84 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # Jumps, calls and returns. Each leaves its target in WZ, and JP cc and
+      # CALL cc do whether they jump or not.
+      module Jumps
+        private
+
+        # The conditions bits 5-3 pick: NZ Z NC C PO PE P M.
+        def condition?(index)
+          case index
+          when 0 then @f.nobits?(ZF)
+          when 1 then @f.anybits?(ZF)
+          when 2 then @f.nobits?(CF)
+          when 3 then @f.anybits?(CF)
+          when 4 then @f.nobits?(PF)
+          when 5 then @f.anybits?(PF)
+          when 6 then @f.nobits?(SF)
+          else @f.anybits?(SF)
+          end
+        end
+
+        # NOP, EX AF,AF', DJNZ, JR and JR cc.
+        def relative_jump(row)
+          case row
+          when 0 then nil
+          when 1 then exchange_af
+          when 2 then decrement_and_jump
+          when 3 then jump_relative(fetch_byte)
+          else
+            offset = fetch_byte
+            jump_relative(offset) if condition?(row - 4)
+          end
+        end
+
+        def decrement_and_jump
+          @cycles += 1
+          offset = fetch_byte
+          @b = (@b - 1) & 0xff
+          jump_relative(offset) unless @b.zero?
+        end
+
+        def jump_relative(offset)
+          @cycles += 5
+          @pc = (@pc + offset - (offset > 127 ? 256 : 0)) & 0xffff
+          @wz = @pc
+        end
+
+        def jump(taken)
+          @wz = fetch_word
+          @pc = @wz if taken
+        end
+
+        def call(taken)
+          @wz = fetch_word
+          return unless taken
+
+          @cycles += 1
+          push(@pc)
+          @pc = @wz
+        end
+
+        def conditional_return(index)
+          @cycles += 1
+          return_from_call if condition?(index)
+        end
+
+        def return_from_call
+          @pc = pop
+          @wz = @pc
+        end
+
+        def restart(address)
+          @cycles += 1
+          push(@pc)
+          @pc = address
+          @wz = address
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/keyed_state.rb

@@ -0,0 +1,73 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # The Z80's fields in a keyed snapshot module (Snapshot::Keyed),
+      # between instructions, where it always is after the C128's cycle:
+      # the registers, the T-state count and the interrupt latches.
+      module KeyedState
+        def save_fields(out)
+          out.int("a", @a).int("f", @f).int("b", @b).int("c", @c).int("d", @d).int("e", @e).int("h", @h).int("l", @l)
+          out.int("af_alt", @af_alt).int("bc_alt", @bc_alt).int("de_alt", @de_alt).int("hl_alt", @hl_alt)
+          out.int("i", @i).int("r", @r).int("pc", @pc).int("sp", @sp).int("ix", @ix).int("iy", @iy).int("wz", @wz)
+          out.int("q", @q).int("last_q", @last_q).int("im", @im).int("cycles", @cycles)
+          out.bool("iff1", @iff1).bool("iff2", @iff2).bool("halted", @halted).bool("after_ei", @after_ei)
+          out.bool("after_ld_a_ir", @after_ld_a_ir).bool("int", @int).bool("nmi", @nmi)
+          out.bool("nmi_pending", @nmi_pending)
+        end
+
+        def load_fields(input)
+          load_main_fields(input)
+          load_special_fields(input)
+          @cycles = input.int("cycles", @cycles)
+          load_latch_fields(input)
+          @prefix = 0
+        end
+
+        def restored! = nil
+
+        private
+
+        def load_main_fields(input)
+          @a = input.byte("a", @a)
+          @f = input.byte("f", @f)
+          @b = input.byte("b", @b)
+          @c = input.byte("c", @c)
+          @d = input.byte("d", @d)
+          @e = input.byte("e", @e)
+          @h = input.byte("h", @h)
+          @l = input.byte("l", @l)
+          @af_alt = input.word("af_alt", @af_alt)
+          @bc_alt = input.word("bc_alt", @bc_alt)
+          @de_alt = input.word("de_alt", @de_alt)
+          @hl_alt = input.word("hl_alt", @hl_alt)
+        end
+
+        def load_special_fields(input)
+          @i = input.byte("i", @i)
+          @r = input.byte("r", @r)
+          @pc = input.word("pc", @pc)
+          @sp = input.word("sp", @sp)
+          @ix = input.word("ix", @ix)
+          @iy = input.word("iy", @iy)
+          @wz = input.word("wz", @wz)
+          @q = input.byte("q", @q)
+          @last_q = input.byte("last_q", @last_q)
+          @im = input.int("im", @im)
+        end
+
+        def load_latch_fields(input)
+          @iff1 = input.bool("iff1", @iff1)
+          @iff2 = input.bool("iff2", @iff2)
+          @halted = input.bool("halted", @halted)
+          @after_ei = input.bool("after_ei", @after_ei)
+          @after_ld_a_ir = input.bool("after_ld_a_ir", @after_ld_a_ir)
+          @int = input.bool("int", @int)
+          @nmi = input.bool("nmi", @nmi)
+          @nmi_pending = input.bool("nmi_pending", @nmi_pending)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/loads.rb

@@ -0,0 +1,100 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # Loads, PUSH, and IN and OUT through a port A and n address. The loads
+      # through a pointer leave the address after it in WZ, or for a store of
+      # A, A and the low byte of that address.
+      module Loads
+        private
+
+        # LD r,r' with (HL) as index 6.
+        def load_register(target, source)
+          if source == 6
+            set_plain_register(target, read_byte(operand_address))
+          elsif target == 6
+            write_byte(operand_address, plain_register(source))
+          else
+            set_register(target, register(source))
+          end
+        end
+
+        # LD r,n, and LD (IX+d),n, which reads n while it adds d.
+        def load_immediate(index)
+          return set_register(index, fetch_byte) unless index == 6
+          return write_byte(hl, fetch_byte) if @prefix.zero?
+
+          displaced
+          value = fetch_byte
+          @cycles += 2
+          write_byte(@wz, value)
+        end
+
+        def indirect_load(row)
+          case row
+          when 0 then store_a(bc)
+          when 1 then load_a(bc)
+          when 2 then store_a(de)
+          when 3 then load_a(de)
+          when 4 then store_word(hl_or_index)
+          when 5 then self.hl_or_index = load_word
+          when 6 then store_a(fetch_word)
+          else load_a(fetch_word)
+          end
+        end
+
+        def load_a(address)
+          @a = read_byte(address)
+          @wz = (address + 1) & 0xffff
+        end
+
+        def store_a(address)
+          write_byte(address, @a)
+          @wz = (@a << 8) | ((address + 1) & 0xff)
+        end
+
+        def store_word(value)
+          address = fetch_word
+          write_word(address, value)
+          @wz = (address + 1) & 0xffff
+        end
+
+        def load_word
+          address = fetch_word
+          @wz = (address + 1) & 0xffff
+          read_word(address)
+        end
+
+        def push_pair(index)
+          @cycles += 1
+          push(stack_pair(index))
+        end
+
+        # RET, EXX, JP (HL) and LD SP,HL.
+        def stack_and_exchange(index)
+          case index
+          when 0 then return_from_call
+          when 1 then exchange_alternates
+          when 2 then @pc = hl_or_index
+          else
+            @cycles += 2
+            @sp = hl_or_index
+          end
+        end
+
+        def output_immediate
+          port = (@a << 8) | fetch_byte
+          output(port, @a)
+          @wz = (port & 0xff00) | ((port + 1) & 0xff)
+        end
+
+        def input_immediate
+          port = (@a << 8) | fetch_byte
+          @wz = (port + 1) & 0xffff
+          @a = input(port)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/main_page.rb

@@ -0,0 +1,136 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # The unprefixed opcodes, which DD and FD reuse with IX or IY for HL.
+      # An opcode splits into its quarter (bits 7-6), its row (5-3) and its
+      # column (2-0), and each quarter of the page is regular in rows and
+      # columns.
+      module MainPage
+        private
+
+        def execute(opcode)
+          case opcode >> 6
+          when 0 then execute_low(opcode)
+          when 1 then opcode == 0x76 ? @halted = true : load_register((opcode >> 3) & 7, opcode & 7)
+          when 2 then alu((opcode >> 3) & 7, operand(opcode & 7))
+          else execute_high(opcode)
+          end
+        end
+
+        def execute_low(opcode)
+          row = (opcode >> 3) & 7
+          case opcode & 7
+          when 0 then relative_jump(row)
+          when 1 then opcode.nobits?(8) ? set_pair(row >> 1, fetch_word) : add_pair(row >> 1)
+          when 2 then indirect_load(row)
+          when 3 then step_pair(row)
+          when 4 then modify(row, true)
+          when 5 then modify(row, false)
+          when 6 then load_immediate(row)
+          else accumulator_operation(row)
+          end
+        end
+
+        def execute_high(opcode)
+          row = (opcode >> 3) & 7
+          case opcode & 7
+          when 0 then conditional_return(row)
+          when 1 then opcode.nobits?(8) ? set_stack_pair(row >> 1, pop) : stack_and_exchange(row >> 1)
+          when 2 then jump(condition?(row))
+          when 3 then miscellaneous(row)
+          when 4 then call(condition?(row))
+          when 5 then opcode.nobits?(8) ? push_pair(row >> 1) : call_or_prefix(row >> 1)
+          when 6 then alu(row, fetch_byte)
+          else restart(row << 3)
+          end
+        end
+
+        # The operand of the 8-bit ALU opcodes: a register or (HL).
+        def operand(index)
+          index == 6 ? read_byte(operand_address) : register(index)
+        end
+
+        # INC and DEC on a register or (HL).
+        def modify(index, increase)
+          if index == 6
+            address = operand_address
+            value = read_byte(address)
+            @cycles += 1
+            write_byte(address, increase ? increment(value) : decrement(value))
+          else
+            set_register(index, increase ? increment(register(index)) : decrement(register(index)))
+          end
+        end
+
+        # INC and DEC on a pair, which touch no flags.
+        def step_pair(row)
+          @cycles += 2
+          index = row >> 1
+          set_pair(index, (pair(index) + (row.nobits?(1) ? 1 : -1)) & 0xffff)
+        end
+
+        def add_pair(index)
+          self.hl_or_index = add16(hl_or_index, pair(index))
+          @cycles += 7
+        end
+
+        def accumulator_operation(row)
+          case row
+          when 0, 1, 2, 3 then rotate_a(row)
+          when 4 then daa
+          when 5 then complement
+          when 6 then assign_flags((@f & (SF | ZF | PF)) | CF | (((@last_q ^ @f) | @a) & XYF))
+          else assign_flags((@f & (SF | ZF | PF)) | ((@f & CF) << 4) | ((@f & CF) ^ CF) | (((@last_q ^ @f) | @a) & XYF))
+          end
+        end
+
+        def complement
+          @a ^= 0xff
+          assign_flags((@f & (SF | ZF | PF | CF)) | HF | NF | (@a & XYF))
+        end
+
+        def miscellaneous(row)
+          case row
+          when 0 then jump(true)
+          when 1 then @prefix.zero? ? execute_bits(fetch_opcode) : execute_index_bits
+          when 2 then output_immediate
+          when 3 then input_immediate
+          when 4 then exchange_stack_top
+          when 5 then exchange_de_hl
+          when 6 then @iff1 = @iff2 = false
+          else enable_interrupts
+          end
+        end
+
+        def call_or_prefix(index)
+          case index
+          when 0 then call(true)
+          when 1 then index_prefix(1)
+          when 2 then extended_prefix
+          else index_prefix(2)
+          end
+        end
+
+        # DD and FD: the next opcode runs with IX or IY for HL. A prefix
+        # after a prefix replaces it.
+        def index_prefix(prefix)
+          @prefix = prefix
+          @last_q = 0
+          execute(fetch_opcode)
+        end
+
+        def extended_prefix
+          @prefix = 0
+          execute_extended(fetch_opcode)
+        end
+
+        def enable_interrupts
+          @iff1 = @iff2 = true
+          @after_ei = true
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/registers.rb

@@ -0,0 +1,122 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # The register file. Opcodes name 8-bit registers by a 3-bit index,
+      # B C D E H L (HL) A, and pairs by a 2-bit one, BC DE HL SP, or BC DE
+      # HL AF for PUSH and POP. After a DD or FD prefix, HL means IX or IY
+      # and H and L their halves, except beside an (IX+d) operand.
+      module Registers
+        attr_accessor :a, :f, :b, :c, :d, :e, :h, :l, :i, :r, :pc, :sp, :ix, :iy, :wz, :im, :q,
+                      :af_alt, :bc_alt, :de_alt, :hl_alt, :iff1, :iff2, :halted, :after_ei, :after_ld_a_ir
+
+        def af = (@a << 8) | @f
+        def bc = (@b << 8) | @c
+        def de = (@d << 8) | @e
+        def hl = (@h << 8) | @l
+
+        def af=(value)
+          @a = value >> 8
+          @f = value & 0xff
+        end
+
+        def bc=(value)
+          @b = value >> 8
+          @c = value & 0xff
+        end
+
+        def de=(value)
+          @d = value >> 8
+          @e = value & 0xff
+        end
+
+        def hl=(value)
+          @h = value >> 8
+          @l = value & 0xff
+        end
+
+        private
+
+        def register(index)
+          case index
+          when 0 then @b
+          when 1 then @c
+          when 2 then @d
+          when 3 then @e
+          when 4 then @prefix.zero? ? @h : index_register >> 8
+          when 5 then @prefix.zero? ? @l : index_register & 0xff
+          else @a
+          end
+        end
+
+        def set_register(index, value)
+          case index
+          when 0 then @b = value
+          when 1 then @c = value
+          when 2 then @d = value
+          when 3 then @e = value
+          when 4 then @prefix.zero? ? @h = value : self.index_register = (index_register & 0xff) | (value << 8)
+          when 5 then @prefix.zero? ? @l = value : self.index_register = (index_register & 0xff00) | value
+          else @a = value
+          end
+        end
+
+        # The register an (HL) or (IX+d) operand sits beside: H and L are
+        # always themselves.
+        def plain_register(index)
+          case index
+          when 4 then @h
+          when 5 then @l
+          else register(index)
+          end
+        end
+
+        def set_plain_register(index, value)
+          case index
+          when 4 then @h = value
+          when 5 then @l = value
+          else set_register(index, value)
+          end
+        end
+
+        def pair(index)
+          case index
+          when 0 then bc
+          when 1 then de
+          when 2 then hl_or_index
+          else @sp
+          end
+        end
+
+        def set_pair(index, value)
+          case index
+          when 0 then self.bc = value
+          when 1 then self.de = value
+          when 2 then self.hl_or_index = value
+          else @sp = value
+          end
+        end
+
+        # The pairs PUSH and POP name, with AF in place of SP.
+        def stack_pair(index) = index == 3 ? af : pair(index)
+
+        def set_stack_pair(index, value)
+          index == 3 ? self.af = value : set_pair(index, value)
+        end
+
+        def hl_or_index = @prefix.zero? ? hl : index_register
+
+        def hl_or_index=(value)
+          @prefix.zero? ? self.hl = value : self.index_register = value
+        end
+
+        def index_register = @prefix == 1 ? @ix : @iy
+
+        def index_register=(value)
+          @prefix == 1 ? @ix = value : @iy = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80/shifts.rb

@@ -0,0 +1,66 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class Z80
+      # Rotates, shifts and the bit operations.
+      module Shifts
+        private
+
+        # RLCA RRCA RLA RRA, which leave S, Z and P/V alone.
+        def rotate_a(operation)
+          carry = operation.even? ? @a >> 7 : @a & 1
+          @a = shifted(operation, @a, carry)
+          assign_flags((@f & (SF | ZF | PF)) | (@a & XYF) | carry)
+        end
+
+        # The CB page's rotates and shifts by bits 5-3: RLC RRC RL RR SLA SRA
+        # SLL SRL. SLL shifts a 1 in.
+        def shift(operation, value)
+          carry = operation.even? ? value >> 7 : value & 1
+          result = shifted(operation, value, carry)
+          assign_flags(SZ53P[result] | carry)
+          result
+        end
+
+        def shifted(operation, value, carry)
+          case operation
+          when 0 then ((value << 1) | carry) & 0xff
+          when 1 then (value >> 1) | (carry << 7)
+          when 2 then ((value << 1) | (@f & CF)) & 0xff
+          when 3 then (value >> 1) | ((@f & CF) << 7)
+          when 4 then (value << 1) & 0xff
+          when 5 then (value >> 1) | (value & 0x80)
+          when 6 then ((value << 1) | 1) & 0xff
+          else value >> 1
+          end
+        end
+
+        # BIT n tests a bit of +value+ and copies bits 5 and 3 from +source+:
+        # the operand for a register, WZ's high byte for a memory operand.
+        def bit(number, value, source)
+          tested = value & (1 << number)
+          flags = (@f & CF) | HF | (source & XYF) | (tested & SF)
+          flags |= ZF | PF if tested.zero?
+          assign_flags(flags)
+        end
+
+        # RRD and RLD rotate a digit through A and (HL).
+        def rotate_digits(left)
+          address = hl
+          value = read_byte(address)
+          @cycles += 4
+          if left
+            write_byte(address, ((value << 4) | (@a & 0x0f)) & 0xff)
+            @a = (@a & 0xf0) | (value >> 4)
+          else
+            write_byte(address, ((@a << 4) | (value >> 4)) & 0xff)
+            @a = (@a & 0xf0) | (value & 0x0f)
+          end
+          @wz = (address + 1) & 0xffff
+          assign_flags((@f & CF) | SZ53P[@a])
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/z80.rb

@@ -0,0 +1,13 @@
+# frozen_string_literal: true
+
+require "badline/chips/z80/core"
+
+module Badline
+  module Chips
+    # The Zilog Z80 (NMOS), which the C128 has beside its 8502. It is not
+    # part of badline/core, so a machine that has one requires it.
+    class Z80
+      include Core
+    end
+  end
+end

data/lib/badline/chips.rb

@@ -0,0 +1,10 @@
+# frozen_string_literal: true
+
+# The chips badline/core's machines share. The C128's own, the Z80 and the
+# VDC, stay out of the core: badline/c128 requires them.
+require "badline/chips/cpu"
+require "badline/chips/cia"
+require "badline/chips/via"
+require "badline/chips/sid"
+require "badline/chips/vic"
+require "badline/chips/vic_i"

data/lib/badline/core.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 # The emulator core: the machine, its chips, media and traps, and the
-# snapshot state Computer saves and restores with, without the options,
+# snapshot state C64 saves and restores with, without the options,
 # the rest of the snapshot code, audio or front end. lib/badline.rb and
 # the Spinel harnesses in spinel/ load it, so a file the core needs is
 # added here.
@@ -12,42 +12,23 @@ require "badline/timing"
 require "badline/model"
 require "badline/addressable"
 require "badline/memory"
-require "badline/color_memory"
+require "badline/c64/color_memory"
 require "badline/rom"
-require "badline/ram_expansion"
-require "badline/cpu_port"
-require "badline/address_bus"
-require "badline/instruction"
-require "badline/instruction_set"
+require "badline/c64/banked_ram"
 require "badline/status"
-require "badline/keyboard"
-require "badline/joystick"
-require "badline/control_ports"
 require "badline/input"
-require "badline/datasette"
-require "badline/time_of_day"
-require "badline/cia"
-require "badline/via"
-require "badline/sid"
-require "badline/debug_register"
-require "badline/reu"
-require "badline/interrupts"
-require "badline/traps"
-require "badline/cpu"
-require "badline/vic"
-require "badline/keyboard_buffer"
-require "badline/iec_bus"
-require "badline/drive1541"
-require "badline/drive1581"
-require "badline/drive1581/slot"
-require "badline/snapshot/state"
-require "badline/snapshot/setup"
+require "badline/chips"
+require "badline/drives"
+require "badline/c64/bus"
+require "badline/c64/reu"
+require "badline/snapshot/keyed"
+require "badline/snapshot/c64_setup"
+require "badline/snapshot/storage_setup"
 require "badline/machine"
-require "badline/computer"
+require "badline/c64"
 require "badline/vic20"
-require "badline/checkpoint"
 require "badline/storage"
-require "badline/cartridge"
+require "badline/sid_tune"
+require "badline/c64/cartridge"
 require "badline/kernal_trap"
-require "badline/chrout_trap"
 require "badline/media"