badline 0.12.1 → 0.14.0

data/lib/badline/cia/interrupt_register.rb

@@ -1,143 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CIA
-    # The interrupt control register: the source flags, their mask and the
-    # IR bit that drives the interrupt line, with the 6526's acknowledge
-    # timing.
-    class InterruptRegister
-      attr_reader :status, :mask, :quiet
-
-      # The 6526A is the faster of the two: see the rules below.
-      def initialize(model = :mos6526)
-        @fast = model == :mos6526a
-        @mask = InterruptFlags.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, 0])
-        @status = InterruptFlags.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, :interrupt])
-        @pending = 0
-        @read = @read_last_cycle = @read_two_cycles_ago = nil
-        @timer_b_bug = false
-        @quiet = true
-      end
-
-      # The CIA skips this while quiet: no read is recent enough to matter
-      # and no assert is due.
-      def cycle!
-        @read_two_cycles_ago = @read_last_cycle
-        @read_last_cycle = @read
-        @read = nil
-        if @pending.positive?
-          @pending -= 1
-          status.interrupt = true if @pending.zero?
-        end
-        @quiet = @pending.zero? && @read_last_cycle.nil? && @read_two_cycles_ago.nil?
-      end
-
-      def interrupted? = status.value >= 0x80
-
-      def save_state(out)
-        out.int(@mask.value).int(@status.value).int(@pending)
-        [@read, @read_last_cycle, @read_two_cycles_ago].each { |read| out.optional_int(read) }
-        out.boolean(@timer_b_bug).boolean(@quiet)
-      end
-
-      def load_state(input)
-        @mask.value = input.int
-        @status.value = input.int
-        @pending = input.int
-        @read = input.optional_int
-        @read_last_cycle = input.optional_int
-        @read_two_cycles_ago = input.optional_int
-        @timer_b_bug = input.boolean?
-        @quiet = input.boolean?
-      end
-
-      # Raises IR on this cycle.
-      def assert_now
-        status.interrupt = true
-        @pending = 0
-      end
-
-      # Schedules IR to rise after delay cycles, keeping an earlier one.
-      def assert!(delay = 1)
-        @pending = @pending.positive? ? [@pending, delay].min : delay
-        @quiet = false
-      end
-
-      # Latch a source, pulling the interrupt line if it is armed. The 6526
-      # raises IR a cycle after the flag. The 6526A raises it on the flag's
-      # own cycle, unless the ICR was read on the cycle before.
-      def flag(source)
-        bit = source_bit(source)
-        @status.value |= bit
-        return unless mask.value.anybits?(bit)
-
-        @fast && @read_last_cycle.nil? ? assert_now : assert!
-      end
-
-      # The 6526 timer B bug: an underflow on the cycle after a read still
-      # raises the flag, but the next read drops it unseen. The 6526A has
-      # no such bug.
-      def timer_b_underflow!
-        @timer_b_bug = !@fast && !@read_last_cycle.nil?
-        flag(:timer_b)
-      end
-
-      # A read releases the interrupt line at once, and cancels an assert
-      # due on the next cycle, but its acknowledge lands a cycle late. On
-      # the 6526 that holds only IR: the next cycle still reads IR set if it
-      # was set, or about to be. The 6526A reads an IR about to rise as set
-      # at once, and holds every bit it read: the next cycle reads them all
-      # again, along with anything flagged since.
-      def read
-        status.timer_b = false if @timer_b_bug
-        @timer_b_bug = false
-        value = status.value
-        value |= 0x80 if @fast && @pending == 1
-        @read = @pending == 1 ? value | 0x80 : value
-        @quiet = false
-        value |= held(@read_last_cycle) if @read_last_cycle
-        status.value = 0x0
-        @pending = 0
-        value
-      end
-
-      # Bit 7 picks between setting and clearing the mask bits given.
-      def write(value)
-        if value.nobits?(0x80)
-          @mask.value &= ~(value & 0x1f)
-        else
-          @mask.value |= (value & 0x1f)
-        end
-        if mask.value.anybits?(status.value & 0x1f)
-          assert!(arm_delay) unless interrupted?
-        elsif @pending == 1 && @read_two_cycles_ago
-          # On the 6526, masking the pending source cancels the assert due
-          # on the next cycle only while a read two cycles back is
-          # acknowledging.
-          @pending = 0
-        end
-      end
-
-      private
-
-      # Arming a pending source raises IR two cycles later on the 6526,
-      # and one cycle later on the 6526A.
-      def arm_delay = @fast ? 1 : 2
-
-      # What a read on the cycle before still holds: IR on the 6526, and
-      # every bit it read on the 6526A.
-      def held(last) = @fast ? last : last & 0x80
-
-      def source_bit(source)
-        case source
-        when :timer_a then 0x01
-        when :timer_b then 0x02
-        when :alarm then 0x04
-        when :serial then 0x08
-        when :flag then 0x10
-        else raise ArgumentError, "unknown interrupt source #{source}"
-        end
-      end
-    end
-  end
-end

data/lib/badline/cia/serial.rb

@@ -1,275 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CIA
-    # The serial shift register and the CNT line that clocks it.
-    #
-    # With CRA bit 6 clear the port is an input: SP is sampled on every
-    # rising CNT edge, and the byte reaches the data register after eight of
-    # them. With the bit set the CIA drives CNT itself, toggling it on every
-    # timer A underflow, so a byte takes sixteen underflows to go out. CNT falls
-    # as each bit is put on SP, and rises again to clock it in.
-    #
-    # The register counts itself empty as soon as the eighth bit is on SP,
-    # fifteen underflows in: the serial flag follows a few cycles later
-    # rather than waiting for the sixteenth underflow, and a byte written
-    # from that point on goes out on the next one.
-    class Serial
-      BITS = 8
-
-      # A byte written to the data register reaches the shift register one
-      # cycle later. The empty countdown starts on the underflow that puts
-      # the eighth bit on SP and is decremented on that same cycle, so the
-      # flag lands four cycles after it.
-      LOAD_DELAY = 1
-      EMPTY_DELAY = 5
-      BUSY_DELAY = 5
-
-      # The logic watching the shift register runs a few cycles behind it,
-      # so the level saying a bit is still on its way out is scheduled
-      # through a delay line: a bit set at position 7 - n takes effect n
-      # cycles later. Putting a bit on SP raises the level after one cycle
-      # and drops it again after two before raising it for good after
-      # three; the eighth bit skips straight to the last of those. CNT
-      # rising over a bit lowers the level four cycles later.
-      IN_FLIGHT = 0x50
-      LAST_IN_FLIGHT = 0x10
-      BOUNCE = 0x20
-      SETTLED = 0x08
-
-      attr_reader :data, :sp_out, :cnt, :cnt_in, :idle
-      attr_accessor :sp_in
-
-      def initialize(control)
-        @control = control
-        @data = 0x0
-        @shift = 0x0
-        @steps = 0
-        @empty_in = nil
-        @busy_in = nil
-        @busy = false
-        @abandoned = false
-        @pending = nil
-        @underflow_high = false
-        @in_flight = false
-        @flight_up = 0x0
-        @flight_down = 0x0
-        @idle = true
-        # Nothing drives the user port, so both lines float high.
-        @cnt = true
-        @cnt_in = true
-        @sp_in = true
-        @sp_out = true
-      end
-
-      # The bits shifted so far, and the byte waiting to go out after the
-      # one shifting.
-      attr_reader :steps, :pending
-
-      def shift_register = @shift
-
-      # Sets the data register and the shift register, as a VICE snapshot
-      # gives them.
-      def restore_shift(data, shift)
-        @data = data
-        @shift = shift
-      end
-
-      def output?
-        @control.serial_mode?
-      end
-
-      # Whether nothing is counting down or in the delay lines, so only
-      # timer A's underflows reach the register.
-      def drained? = idle?
-
-      # Takes timer A's underflow line as cycle! would have left it, with
-      # +underflowed+ its level on the last cycle, for a CIA run without
-      # the register in use (CIA#fast_forward).
-      def follow_underflow(underflowed)
-        @underflow_high = underflowed
-        @idle = !underflowed
-      end
-
-      def cnt_in=(level)
-        @cnt_in = level
-        @cnt = level unless output?
-      end
-
-      def save_state(out)
-        out.int(@data).int(@shift).int(@steps).optional_int(@empty_in).optional_int(@busy_in)
-        out.boolean(@busy).boolean(@abandoned).optional_int(@pending).boolean(@underflow_high).boolean(@in_flight)
-        out.int(@flight_up).int(@flight_down).boolean(@idle)
-        [@cnt, @cnt_in, @sp_in, @sp_out].each { |level| out.boolean(level) }
-      end
-
-      def load_state(input)
-        @data = input.int
-        @shift = input.int
-        @steps = input.int
-        @empty_in = input.optional_int
-        @busy_in = input.optional_int
-        @busy = input.boolean?
-        @abandoned = input.boolean?
-        @pending = input.optional_int
-        load_lines(input)
-      end
-
-      def write(value)
-        @data = value
-        @pending = LOAD_DELAY
-        @idle = false
-      end
-
-      # Clocked every cycle with timer A's underflow line. Yields once the
-      # shift register reports itself empty, which it does without waiting
-      # for the underflow that raises CNT over the eighth bit.
-      def cycle!(underflowed)
-        return if @idle && !underflowed
-
-        shift(underflowed)
-        @pending -= 1 if @pending&.positive?
-        drain_flight
-        count_busy
-        @idle = !underflowed && idle?
-        return if @empty_in.nil?
-
-        @empty_in -= 1
-        return unless @empty_in.zero?
-
-        @empty_in = nil
-        @busy = false
-        yield
-      end
-
-      # Clocked by rising CNT edges while receiving. Yields once a whole
-      # byte has arrived.
-      def rising_edge!
-        return if output?
-
-        @shift = ((@shift << 1) | (@sp_in ? 1 : 0)) & 0xff
-        @steps += 1
-        return unless @steps == BITS
-
-        @steps = 0
-        @data = @shift
-        yield if block_given?
-      end
-
-      # A mode change drops the byte in flight and hands CNT back to
-      # whichever side drives it now, and yields: that byte counts as gone.
-      # Handing the port over as an input tears a transmission down, so a
-      # busy register reports it; the same change latches how far the bit
-      # in flight had got, and taking the port back reports that.
-      def reset!
-        abandoned = output? ? @abandoned : @busy
-        @abandoned = output? ? false : @in_flight
-        @in_flight = false
-        @steps = 0
-        @empty_in = nil
-        @busy_in = nil
-        @busy = false
-        @pending = nil
-        @cnt = output? || @cnt_in
-        yield if abandoned
-      end
-
-      private
-
-      def load_lines(input)
-        @underflow_high = input.boolean?
-        @in_flight = input.boolean?
-        @flight_up = input.int
-        @flight_down = input.int
-        @idle = input.boolean?
-        @cnt = input.boolean?
-        @cnt_in = input.boolean?
-        @sp_in = input.boolean?
-        @sp_out = input.boolean?
-      end
-
-      # Without an underflow, a register with nothing counting down and
-      # nothing in the delay lines has nothing to do on a cycle.
-      def idle?
-        !@pending&.positive? && (@flight_up | @flight_down).zero? &&
-          @busy_in.nil? && @empty_in.nil?
-      end
-
-      # The shift register picks up a waiting byte whenever the underflow
-      # line is asserted, but every half-step after that needs a fresh edge
-      # on it. A zero latch holds the line down for good rather than
-      # pulsing it, so such a byte stops after its first bit and never
-      # reaches the data register.
-      def shift(underflowed)
-        edge = underflowed && !@underflow_high
-        @underflow_high = underflowed
-        clock(edge) if underflowed && output?
-      end
-
-      def clock(edge)
-        start if @steps <= 1
-        if @steps.zero?
-          @flight_down |= SETTLED
-        elsif edge || @steps == BITS * 2
-          half_step
-        end
-      end
-
-      def half_step
-        @steps -= 1
-        @cnt = @steps.even?
-        if @cnt
-          @flight_down |= SETTLED
-        else
-          shift_out
-        end
-      end
-
-      # The register reads as busy from a few cycles after the first bit
-      # reaches SP until it reports itself empty over the eighth.
-      def mark_busy
-        case @steps
-        when (BITS * 2) - 1 then @busy_in = BUSY_DELAY
-        when 1
-          @empty_in = EMPTY_DELAY
-          @busy_in = nil
-        end
-      end
-
-      def count_busy
-        return if @busy_in.nil?
-
-        @busy_in -= 1
-        return unless @busy_in.zero?
-
-        @busy_in = nil
-        @busy = true
-      end
-
-      def drain_flight
-        @in_flight = false if @flight_down.anybits?(0x80)
-        @flight_down = (@flight_down << 1) & 0xff
-        @in_flight = true if @flight_up.anybits?(0x80)
-        @flight_up = (@flight_up << 1) & 0xff
-      end
-
-      # A byte only moves out of the data register once the one before it
-      # has put its last bit on SP.
-      def start
-        return unless @pending&.zero?
-
-        @pending = nil
-        @shift = @data
-        @steps = BITS * 2
-      end
-
-      def shift_out
-        @sp_out = @shift.anybits?(0x80)
-        @shift = (@shift << 1) & 0xff
-        mark_busy
-        @flight_up |= @steps == 1 ? LAST_IN_FLIGHT : IN_FLIGHT
-        @flight_down |= BOUNCE
-      end
-    end
-  end
-end

data/lib/badline/cia/state.rb

@@ -1,47 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CIA
-    # A snapshot of the chip: everything it holds but its wiring, the ports,
-    # the PB4 and CNT levels, the timers, the interrupt register, the serial
-    # port and the TOD clock.
-    module State
-      def save_state(out)
-        out.marker("CIA")
-        out.int(@data_port_a).int(@data_port_b).int(@data_dir_a).int(@data_dir_b)
-        out.boolean(@port_b4_high).boolean(@port_b4_driven_high).boolean(@cnt_high).boolean(@cnt_rise)
-        out.int(@control_a.value).int(@control_b.value)
-        @ta.save_state(out)
-        @tb.save_state(out)
-        @icr.save_state(out)
-        @serial.save_state(out)
-        @tod.save_state(out)
-      end
-
-      def load_state(input)
-        input.marker("CIA")
-        @data_port_a = input.int
-        @data_port_b = input.int
-        @data_dir_a = input.int
-        @data_dir_b = input.int
-        @port_b4_high = input.boolean?
-        @port_b4_driven_high = input.boolean?
-        @cnt_high = input.boolean?
-        @cnt_rise = input.boolean?
-        @control_a.value = input.int
-        @control_b.value = input.int
-        load_parts(input)
-      end
-
-      private
-
-      def load_parts(input)
-        @ta.load_state(input)
-        @tb.load_state(input)
-        @icr.load_state(input)
-        @serial.load_state(input)
-        @tod.load_state(input)
-      end
-    end
-  end
-end

data/lib/badline/cia/timer.rb

@@ -1,206 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CIA
-    class Timer
-      attr_accessor :counter, :latch
-      attr_reader :control, :underflowed
-
-      def initialize(control)
-        @control = control
-        @counter = @latch = 0xffff
-        @pipe = 0
-        @load_delay = 0
-        @reload = false
-        @underflowed = false
-        @oneshot_linger = 0
-        @toggle = true
-        settle
-      end
-
-      # The level this timer drives on its port B pin: a square wave that
-      # flips on each underflow, or a single high tick when one happens.
-      def output?
-        control.out_mode? ? @toggle : @underflowed
-      end
-
-      # Whether the timer is stopped with nothing in its pipeline, so a
-      # cycle changes nothing.
-      def idle? = @empty && !started?
-
-      # Whether the timer counts ø2 in continuous mode with nothing pending
-      # but the reload after an underflow, so fast_forward can run it. A
-      # latch below 2 is left out.
-      def free_running?
-        started? && !@control.run_mode? && @control.value.nobits?(0x20) && @latch >= 2 && @pipe == 0b11 &&
-          (@load_delay | @oneshot_linger).zero? && (@settled || @reload)
-      end
-
-      # Runs a free-running timer +cycles+ cycles at once, as cycle! would:
-      # an underflow every latch + 1 cycles, each one followed by the
-      # reload. Returns the underflows.
-      def fast_forward(cycles)
-        return 0 if cycles.zero?
-        return after_underflow(cycles, 0) unless @settled
-
-        if cycles < @counter
-          @counter -= cycles
-          return 0
-        end
-        after_underflow(cycles - @counter, 1)
-      end
-
-      def cycle!(feed)
-        feed &&= @control.value & 0x01 != 0
-        if @settled
-          return @counter -= 1 if feed && @counter > 1
-        elsif @empty
-          enter if feed
-          return
-        end
-        run_tick(feed)
-      end
-
-      def run_tick(feed)
-        @underflowed = false
-        @oneshot_linger -= 1 if @oneshot_linger.positive?
-        tick(feed)
-        settle
-      end
-
-      # The counter, the latch and the pipeline between them. The control
-      # register is the CIA's to save.
-      def save_state(out)
-        out.int(@counter).int(@latch).int(@pipe).int(@load_delay).boolean(@reload).boolean(@underflowed)
-        out.int(@oneshot_linger).boolean(@toggle).boolean(@settled).boolean(@empty)
-      end
-
-      def load_state(input)
-        @counter = input.int
-        @latch = input.int
-        @pipe = input.int
-        @load_delay = input.int
-        @reload = input.boolean?
-        @underflowed = input.boolean?
-        @oneshot_linger = input.int
-        @toggle = input.boolean?
-        @settled = input.boolean?
-        @empty = input.boolean?
-      end
-
-      def write_control(value)
-        @toggle = true if value.anybits?(0x01) && !started?
-        @oneshot_linger = 2 if control.run_mode? && value.nobits?(0x08)
-        control.value = value & ~0x10
-        @load_delay = 3 if value.anybits?(0x10)
-        settle
-      end
-
-      def write_latch_low(value)
-        @latch = (@latch & 0xff00) | value
-      end
-
-      def write_latch_high(value)
-        @latch = (value << 8) | (@latch & 0xff)
-        @counter = @latch unless started?
-      end
-
-      # Whether the timer's PB output toggle is high, and its count pipeline
-      # as two bits, the newer stage high.
-      attr_reader :toggle, :pipe
-
-      # Sets the control register without its load strobe, the toggle and
-      # the count pipeline, as a VICE snapshot gives them.
-      def restore_pipeline(control, toggle, pipe)
-        @control.value = control & ~0x10
-        @toggle = toggle
-        @pipe = pipe
-        settle
-      end
-
-      private
-
-      def started?
-        @control.value & 0x01 != 0
-      end
-
-      # Where fast_forward lands +cycles+ after an underflow, with
-      # +underflows+ underflows counted so far.
-      def after_underflow(cycles, underflows)
-        periods, rest = cycles.divmod(@latch + 1)
-        underflows += periods
-        @toggle = !@toggle if underflows.odd?
-        @underflowed = rest.zero?
-        @reload = rest.zero?
-        @counter = @latch - (rest.zero? ? 0 : rest - 1)
-        settle
-        underflows
-      end
-
-      def enter
-        @pipe = 0b10
-        @empty = false
-      end
-
-      # With no load, reload or one-shot linger pending, a full pipe only
-      # counts and an empty one only waits to be fed.
-      def settle
-        quiet = (@load_delay | @oneshot_linger).zero? && !@reload
-        @settled = quiet && @pipe == 0b11
-        @empty = quiet && @pipe.zero?
-      end
-
-      def tick(feed)
-        counting = @pipe.anybits?(0b01)
-        @pipe = (@pipe >> 1) | (feed ? 0b10 : 0)
-        loading = @reload || @load_delay == 1
-        @reload = false
-
-        if loading
-          reload
-        elsif premature_underflow?
-          underflow
-        elsif counting
-          count
-        end
-
-        forced_load
-      end
-
-      def forced_load
-        return unless @load_delay.positive?
-
-        @load_delay -= 1
-        @counter = @latch if @load_delay == 1
-      end
-
-      # the final pipeline stage, before any pending load lands
-      def premature_underflow?
-        @counter.zero? && @pipe.anybits?(0b01) && started?
-      end
-
-      # A load consumes its tick, so the counter never decrements on it
-      def reload
-        @counter = @latch
-        # A zero latch underflows again on the reload tick while running
-        underflow if @counter.zero? && started? && @pipe.anybits?(0b01)
-      end
-
-      def count
-        @counter -= 1 if @counter.positive?
-        underflow if @counter.zero? && @pipe.anybits?(0b01)
-      end
-
-      def underflow
-        @underflowed = true
-        @reload = true
-        @counter = @latch
-        @toggle = !@toggle
-        return unless control.run_mode? || @oneshot_linger.positive?
-
-        control.start = false
-        @pipe = 0
-      end
-    end
-  end
-end