badline 0.12.1 → 0.14.0

data/lib/badline/cpu/saved_state.rb

@@ -1,115 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CPU
-    # The CPU's state for a snapshot: the registers, the interrupt lines and
-    # their pipeline, and the step of the instruction in flight, named by
-    # where its plan comes from.
-    module SavedState
-      # Writes everything the CPU holds, down to the step of the instruction
-      # it is in, for load_state to put back. The interrupt lines, BA stalls
-      # and SO are state too; the traps and the debug flag belong to the host.
-      def save_state(out)
-        out.marker("CPU")
-        out.int(@program_counter).int(@stack_pointer).int(@a).int(@x).int(@y).int(@status.value)
-        [@irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll, @boundary_irq,
-         @boundary_nmi, @boundary_crossed, @brk, @pending_write, @so_high, @optional_dummy,
-         @branch_taken].each { |flag| out.boolean(flag) }
-        out.optional_int(@interrupt).optional_int(@stalled_at).int(@cycles).int(@instructions)
-        out.int(plan_source).int(@index).int(OPERATIONS.index(@operation) || -1)
-        [@address, @dummy_address, @value, @rmw_result, @pointer].each { |register| out.optional_int(register) }
-      end
-
-      def load_state(input)
-        input.marker("CPU")
-        @program_counter = input.int
-        @stack_pointer = input.int
-        @a = input.int
-        @x = input.int
-        @y = input.int
-        @status.value = input.int
-        load_flags(input)
-        @interrupt = input.optional_int
-        @stalled_at = input.optional_int
-        @cycles = input.int
-        @instructions = input.int
-        load_plan(input.int)
-        @index = input.int
-        operation = input.int
-        @operation = operation.negative? ? nil : OPERATIONS.fetch(operation)
-        load_working_registers(input)
-      end
-
-      # Drops the instruction or interrupt sequence in flight and the
-      # interrupt lines' pipeline, so the next cycle fetches an opcode at the
-      # program counter, and sets the cycle count. A snapshot taken between
-      # instructions, as VICE's are, restores through here.
-      def resume(cycles)
-        @irq_sample = @irq_pending = false
-        @nmi_sample = @nmi_pending = false
-        @skip_poll = false
-        @interrupt = nil
-        @brk = false
-        @stalled_at = nil
-        @cycles = cycles
-        end_sequence
-        @pending_write = false
-      end
-
-      private
-
-      # Where the plan running comes from: an opcode's microcode, or FETCH,
-      # INTERRUPT or JAMMED below it.
-      def plan_source
-        return FETCH if @plan.equal?(FETCH_PLAN)
-        return INTERRUPT if @plan.equal?(INTERRUPT_PLAN)
-        return JAMMED if @plan.equal?(JAMMED_PLAN)
-
-        MICROCODE.index { |micro| micro.plan.equal?(@plan) && micro.operation == @operation } ||
-          MICROCODE.index { |micro| micro.plan.equal?(@plan) }
-      end
-
-      def load_plan(source)
-        case source
-        when FETCH then use_plan(FETCH_PLAN, FETCH_WRITES)
-        when INTERRUPT then use_plan(INTERRUPT_PLAN, INTERRUPT_WRITES)
-        when JAMMED then use_plan(JAMMED_PLAN, JAMMED_WRITES)
-        else
-          micro = MICROCODE.fetch(source)
-          use_plan(micro.plan, micro.writes)
-        end
-      end
-
-      def use_plan(plan, writes)
-        @plan = plan
-        @writes = writes
-      end
-
-      def load_flags(input)
-        @irq = input.boolean?
-        @nmi = input.boolean?
-        @irq_sample = input.boolean?
-        @irq_pending = input.boolean?
-        @nmi_sample = input.boolean?
-        @nmi_pending = input.boolean?
-        @skip_poll = input.boolean?
-        @boundary_irq = input.boolean?
-        @boundary_nmi = input.boolean?
-        @boundary_crossed = input.boolean?
-        @brk = input.boolean?
-        @pending_write = input.boolean?
-        @so_high = input.boolean?
-        @optional_dummy = input.boolean?
-        @branch_taken = input.boolean?
-      end
-
-      def load_working_registers(input)
-        @address = input.optional_int
-        @dummy_address = input.optional_int
-        @value = input.optional_int
-        @rmw_result = input.optional_int
-        @pointer = input.optional_int
-      end
-    end
-  end
-end

data/lib/badline/cpu/stack_operations.rb

@@ -1,82 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class CPU
-    # Steps that use the stack: PHA, PHP, PLA, PLP, JSR, RTS and RTI.
-    module StackOperations
-      private
-
-      def op_push_exec
-        send(@operation, nil, nil)
-        end_instruction
-      end
-
-      def op_pull_dummy
-        @memory.peek(stack_address)
-      end
-
-      def op_pull_exec
-        send(@operation, nil, nil)
-        end_instruction
-      end
-
-      def op_pull_low
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @address = @memory.peek(stack_address)
-      end
-
-      def op_pull_high
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @address |= @memory.peek(stack_address) << 8
-      end
-
-      def op_rts_fixup
-        @memory.peek(@address)
-        @program_counter = (@address + 1) & 0xffff
-        end_instruction
-      end
-
-      def op_rti_pull_status
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @status.value = @memory.peek(stack_address)
-        @status.break = false
-      end
-
-      def op_rti_pull_high
-        @stack_pointer = (@stack_pointer + 1) & 0xff
-        @program_counter = @address | (@memory.peek(stack_address) << 8)
-        end_instruction
-      end
-
-      def op_jsr_low
-        @address = @memory.peek(@program_counter)
-        @program_counter = (@program_counter + 2) & 0xffff
-      end
-
-      def op_jsr_dummy
-        @memory.peek(stack_address)
-      end
-
-      def op_jsr_push_high
-        @memory.poke(stack_address, high_byte(return_address))
-      end
-
-      def op_jsr_push_low
-        @memory.poke(stack_address(-1), low_byte(return_address))
-        @stack_pointer = (@stack_pointer - 2) & 0xff
-      end
-
-      # JSR reads its target's high byte after pushing the return address.
-      # A JSR running from the stack page can overwrite its own operand
-      # with that push, and then jumps to the overwritten address.
-      def op_jsr_high
-        @program_counter = @address | (@memory.peek(return_address) << 8)
-        end_instruction
-      end
-
-      def return_address
-        (@program_counter - 1) & 0xffff
-      end
-    end
-  end
-end

data/lib/badline/cpu.rb

@@ -1,10 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/cpu/core"
-
-module Badline
-  # The C64's 6510, on the AddressBus.
-  class CPU
-    include Core
-  end
-end

data/lib/badline/cpu_port.rb

@@ -1,112 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  # The I/O port of the 6510 and the 8502 at $00 (direction) and $01
-  # (data). An input pin reads its pull-up, P4 reads the datasette's sense
-  # line, and a pin without a pull-up holds the charge last driven onto
-  # it. P5 drives the datasette motor through an inverter: low runs it.
-  #
-  # The 6510 has pull-ups on P0-P2 and P4 and leaves P3, P6 and P7
-  # floating. The 8502 adds a CAPS LOCK pin on P6, high while the key is
-  # up.
-  class CPUPort
-    TAPE_SENSE = 0b0001_0000
-
-    # The direction and output registers, and the charge on the floating
-    # pins.
-    attr_reader :ddr, :data, :floating
-
-    # The port as the banking logic reads it (PortStatus).
-    attr_reader :status
-
-    # Whether CAPS LOCK is down, holding its pin low.
-    attr_reader :caps_lock
-
-    # +pullups+ and +floating+ are the masks of the pins with a pull-up and
-    # of the floating ones, and +caps_lock+ the CAPS LOCK pin's, 0 where
-    # there is none.
-    def initialize(datasette, pullups:, floating:, caps_lock: 0)
-      @datasette = datasette
-      @pullups = pullups
-      @floating_mask = floating
-      @caps_lock_pin = caps_lock
-      @caps_lock = false
-      @ddr = 0x00
-      @data = 0x00
-      @floating = 0x00
-      @change_handler = nil
-      @status = PortStatus.new(%i[basic kernal io tape_out tape_switch tape_motor], value: input_value)
-    end
-
-    # Calls the block after every write to the port, for the bus to remap
-    # its banks.
-    def on_change(&handler)
-      @change_handler = handler
-    end
-
-    # What a read of $01 sees.
-    def value = @status.value
-
-    def write_ddr(value)
-      @ddr = value
-      update
-    end
-
-    def write_data(value)
-      @data = value
-      update
-    end
-
-    # The RES line clears the direction and output registers. The floating
-    # pins keep their charge.
-    def reset!
-      @ddr = 0x00
-      @data = 0x00
-      update
-    end
-
-    # Sets the registers and the charge, as a snapshot restores them, and
-    # drives the motor and calls the change handler as a write does.
-    def restore(ddr, data, floating)
-      load(ddr, data, floating)
-      update
-    end
-
-    # Sets the registers and the charge, as a snapshot loads them, without
-    # driving the motor or calling the change handler.
-    def load(ddr, data, floating)
-      @ddr = ddr
-      @data = data
-      @floating = floating
-      refresh
-    end
-
-    # Holds CAPS LOCK down, or lets it up.
-    def caps_lock=(down)
-      @caps_lock = down
-      refresh
-    end
-
-    # Reads the inputs again, after the datasette's sense line changes.
-    def refresh
-      @status.value = input_value
-    end
-
-    private
-
-    def update
-      driven = @ddr & @floating_mask
-      @floating = (@floating & ~driven) | (@data & driven)
-      refresh
-      @datasette.motor = !@status.tape_motor?
-      @change_handler&.call
-    end
-
-    def input_value
-      input = @pullups | (@floating & @floating_mask)
-      input |= @caps_lock_pin unless @caps_lock
-      input &= ~TAPE_SENSE if @datasette.sense_low?
-      (@data & @ddr) | (input & ~@ddr & 0xff)
-    end
-  end
-end

data/lib/badline/datasette.rb

@@ -1,161 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  # The 1530 datasette. Plays a pulse stream into CIA 1's FLAG pin while the
-  # motor runs with a key pressed, and reports the keys through the cassette
-  # sense line on the $01 port. With RECORD down too, it records the
-  # machine's write line onto the tape instead.
-  class Datasette
-    # What inserting a tape raises on a machine without a cassette port.
-    class Missing < ArgumentError; end
-
-    attr_reader :tape
-    attr_writer :motor
-
-    def initialize(tape = nil)
-      @tape = tape
-      @connected = true
-      @playing = false
-      @recording = false
-      @write_high = true
-      @since = 0
-      @motor = false
-      @countdown = 0
-      @flag_handler = nil
-      @sense_handler = nil
-    end
-
-    # Falling edges on the tape read line.
-    def on_flag(&handler)
-      @flag_handler = handler
-    end
-
-    # The cassette sense line, which the $01 port reads back.
-    def on_sense_change(&handler)
-      @sense_handler = handler
-    end
-
-    # Whether the machine has a datasette at its cassette port. The SX-64
-    # has none: its keys stay up and it takes no tape.
-    def connected? = @connected
-
-    def disconnect!
-      eject
-      @connected = false
-    end
-
-    def insert(tape)
-      raise Missing, "this machine has no datasette" unless @connected
-
-      @tape = tape
-      rewind
-    end
-
-    def eject
-      stop!
-      @tape = nil
-    end
-
-    def rewind
-      @tape&.rewind
-      @countdown = 0
-    end
-
-    def play! = press(true)
-    def stop! = press(false)
-
-    # Presses RECORD and PLAY together.
-    def record!
-      return if !@connected || @tape.nil?
-
-      press(true)
-      @recording = true
-      @since = 0
-    end
-
-    def recording? = @recording
-
-    # The machine's tape write line. While the deck records with its motor
-    # running, each rising edge ends a pulse on the tape, as long as the
-    # time since the edge before, and plays back as a falling edge on the
-    # read line.
-    def write_line=(high)
-      rose = high && !@write_high
-      @write_high = high
-      return unless rose && @recording && running?
-
-      @tape.record_pulse(@since)
-      @since = 0
-    end
-
-    def playing? = @playing
-
-    # Sense reads low while a key is down on the deck.
-    def sense_low? = @playing
-
-    def motor? = @motor
-
-    def running? = @playing && @motor && !@tape.nil?
-
-    # The keys, the motor, the countdown to the next pulse and the tape:
-    # its path, its bytes and how far it has played.
-    def save_state(out)
-      out.marker("DATASETTE")
-      out.boolean(@playing).boolean(@motor).int(@countdown).boolean(!@tape.nil?)
-      return unless @tape
-
-      out.string(@tape.path).blob(@tape.bytes).int(@tape.position)
-    end
-
-    # The tape goes back in from the bytes the state holds, without its
-    # host file, unless the tape in is the same one. The sense and flag
-    # handlers don't fire.
-    def load_state(input)
-      input.marker("DATASETTE")
-      @playing = input.boolean?
-      @motor = input.boolean?
-      @countdown = input.int
-      return @tape = nil unless input.boolean?
-
-      path = input.string
-      bytes = input.blob
-      position = input.int
-      @tape = Storage::TAP.new(path, bytes:) unless @tape&.path&.b == path && @tape.bytes == bytes
-      @tape.position = position
-    end
-
-    def cycle!
-      return unless running?
-      return @since += 1 if @recording
-
-      @countdown = @tape.next_pulse.to_i if @countdown.zero?
-      return if @countdown.zero?
-
-      @countdown -= 1
-      @flag_handler&.call if @countdown.zero?
-    end
-
-    def inspect
-      "#<#{self.class.name} tape=#{@tape ? @tape.class.name : 'none'} " \
-        "playing=#{@playing} motor=#{@motor}>"
-    end
-
-    private
-
-    def press(down)
-      return if down == @playing || !@connected
-
-      finish_recording unless down
-      @playing = down
-      @sense_handler&.call
-    end
-
-    # Releasing the keys ends a recording, and writes the tape out.
-    def finish_recording
-      return unless @recording
-
-      @recording = false
-      @tape.save
-    end
-  end
-end

data/lib/badline/debug_register.rb

@@ -1,28 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  # The VICE debug cartridge register, mapped at $D7FF on the C64. It is a
-  # VICE facility rather than real hardware, enabled there with -debugcart:
-  # writing a byte ends the run with that value as the exit code. The VICE
-  # test suites write $00 for success and $ff for failure.
-  #
-  # Wraps the SID's top mirror page, so every other access falls through.
-  class DebugRegister
-    ADDRESS = 0xd7ff
-
-    def initialize(sid, &handler)
-      @sid = sid
-      @handler = handler
-    end
-
-    def peek(addr)
-      @sid.peek(addr)
-    end
-
-    def poke(addr, value)
-      return @handler.call(value) if addr == ADDRESS
-
-      @sid.poke(addr, value)
-    end
-  end
-end

data/lib/badline/drive/core.rb

@@ -1,147 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  module Drive
-    # What every Commodore disk drive here shares: a 6502 running the DOS
-    # ROM, with chips on its bus facing the serial bus and the disk
-    # mechanism, on a clock of its own.
-    #
-    # The drive runs on its own crystal, so it clocks against the host's
-    # clock through a fractional accumulator: each host cycle adds the
-    # drive's clock rate worth of phase, and every whole host period in it
-    # runs a drive cycle. Against the PAL C64's 985,248 Hz a drive at
-    # 1 MHz runs one drive cycle per host cycle and a second one about
-    # every 67. The host sets its clock on attaching the drive, and until
-    # then a 1 MHz drive runs one cycle per host cycle.
-    #
-    # The Mechanism reads a Disk put in with insert.
-    #
-    # While the DOS idles, host_cycle! skips the drive's cycles and catches
-    # up on them later, exactly (see Idle). The readers of the drive's parts
-    # catch up first, so they find the drive as running every cycle would
-    # have left it. Once the DOS's timer interrupts come round, the drive
-    # sleeps through them too (see Orbit).
-    #
-    # A model includes Core and builds its parts, sets @clock_hz and
-    # @idle_loop, and runs one drive cycle in step. It hears ATN on
-    # connecting (hear_atn), drives the serial bus (serial_output), and
-    # answers Idle's and Orbit's questions about its chips, as VIAs does
-    # for the 1541 and the 1571.
-    module Core
-      include Sleep
-      include Idle
-      include Orbit
-
-      attr_reader :device, :serial_bus
-
-      def cpu
-        settle!
-        @cpu
-      end
-
-      def bus
-        settle!
-        @bus
-      end
-
-      def mechanism
-        settle!
-        @mechanism
-      end
-
-      def cycles
-        settle!
-        @cycles
-      end
-
-      def ram = bus.ram
-
-      def host_clock_hz=(clock_hz)
-        settle!
-        @host_clock_hz = clock_hz
-      end
-
-      # Plugs the drive into a serial bus, leaving the one it was on. A drive
-      # starts out on a bus of its own, with nothing else on it.
-      def connect(serial_bus)
-        settle!
-        @serial_bus&.detach(self)
-        @serial_bus = serial_bus
-        @serial_port.bus = serial_bus
-        serial_bus.attach(self)
-        hear_atn
-      end
-
-      # Puts a Disk in the drive (Disk.from_d64 makes one from an image).
-      # Nil takes the disk out.
-      def insert(disk)
-        settle!
-        @mechanism.insert(disk)
-      end
-
-      def disk = mechanism.disk
-
-      # Whether the LED is lit. Reading it leaves the drive asleep: the LED
-      # is the same at the end of every pass the drive sleeps through.
-      def led_on? = @mechanism.led_on?
-
-      # Stores what the head wrote since the motor last stopped in the
-      # disk's image, as the motor stopping does.
-      def flush
-        settle!
-        @mechanism.flush
-      end
-
-      # Runs the drive cycles that fall in one host cycle: none, one or two.
-      # The host has run this cycle already, and the drive sees what it did
-      # from the next one on (see SerialPort). Asleep, the drive owes the
-      # cycles instead, until ATN moves or its counters are due (see Idle).
-      # It looks at ATN only after the machine pushed its lines into the bus
-      # (see host_written!).
-      def host_cycle!
-        if @asleep
-          return if (@slept += 1) != @wake_at && @host_still
-
-          return doze
-        end
-
-        phase = @phase + @clock_hz
-        while phase >= @host_clock_hz
-          @asleep ? @owed += 1 : run_cycle
-          phase -= @host_clock_hz
-        end
-        @phase = phase
-        settle! if @serial_port.atn_moved?
-        @serial_port.latch_host
-        plan_wake if @asleep
-      end
-
-      # The machine pushed its lines into the bus, so ATN may have moved.
-      def host_written!
-        @host_still = false
-      end
-
-      # The host moved its fast serial pins, which a 1541 has none to hear.
-      def fast_lines_moved = nil
-
-      # Runs one drive cycle, catching up first on any the drive owes (see
-      # step).
-      def cycle!
-        settle!
-        step
-      end
-
-      def inspect
-        "#<#{self.class.name} cycles=#{cycles} cpu=(#{cpu.inspect})>"
-      end
-
-      private
-
-      # A drive cycle from host_cycle!, which may find the idle loop.
-      def run_cycle
-        step
-        idle_loop_reached if @cpu.program_counter == @idle_loop && @idle_skip
-      end
-    end
-  end
-end