badline 0.12.1 → 0.14.0

data/lib/badline/chips/cia/timer.rb

@@ -0,0 +1,188 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CIA
+      class Timer
+        attr_accessor :counter, :latch
+        attr_reader :control, :underflowed
+
+        def initialize(control)
+          @control = control
+          @counter = @latch = 0xffff
+          @pipe = 0
+          @load_delay = 0
+          @reload = false
+          @underflowed = false
+          @oneshot_linger = 0
+          @toggle = true
+          settle
+        end
+
+        # The level this timer drives on its port B pin: a square wave that
+        # flips on each underflow, or a single high tick when one happens.
+        def output?
+          control.out_mode? ? @toggle : @underflowed
+        end
+
+        # Whether the timer is stopped with nothing in its pipeline, so a
+        # cycle changes nothing.
+        def idle? = @empty && !started?
+
+        # Whether the timer counts ø2 in continuous mode with nothing pending
+        # but the reload after an underflow, so fast_forward can run it. A
+        # latch below 2 is left out.
+        def free_running?
+          started? && !@control.run_mode? && @control.value.nobits?(0x20) && @latch >= 2 && @pipe == 0b11 &&
+            (@load_delay | @oneshot_linger).zero? && (@settled || @reload)
+        end
+
+        # Runs a free-running timer +cycles+ cycles at once, as cycle! would:
+        # an underflow every latch + 1 cycles, each one followed by the
+        # reload. Returns the underflows.
+        def fast_forward(cycles)
+          return 0 if cycles.zero?
+          return after_underflow(cycles, 0) unless @settled
+
+          if cycles < @counter
+            @counter -= cycles
+            return 0
+          end
+          after_underflow(cycles - @counter, 1)
+        end
+
+        def cycle!(feed)
+          feed &&= @control.value & 0x01 != 0
+          if @settled
+            return @counter -= 1 if feed && @counter > 1
+          elsif @empty
+            enter if feed
+            return
+          end
+          run_tick(feed)
+        end
+
+        def run_tick(feed)
+          @underflowed = false
+          @oneshot_linger -= 1 if @oneshot_linger.positive?
+          tick(feed)
+          settle
+        end
+
+        def write_control(value)
+          @toggle = true if value.anybits?(0x01) && !started?
+          @oneshot_linger = 2 if control.run_mode? && value.nobits?(0x08)
+          control.value = value & ~0x10
+          @load_delay = 3 if value.anybits?(0x10)
+          settle
+        end
+
+        def write_latch_low(value)
+          @latch = (@latch & 0xff00) | value
+        end
+
+        def write_latch_high(value)
+          @latch = (value << 8) | (@latch & 0xff)
+          @counter = @latch unless started?
+        end
+
+        # Whether the timer's PB output toggle is high, and its count pipeline
+        # as two bits, the newer stage high.
+        attr_reader :toggle, :pipe
+
+        # Sets the control register without its load strobe, the toggle and
+        # the count pipeline, as a VICE snapshot gives them.
+        def restore_pipeline(control, toggle, pipe)
+          @control.value = control & ~0x10
+          @toggle = toggle
+          @pipe = pipe
+          settle
+        end
+
+        private
+
+        def started?
+          @control.value & 0x01 != 0
+        end
+
+        # Where fast_forward lands +cycles+ after an underflow, with
+        # +underflows+ underflows counted so far.
+        def after_underflow(cycles, underflows)
+          periods, rest = cycles.divmod(@latch + 1)
+          underflows += periods
+          @toggle = !@toggle if underflows.odd?
+          @underflowed = rest.zero?
+          @reload = rest.zero?
+          @counter = @latch - (rest.zero? ? 0 : rest - 1)
+          settle
+          underflows
+        end
+
+        def enter
+          @pipe = 0b10
+          @empty = false
+        end
+
+        # With no load, reload or one-shot linger pending, a full pipe only
+        # counts and an empty one only waits to be fed.
+        def settle
+          quiet = (@load_delay | @oneshot_linger).zero? && !@reload
+          @settled = quiet && @pipe == 0b11
+          @empty = quiet && @pipe.zero?
+        end
+
+        def tick(feed)
+          counting = @pipe.anybits?(0b01)
+          @pipe = (@pipe >> 1) | (feed ? 0b10 : 0)
+          loading = @reload || @load_delay == 1
+          @reload = false
+
+          if loading
+            reload
+          elsif premature_underflow?
+            underflow
+          elsif counting
+            count
+          end
+
+          forced_load
+        end
+
+        def forced_load
+          return unless @load_delay.positive?
+
+          @load_delay -= 1
+          @counter = @latch if @load_delay == 1
+        end
+
+        # the final pipeline stage, before any pending load lands
+        def premature_underflow?
+          @counter.zero? && @pipe.anybits?(0b01) && started?
+        end
+
+        # A load consumes its tick, so the counter never decrements on it
+        def reload
+          @counter = @latch
+          # A zero latch underflows again on the reload tick while running
+          underflow if @counter.zero? && started? && @pipe.anybits?(0b01)
+        end
+
+        def count
+          @counter -= 1 if @counter.positive?
+          underflow if @counter.zero? && @pipe.anybits?(0b01)
+        end
+
+        def underflow
+          @underflowed = true
+          @reload = true
+          @counter = @latch
+          @toggle = !@toggle
+          return unless control.run_mode? || @oneshot_linger.positive?
+
+          control.start = false
+          @pipe = 0
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cia.rb

@@ -0,0 +1,281 @@
+# frozen_string_literal: true
+
+require "badline/chips/cia/time_of_day"
+require "badline/chips/cia/interrupt_register"
+require "badline/chips/cia/serial"
+require "badline/chips/cia/timer"
+require "badline/chips/cia/fast_forward"
+require "badline/chips/cia/keyed_parts"
+
+module Badline
+  module Chips
+    # CIA (Complex Interface Adapter) chip
+    class CIA
+      include Addressable
+      include FastForward
+
+      # The original NMOS 6526 of the breadbin C64, and the HMOS 6526A of the
+      # C64C, which differs from it only in its interrupt control register.
+      MODELS = %i[mos6526 mos6526a].freeze
+
+      attr_reader :start, :control_a, :control_b, :serial, :model
+
+      # What's on the ports outside the chip. It pulls port lines low through
+      # read_a and read_b, and on CIA 1 drives PB4 through port_b4_high?.
+      attr_accessor :peripheral
+
+      # Timer A and timer B.
+      def timers = [@ta, @tb]
+
+      # Port A and B's data and direction registers.
+      def port_registers = [@data_port_a, @data_port_b, @data_dir_a, @data_dir_b]
+
+      def interrupt_status = @icr.status
+
+      def interrupt_control = @icr.mask
+
+      def interrupt!(delay = 1) = @icr.assert!(delay)
+
+      def time_of_day = @tod
+
+      def timer_a = @ta.counter
+
+      def timer_a=(value)
+        @ta.counter = value
+      end
+
+      def timer_a_latch = @ta.latch
+
+      def timer_a_latch=(value)
+        @ta.latch = value
+      end
+
+      def timer_b = @tb.counter
+
+      def timer_b=(value)
+        @tb.counter = value
+      end
+
+      def timer_b_latch = @tb.latch
+
+      def timer_b_latch=(value)
+        @tb.latch = value
+      end
+
+      # +tod_hz+ is the rate of the pulses on the TOD pin, the region's mains
+      # unless a machine feeds it otherwise, and 0 for a pin held still.
+      def initialize(start: 0, peripheral: nil, model: :mos6526, region: Region::PAL, tod_hz: nil)
+        raise ArgumentError, "unknown CIA model #{model}" unless MODELS.include?(model)
+
+        addressable_at(start, length: 2**8)
+
+        @model = model
+        @clock_hz = region.clock_hz
+        @mains_hz = tod_hz || region.mains_hz
+
+        @peripheral = peripheral
+        @port_b4_handler = nil
+        @port_a_handler = nil
+        @port_b4_high = true
+        reset!
+      end
+
+      # The RES line: ports back to inputs, timers stopped with their latches
+      # full, interrupts masked and the TOD clock stopped at 1:00:00.0. The
+      # PB4 level carries over and is resampled on the next cycle.
+      def reset!
+        @data_port_a = 0x00
+        @data_port_b = 0x00
+        @data_dir_a = 0x00
+        @data_dir_b = 0x00
+        @port_b4_driven_high = true
+        @cnt_high = true
+        @cnt_rise = false
+        @tod = TimeOfDay.new(clock_hz: @clock_hz, mains_hz: @mains_hz)
+        @icr = InterruptRegister.new(@model)
+        @icr_status = @icr.status
+        @control_a = ControlRegister.new(%i[start output out_mode run_mode load
+                                            in_mode serial_mode clock_frequency])
+        @control_b = ControlRegister.new(%i[start output out_mode run_mode load
+                                            in_cnt in_timer_a alarm])
+        @ta = Timer.new(@control_a)
+        @tb = Timer.new(@control_b)
+        @serial = Serial.new(@control_a)
+        @port_a_handler&.call
+      end
+
+      # Register a change handler on the PB4 line. On CIA 1, this feeds the
+      # light pen input.
+      def on_port_b4_change(&handler)
+        @port_b4_handler = handler
+      end
+
+      # Register a handler for writes that can move port A's lines: to the
+      # data register or DDR, and the reset. On CIA 2, this tells the drives
+      # on the serial bus that the C64 may have moved a line.
+      def on_port_a_write(&handler)
+        @port_a_handler = handler
+      end
+
+      # A falling edge on the FLAG pin. On CIA 1 the datasette's tape read
+      # line drives it, on CIA 2 the serial bus SRQ.
+      def flag! = raise_interrupt(:flag)
+
+      def interrupted? = @icr_status.value >= 0x80
+
+      def cycle!
+        @icr.cycle! unless @icr.quiet
+        refresh_port_b4 if @port_b4_handler
+        level = @serial.cnt
+        level == @cnt_high ? @cnt_rise = false : cnt_edge(level)
+        underflowed = update_timers
+        @serial.cycle!(underflowed) { trigger_serial } if underflowed || !@serial.idle
+        @tod.cycle! { trigger_alarm }
+      end
+
+      def read_port_a
+        lines = driven_lines(@data_port_a, @data_dir_a)
+        return lines unless peripheral
+
+        lines & peripheral.read_a(lines, driven_lines(@data_port_b, @data_dir_b))
+      end
+
+      # Port A as driven by the data/direction registers alone, without
+      # peripheral pulldown. Cheap path for the VIC bank lookup.
+      def port_a_lines = driven_lines(@data_port_a, @data_dir_a)
+
+      # Port B as driven by the data/direction registers alone.
+      def port_b_lines = driven_lines(@data_port_b, @data_dir_b)
+
+      def read_port_b
+        lines = driven_lines(@data_port_b, @data_dir_b)
+        lines &= peripheral.read_b(driven_lines(@data_port_a, @data_dir_a), lines) if peripheral
+        apply_timer_output(lines)
+      end
+
+      def peek(addr)
+        case offset_of(addr) & 0x0f
+        when 0x00 then read_port_a
+        when 0x01 then read_port_b
+        when 0x02 then @data_dir_a
+        when 0x03 then @data_dir_b
+        when 0x04 then low_byte(@ta.counter)
+        when 0x05 then high_byte(@ta.counter)
+        when 0x06 then low_byte(@tb.counter)
+        when 0x07 then high_byte(@tb.counter)
+        when 0x08 then @tod.tenths
+        when 0x09 then @tod.seconds
+        when 0x0a then @tod.minutes
+        when 0x0b then @tod.hours
+        when 0x0c then @serial.data
+        when 0x0d then @icr.read
+        when 0x0e then control_a.value
+        when 0x0f then control_b.value
+        end
+      end
+
+      def poke(addr, value)
+        case offset_of(addr) & 0x0f
+        when 0x00 then update_port_a { @data_port_a = value }
+        when 0x01 then update_port_b { @data_port_b = value }
+        when 0x02 then update_port_a { @data_dir_a = value }
+        when 0x03 then update_port_b { @data_dir_b = value }
+        when 0x04 then @ta.write_latch_low(value)
+        when 0x05 then @ta.write_latch_high(value)
+        when 0x06 then @tb.write_latch_low(value)
+        when 0x07 then @tb.write_latch_high(value)
+        when 0x08 then @tod.write(:tenths, value, alarm: control_b.alarm?)
+        when 0x09 then @tod.write(:seconds, value, alarm: control_b.alarm?)
+        when 0x0a then @tod.write(:minutes, value, alarm: control_b.alarm?)
+        when 0x0b then @tod.write_hours(value, alarm: control_b.alarm?)
+        when 0x0c then @serial.write(value)
+        when 0x0d then @icr.write(value)
+        when 0x0e then write_control_a(value)
+        when 0x0f then @tb.write_control(value)
+        end
+      end
+
+      private
+
+      def update_port_a
+        yield
+        @port_a_handler&.call
+      end
+
+      def update_port_b
+        yield
+        @port_b4_driven_high = driven_lines(@data_port_b, @data_dir_b).anybits?(0x10)
+        refresh_port_b4 if @port_b4_handler
+      end
+
+      # PB4 is also control port 1's fire line, and a peripheral pulls it low
+      # without any register write, so the level is resampled every cycle rather
+      # than only after a poke.
+      def refresh_port_b4
+        high = @port_b4_driven_high && (peripheral.nil? || peripheral.port_b4_high?)
+        return if high == @port_b4_high
+
+        @port_b4_high = high
+        @port_b4_handler.call(high)
+      end
+
+      def driven_lines(register, direction)
+        # Output bits are driven from the data register; input bits float high.
+        # External peripherals can still pull any line low (wired-AND).
+        (register & direction) | (~direction & 0xff)
+      end
+
+      def apply_timer_output(value)
+        value = with_bit(value, 6, @ta.output?) if control_a.output?
+        value = with_bit(value, 7, @tb.output?) if control_b.output?
+        value
+      end
+
+      def with_bit(value, bit, set)
+        set ? value | (1 << bit) : value & ~(1 << bit)
+      end
+
+      def trigger_alarm = raise_interrupt(:alarm)
+      def trigger_serial = raise_interrupt(:serial)
+
+      def raise_interrupt(source) = @icr.flag(source)
+
+      # CNT is sampled once a cycle. When the serial port drives it from this
+      # cycle's timer A underflow, the new level is picked up on the next one.
+      def cnt_edge(level)
+        @cnt_high = level
+        @cnt_rise = level
+        @serial.rising_edge! { trigger_serial } if level
+      end
+
+      # Returns whether timer A underflowed, which clocks the serial port.
+      #
+      # CRB bits 6-5 pick timer B's source: ø2, CNT edges, timer A
+      # underflows, or timer A underflows gated by the CNT level. Every source
+      # drives the same count-enable line, so a cascaded underflow goes through
+      # the input pipeline exactly as a CNT edge does.
+      def update_timers
+        @ta.cycle!(@control_a.value & 0x20 == 0x20 ? @cnt_rise : true)
+        underflowed = @ta.underflowed
+        @tb.cycle!(
+          case @control_b.value & 0x60
+          when 0x00 then true
+          when 0x20 then @cnt_rise
+          when 0x40 then underflowed
+          else underflowed && @cnt_high
+          end
+        )
+        @icr.flag(:timer_a) if underflowed
+        @icr.timer_b_underflow! if @tb.underflowed
+        underflowed
+      end
+
+      def write_control_a(value)
+        was_output = control_a.serial_mode?
+        @ta.write_control(value)
+        @serial.reset! { trigger_serial } if control_a.serial_mode? != was_output
+        @tod.fifty_hz = control_a.clock_frequency?
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/addressing.rb

@@ -0,0 +1,133 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      # Steps that read an instruction's operand bytes and work out the
+      # address it operates on, which they leave in @address. Also the
+      # single-step implied, accumulator and immediate instructions, and JMP.
+      module Addressing
+        private
+
+        def op_implied_dummy
+          @memory.peek(@program_counter)
+        end
+
+        def op_implied_exec
+          @memory.peek(@program_counter)
+          send(@operation, nil, nil)
+          end_instruction
+        end
+
+        def op_accumulator_exec
+          @memory.peek(@program_counter)
+          send(@operation, :accumulator, @a)
+          end_instruction
+        end
+
+        def op_immediate_read
+          value = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 1) & 0xffff
+          send(@operation, nil, value)
+          end_instruction
+        end
+
+        def op_zp
+          @address = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 1) & 0xffff
+        end
+
+        def op_zp_x
+          @memory.peek(@address)
+          @address = (@address + @x) & 0xff
+        end
+
+        def op_zp_y
+          @memory.peek(@address)
+          @address = (@address + @y) & 0xff
+        end
+
+        def op_abs_low
+          @address = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 1) & 0xffff
+        end
+
+        def op_abs_high
+          @address |= @memory.peek(@program_counter) << 8
+          @program_counter = (@program_counter + 1) & 0xffff
+        end
+
+        def op_abs_high_x
+          high = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 1) & 0xffff
+          index_address(high, @x)
+        end
+
+        def op_abs_high_y
+          high = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 1) & 0xffff
+          index_address(high, @y)
+        end
+
+        def op_idx_dummy
+          @memory.peek(@dummy_address)
+        end
+
+        def op_zp_pointer
+          @pointer = @memory.peek(@program_counter)
+          @program_counter = (@program_counter + 1) & 0xffff
+        end
+
+        def op_pointer_x
+          @memory.peek(@pointer)
+          @pointer = (@pointer + @x) & 0xff
+        end
+
+        def op_pointer_low
+          @address = @memory.peek(@pointer)
+        end
+
+        def op_pointer_high
+          @address |= @memory.peek((@pointer + 1) & 0xff) << 8
+        end
+
+        def op_pointer_high_y
+          index_address(@memory.peek((@pointer + 1) & 0xff), @y)
+        end
+
+        def op_jmp_high
+          @program_counter = @address | (@memory.peek(@program_counter) << 8)
+          end_instruction
+        end
+
+        def op_indirect_low
+          @pointer = @address
+          @address = @memory.peek(@pointer)
+        end
+
+        # The pointer's high byte never increments, so JMP ($30FF) reads its
+        # target's high byte from $3000, not $3100.
+        def op_indirect_high
+          high = @memory.peek((@pointer & 0xff00) | ((@pointer + 1) & 0xff))
+          @program_counter = @address | (high << 8)
+          end_instruction
+        end
+
+        # Adds an index register to a base address. The 6502 adds to the low
+        # byte first and spends the next cycle reading from that address,
+        # before the carry reaches the high byte. Read instructions skip that
+        # cycle when there is no carry.
+        def index_address(high, index)
+          low = @address
+          @address = (((high << 8) | low) + index) & 0xffff
+          @boundary_crossed = (low + index) > 0xff
+          if @optional_dummy && !@boundary_crossed
+            @index += 1
+          else
+            @dummy_address = (high << 8) | ((low + index) & 0xff)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/boundary.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      # The steps at an instruction boundary: the opcode fetch that starts
+      # an instruction, and the ends of one.
+      module Boundary
+        private
+
+        # The first cycle of every instruction. Starts an interrupt if one was
+        # pending when the previous instruction ended. Otherwise reads the
+        # opcode and switches to its plan.
+        def op_fetch
+          return start_interrupt if @boundary_nmi || @boundary_irq
+
+          run_traps
+          opcode = @memory.peek(@program_counter)
+          log(opcode) if @debug
+          micro = MICROCODE[opcode]
+          @operation = micro.operation
+          @plan = micro.plan
+          @writes = micro.writes
+          @optional_dummy = micro.optional_dummy
+          @index = 1
+          @boundary_crossed = false
+          @program_counter = (@program_counter + 1) & 0xffff
+        end
+
+        def end_instruction
+          @instructions += 1
+          end_sequence
+        end
+
+        # Makes the next cycle an opcode fetch, and saves the pending interrupt
+        # flags for op_fetch. The next cycle polls before op_fetch runs, which
+        # updates the live flags.
+        def end_sequence
+          @plan = FETCH_PLAN
+          @writes = FETCH_WRITES
+          @index = 0
+          @boundary_irq = @irq_pending
+          @boundary_nmi = @nmi_pending
+        end
+
+        def log(opcode)
+          instruction = Instruction.find(opcode)
+          puts(
+            "#{@cycles}: PC: #{format16(@program_counter)} - " \
+            "#{instruction.name.upcase} #{instruction.addressing_mode}"
+          )
+        end
+      end
+    end
+  end
+end