badline 0.12.1 → 0.14.0

data/lib/badline/reu/dma.rb

@@ -1,273 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/reu/dma/saved_state"
-
-module Badline
-  class REU
-    # One transfer between the C64 and the REU's RAM, clocked a cycle at a
-    # time while the REC holds the bus. The REC only reads the C64's bus
-    # while BA is high, so a read followed by BA low waits for BA to rise.
-    # After a write it goes on through the first BA-low cycle and stops at
-    # the second. See doc/pinned-behaviour.md, REU DMA.
-    class DMA
-      include SavedState
-
-      # Transfer types, as the command register's bottom two bits give
-      # them.
-      STASH = 0
-      FETCH = 1
-      SWAP = 2
-      VERIFY = 3
-
-      # What the REC did on the cycle before.
-      IDLE = 0
-      READ = 1
-      WRITE = 2
-
-      # Where the transfer stopped, what it left for the length register,
-      # and the status bits it ended with.
-      attr_reader :c64, :expansion, :length, :events
-
-      def initialize(ram, span, bus)
-        @ram = ram
-        @span = span
-        @bus = bus
-        @c64 = @expansion = @length = @events = 0
-        @holding = false
-      end
-
-      # Whether the REC held the bus on the last cycle clocked, which it
-      # does while it waits for BA too, since the CPU stays halted.
-      def holds_bus? = @holding
-
-      # A length of 0 moves 64K. control is the address control register,
-      # which can hold either address where it is.
-      def start(type, c64, expansion, length, control)
-        @type = type
-        @c64 = c64
-        @expansion = expansion
-        @length = length.zero? ? 0x10000 : length
-        @c64_step = control.anybits?(FIX_C64) ? 0 : 1
-        @expansion_step = control.anybits?(FIX_EXPANSION) ? 0 : 1
-        @events = 0
-        @holding = true
-        @last = IDLE
-        @waiting = false
-        @ba_low_after_writes = 0
-        @stopped_after_write = false
-        @swap_write_due = false
-        @swap_read_again = false
-        @swap_byte = 0
-        @held_read = 0
-        @moved_all = false
-        @extra_cycle = false
-      end
-
-      # Writes the byte a fetch from these addresses starts with, without
-      # counting it. Other transfers start with a read.
-      def write_ahead(type, c64, expansion)
-        return unless type == FETCH
-
-        @c64 = c64
-        byte = @ram.peek(expansion)
-        @ram.latch = byte
-        write_c64(byte)
-      end
-
-      # One cycle of the transfer. The cycle the REC lets go of the bus on
-      # is the CPU's. late says BA fell on this cycle but a REC that moved a
-      # byte on the last one doesn't see it yet (VIC#reu_ba_late?), and
-      # handed_on that BA runs on from a bad line's DMA into a sprite's
-      # here (VIC#reu_ba_handed_on?).
-      def cycle!(ba_low, late, handed_on)
-        note_ba(ba_low, late)
-        @swap_read_again ||= handed_on && @swap_write_due
-        settle_held_read(ba_low) if @held_read.positive?
-        return if @waiting && ba_low
-
-        @waiting = false
-        @moved_all ? wind_down : move(ba_low)
-      end
-
-      private
-
-      # The second BA-low cycle in a row after writes stops the REC, and so
-      # does any BA-low cycle after a read. It then waits for BA to rise.
-      def note_ba(ba_low, late)
-        seen = ba_low && !late
-        if @last == READ
-          note_ba_after_read(seen)
-        elsif @last == WRITE
-          note_ba_after_write(seen)
-        end
-        @last = IDLE
-      end
-
-      # A swap's read that BA stops before its write is made again.
-      def note_ba_after_read(ba_low)
-        @waiting = ba_low
-        @ba_low_after_writes = 0
-        @swap_read_again = ba_low && @swap_write_due && @held_read.zero?
-      end
-
-      # A fetch's last write doesn't go through the first BA-low cycle.
-      # Pinned by REU/reutiming2/d and d2.
-      def note_ba_after_write(ba_low)
-        @ba_low_after_writes = ba_low ? @ba_low_after_writes + 1 : 0
-        @stopped_after_write = @ba_low_after_writes == 2 || (ba_low && @type == FETCH && @length == 1)
-        return unless @stopped_after_write
-
-        @waiting = true
-        @ba_low_after_writes = 0
-      end
-
-      # A fetch or a swap whose last write ran into BA, or a verify that
-      # found a difference before its last byte, takes one more cycle before
-      # the REC lets go of the bus.
-      def wind_down
-        if @extra_cycle || (@stopped_after_write && (@type == FETCH || @type == SWAP))
-          @extra_cycle = @stopped_after_write = false
-          @last = READ
-          return
-        end
-
-        @holding = false
-        settle
-      end
-
-      def move(ba_low)
-        case @type
-        when STASH then stash
-        when FETCH then fetch
-        when SWAP then swap(ba_low)
-        else verify
-        end
-      end
-
-      # The REU's data bus latch keeps the last byte the REC stored.
-      def stash
-        byte = read_c64
-        @ram.poke(@expansion, byte)
-        @ram.latch = byte
-        step
-        @last = READ
-      end
-
-      def fetch
-        byte = @ram.peek(@expansion)
-        @ram.latch = byte
-        write_c64(byte)
-        step
-        @last = WRITE
-      end
-
-      # Two cycles a byte: the C64's byte is read and stored while the
-      # REU's is fetched, and the REU's is written to the C64 on the next.
-      def swap(ba_low)
-        return read_swap_again if @swap_read_again
-
-        if @swap_write_due
-          @swap_write_due = false
-          write_c64(@swap_byte)
-          step
-          @last = WRITE
-          return
-        end
-
-        @swap_byte = @ram.peek(@expansion)
-        @swap_write_due = true
-        @last = READ
-        return swap_read_on_ba if ba_low
-
-        @ram.poke(@expansion, read_c64)
-      end
-
-      # A swap's read on the first BA-low cycle after a write, while AEC is
-      # still high. On the last byte the read is made there, the write
-      # follows on the next cycle whatever BA does, and the REC lets go.
-      # Otherwise the read stays open and takes what is on the bus two
-      # cycles later, or on the cycle BA rises if that comes first. Pinned
-      # by REU/reutiming2/e5-m2, f3-m2 and f4-m2.
-      def swap_read_on_ba
-        return @held_read = 2 unless @length == 1
-
-        @ram.poke(@expansion, read_c64)
-        @last = IDLE
-        @ba_low_after_writes = 0
-      end
-
-      # A swap's read that BA cut off from its write is made again when BA
-      # rises, and the write follows it. Pinned by REU/reutiming2/e4-m2,
-      # e6-m2 and g3-m2.
-      def read_swap_again
-        @swap_read_again = false
-        @ram.poke(@expansion, read_c64)
-        @last = READ
-      end
-
-      def settle_held_read(ba_low)
-        @held_read -= 1
-        return if @held_read.positive? && ba_low
-
-        @held_read = 0
-        @ram.poke(@expansion, read_c64)
-      end
-
-      # A difference ends the transfer, with one cycle more if bytes were
-      # left to compare.
-      def verify
-        same = @ram.peek(@expansion) == read_c64
-        step
-        @last = READ
-        return if same
-
-        @events |= FAULT
-        @extra_cycle = @length.positive?
-        @moved_all = true
-      end
-
-      # The REC reaches C64 memory as the CPU sees it, but at $00 and $01
-      # it reaches the RAM under the CPU's port.
-      def read_c64
-        @c64 < 0x02 ? @bus.ram.peek(@c64) : @bus.peek(@c64)
-      end
-
-      def write_c64(byte)
-        @c64 < 0x02 ? @bus.ram.poke(@c64, byte) : @bus.poke(@c64, byte)
-      end
-
-      # The REC counts the expansion address in its 19 low bits, from the
-      # top of its span back to 0, and leaves the bank bits above them as
-      # they were.
-      def step
-        @c64 = (@c64 + @c64_step) & 0xffff
-        low = (@expansion & 0x7ffff) + @expansion_step
-        @expansion = (@expansion & 0xf80000) | (low == @span ? 0 : low)
-        @length -= 1
-        @moved_all = true if @length.zero?
-      end
-
-      # The length register is left at 1 after a whole block. A fetch has
-      # already fetched the byte after its last into the latch.
-      def settle
-        return settle_verify if @type == VERIFY
-
-        @length += 1
-        @events |= END_OF_BLOCK
-        @ram.latch = @ram.peek(@expansion) if @type == FETCH
-      end
-
-      # A verify that compared every byte ends the block. One that found a
-      # difference on the byte before the last compares the last too, and
-      # ends the block if that one is the same.
-      def settle_verify
-        if @length.zero?
-          @length = 1
-          @events |= END_OF_BLOCK
-        elsif @length == 1 && @ram.peek(@expansion) == read_c64
-          @events |= END_OF_BLOCK
-        end
-      end
-    end
-  end
-end

data/lib/badline/reu/ram.rb

@@ -1,107 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class REU
-    # The REU's DRAM, as the REC addresses it. The REC counts 19 address
-    # bits, 17 on the 1700, and the 1764 fills only the first 256K of
-    # them: past that a read finds the latch on the REU's data bus, which
-    # holds the last byte the REC moved. A unit past 512K takes its upper
-    # address lines from the bank register.
-    class RAM
-      BANK_SIZE = 0x10000
-
-      # Where a bank of a 1764 that has just been switched on reads
-      # inverted, over the first 128K of each 256K. Over the second 128K
-      # it is the rest of the bank that reads inverted. Measured from
-      # REU/raminitpattern/dumpfile-256k-x1541.bin, a real 1764's dump.
-      INVERTED = [0x2a00...0x5400, 0x8000...0xac00, 0xd600...0x10000].freeze
-
-      attr_reader :size
-      attr_accessor :latch
-
-      def initialize(size, span)
-        @size = size
-        @mask = (size > 0x80000 ? size : span) - 1
-        @banks = Array.new(size / BANK_SIZE) { [] }
-        @power_on = [[], []]
-        @latch = 0xff
-      end
-
-      def peek(addr)
-        addr &= @mask
-        addr < @size ? bank(addr >> 16)[addr & 0xffff] : @latch
-      end
-
-      def poke(addr, value)
-        addr &= @mask
-        bank(addr >> 16)[addr & 0xffff] = value if addr < @size
-      end
-
-      # The latch, and each 64K bank the REC has touched. A bank it hasn't
-      # keeps its power-on contents until it does.
-      def save_state(out)
-        out.int(@latch)
-        @banks.each do |bank|
-          out.boolean(!bank.empty?)
-          out.blob(bank) unless bank.empty?
-        end
-      end
-
-      def load_state(input)
-        @latch = input.int
-        @banks.each_index { |number| @banks[number] = input.boolean? ? input.blob : [] }
-      end
-
-      # Every byte, as one string, with a bank the REC hasn't touched at
-      # its power-on contents.
-      def contents
-        power_on = power_on_strings
-        Array.new(@banks.length) do |number|
-          bank = @banks[number]
-          bank.empty? ? power_on[(number >> 1) & 1] : bank.pack("C*")
-        end.join
-      end
-
-      # Takes every byte from a string as long as the RAM. A bank that
-      # holds its power-on contents stays untouched.
-      def restore(bytes)
-        power_on = power_on_strings
-        @banks.each_index do |number|
-          slice = bytes.byteslice(number * BANK_SIZE, BANK_SIZE).to_s
-          @banks[number] = slice == power_on[(number >> 1) & 1] ? [] : slice.bytes
-        end
-      end
-
-      private
-
-      def power_on_strings
-        [0, 1].map do |half|
-          @power_on[half] = power_on_bank(half == 1) if @power_on[half].empty?
-          @power_on[half].pack("C*")
-        end
-      end
-
-      # A bank takes its power-on contents the first time it is touched,
-      # so an REU costs only the memory a program uses.
-      def bank(number)
-        bank = @banks[number]
-        return bank unless bank.empty?
-
-        half = (number >> 1) & 1
-        @power_on[half] = power_on_bank(half == 1) if @power_on[half].empty?
-        @banks[number] = @power_on[half].dup
-      end
-
-      # Pairs of $FF and $00 bytes, starting with a single $FF, and each
-      # odd page the inverse of the even one before it.
-      def power_on_bank(upper)
-        Array.new(BANK_SIZE) do |offset|
-          byte = (offset + 1).anybits?(2) ? 0x00 : 0xff
-          byte ^= 0xff if offset.anybits?(0x100)
-          inverted = INVERTED.any? { |range| range.cover?(offset) }
-          inverted == upper ? byte : byte ^ 0xff
-        end
-      end
-    end
-  end
-end

data/lib/badline/reu/saved_state.rb

@@ -1,80 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class REU
-    # The REU's state for a snapshot: the REC's registers and the values
-    # its counters start from, an armed or running transfer, the IRQ line,
-    # the transfer's own state and the RAM. The size is the machine's
-    # setup (Snapshot::Setup), so a restore finds an REU of the same size.
-    module SavedState
-      def size_kb = @size_kb
-
-      def save_state(out)
-        out.marker("REU")
-        [@status, @command, @c64, @c64_start, @expansion, @expansion_start, @bank, @bank_start, @length,
-         @length_start, @interrupt_mask, @address_control].each { |value| out.int(value) }
-        out.boolean(@armed).boolean(@requested).boolean(@running).boolean(@irq).boolean(@ba_was_low)
-        @dma.save_state(out)
-        @ram.save_state(out)
-      end
-
-      # The IRQ line comes back as it was without calling back into the
-      # machine, which reads it again afterwards.
-      def load_state(input)
-        input.marker("REU")
-        load_registers(input)
-        @armed = input.boolean?
-        @requested = input.boolean?
-        @running = input.boolean?
-        @irq = input.boolean?
-        @ba_was_low = input.boolean?
-        @dma.load_state(input)
-        @ram.load_state(input)
-      end
-
-      # The sixteen bytes the REC's registers read from $DF00, without
-      # what reading the status does, as VICE's REU1764 module holds them.
-      def register_file = Array.new(16) { |register| register_value(register) }
-
-      # Sets the registers from a register file, as writing them would but
-      # without starting a transfer: each address and the length set both
-      # the counter and the value it starts from. A command with the
-      # execute bit set and the $FF00 trigger on arms the REC.
-      def restore_registers(values)
-        @status = (values[STATUS] & (INTERRUPT_PENDING | END_OF_BLOCK | FAULT)) | @chips
-        @command = values[COMMAND]
-        @c64 = @c64_start = values[C64_LOW] | (values[C64_HIGH] << 8)
-        @expansion = @expansion_start = values[EXPANSION_LOW] | (values[EXPANSION_HIGH] << 8)
-        @bank = @bank_start = values[EXPANSION_BANK] & @bank_bits
-        @length = @length_start = values[LENGTH_LOW] | (values[LENGTH_HIGH] << 8)
-        @interrupt_mask = values[INTERRUPT_MASK] | 0x1f
-        @address_control = values[ADDRESS_CONTROL] | 0x3f
-        @armed = @command.anybits?(EXECUTE) && @command.nobits?(NO_FF00_TRIGGER)
-        @requested = @running = @ba_was_low = false
-        interrupt(@status.anybits?(INTERRUPT_PENDING))
-      end
-
-      # The RAM, every byte of it, as one string.
-      def ram_contents = @ram.contents
-
-      def restore_ram(bytes) = @ram.restore(bytes)
-
-      private
-
-      def load_registers(input)
-        @status = input.int
-        @command = input.int
-        @c64 = input.int
-        @c64_start = input.int
-        @expansion = input.int
-        @expansion_start = input.int
-        @bank = input.int
-        @bank_start = input.int
-        @length = input.int
-        @length_start = input.int
-        @interrupt_mask = input.int
-        @address_control = input.int
-      end
-    end
-  end
-end

data/lib/badline/reu/trigger.rb

@@ -1,32 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class REU
-    # Stands in for the page at $FF00 in the write table, passing each
-    # write on to what is mapped there and telling the REC when $FF00 is
-    # written, which starts an armed transfer.
-    class Trigger
-      ADDRESS = 0xff00
-
-      def initialize(reu)
-        @reu = reu
-        @target = nil
-      end
-
-      # Puts the trigger in front of target and returns it.
-      def wrap(target)
-        @target = target
-        self
-      end
-
-      def peek(addr)
-        @target.peek(addr)
-      end
-
-      def poke(addr, value)
-        @target.poke(addr, value)
-        @reu.ff00_written if addr == ADDRESS
-      end
-    end
-  end
-end