badline 0.12.1 → 0.14.0

data/lib/badline/c128/bus.rb

@@ -11,7 +11,7 @@ module Badline
     # $FF00-$FF04.
     #
     # In C64 mode the 8721 PLA decodes $01's LORAM, HIRAM and CHAREN and the
-    # cartridge's EXROM and GAME as a C64's does (AddressBus::PLA), and the
+    # cartridge's EXROM and GAME as a C64's does (C64::Bus::PLA), and the
     # MMU answers nowhere.
     #
     # In both modes the RAM is the bank CR picks, with common RAM in bank 0,
@@ -34,12 +34,11 @@ module Badline
     # Colour RAM has two 1K banks (ColorLines).
     class Bus
       include Addressable
-      include AddressBus::PLA
-      include AddressBus::ROMs
+      include C64::Bus::PLA
+      include C64::Bus::ROMs
       include MMUPages
       include IOPages
       include Z80Pages
-      include SavedState
 
       # The 8502's port has seven pins. P0-P5 are the 6510's, and P6 senses
       # the CAPS LOCK key, high while it is up. Bit 7 has no pin, and holds
@@ -48,9 +47,9 @@ module Badline
       PORT_FLOATING = 0b1000_1000
       CAPS_LOCK     = 0b0100_0000
 
-      # The C64's power-on pattern (AddressBus::RAM_POWER_ON) in both 64K
+      # The C64's power-on pattern (C64::Bus::RAM_POWER_ON) in both 64K
       # banks. The C128's own DRAMs' pattern is unmeasured.
-      RAM_POWER_ON = Array.new(2**17) { |addr| AddressBus::RAM_POWER_ON[addr & 0xffff] }.freeze
+      RAM_POWER_ON = Array.new(2**17) { |addr| C64::Bus::RAM_POWER_ON[addr & 0xffff] }.freeze
 
       # The VIC's write side: a write to $D02F also drives the extra
       # keyboard lines K0-K2 onto the keyboard's rows 8-10.
@@ -143,7 +142,7 @@ module Badline
         @on_mode_change = nil
         plug_chips(model, sid_model)
 
-        @datasette = Datasette.new
+        @datasette = Badline::Drives::Datasette.new
         @datasette.on_flag { @cia1.flag! }
         @datasette.on_sense_change { @cpu_port.refresh }
 
@@ -151,15 +150,18 @@ module Badline
         @color_ram = @color_lines.color_ram(1)
         build_z80_pages
         @vic_writes = VICWrites.new(@vic, @control_ports)
-        @open_bus = AddressBus::OpenBus.new(@vic)
+        @open_bus = C64::Bus::OpenBus.new(@vic)
         @configuration_reads = ConfigurationPage.new(@mmu, @open_bus)
         @configuration_writes = ConfigurationPage.new(@mmu, @open_bus)
 
-        @cpu_port = CPUPort.new(@datasette, pullups: PORT_PULLUPS, floating: PORT_FLOATING, caps_lock: CAPS_LOCK)
+        @cpu_port = Chips::CPU::Port.new(@datasette, pullups: PORT_PULLUPS, floating: PORT_FLOATING,
+                                                     caps_lock: CAPS_LOCK)
         @io_port = @cpu_port.status
 
         @read_pages = Array.new(256)
         @write_pages = Array.new(256)
+        @bank_io_reads = Array.new(256)
+        @bank_io_writes = Array.new(256)
         @address = 0
         @data = 0
         @io_mapped = false
@@ -210,8 +212,21 @@ module Badline
       # ROM at $C000-$FFFF.
       def system_rom_mapped? = !@mmu.c64_mode? && @mmu.cr.nobits?(0x30)
 
-      # The RAM the C128 KERNAL's bank number +bank+ reaches (Banks).
-      def peek_bank(bank, addr) = @banks.peek(bank, addr)
+      # The byte the C128 KERNAL's bank number +bank+ reads at +addr+, as
+      # its INDFET does: the ROMs and I/O the bank's CR value maps, over the
+      # RAM it reaches (Banks).
+      def peek_bank(bank, addr)
+        cr = @banks.configuration(bank)
+        return @mmu.peek_configuration(addr) if addr.between?(0xff00, 0xff04)
+        return bank_io_peek(addr) if cr.nobits?(0x01) && (addr & 0xf000) == 0xd000
+        return @basic_low_rom.peek(addr) if cr.nobits?(0x02) && addr.between?(0x4000, 0x7fff)
+
+        select = addr < 0xc000 ? (cr >> 2) & 0x03 : (cr >> 4) & 0x03
+        return @banks.peek(bank, addr) if addr < 0x8000 || select == 3
+        return @open_bus.peek(addr) unless select.zero?
+
+        system_rom_peek(addr)
+      end
 
       def write_bank(bank, addr, bytes) = @banks.write(bank, addr, bytes)
 
@@ -274,17 +289,17 @@ module Badline
       end
 
       def plug_chips(model, sid_model)
-        @keyboard = Keyboard.new(matrix: KEYBOARD_MATRIX)
-        @joystick1 = Joystick.new
-        @joystick2 = Joystick.new
-        @control_ports = ControlPorts.new(keyboard: @keyboard, joystick1: @joystick1, joystick2: @joystick2)
-        @vic = VIC.new(model: model.vic_model, region: @region)
-        @cia1 = CIA.new(start: 0xdc00, peripheral: @control_ports, model: model.cia_model, region: @region)
-        @cia2 = CIA.new(start: 0xdd00, model: model.cia_model, region: @region)
+        @keyboard = Input::Keyboard.new(matrix: KEYBOARD_MATRIX)
+        @joystick1 = Input::Joystick.new
+        @joystick2 = Input::Joystick.new
+        @control_ports = Input::ControlPorts.new(keyboard: @keyboard, joystick1: @joystick1, joystick2: @joystick2)
+        @vic = Chips::VIC.new(model: model.vic_model, region: @region)
+        @cia1 = Chips::CIA.new(start: 0xdc00, peripheral: @control_ports, model: model.cia_model, region: @region)
+        @cia2 = Chips::CIA.new(start: 0xdd00, model: model.cia_model, region: @region)
         @control_ports.port_a_source = @cia1
         @cia1.on_port_b4_change { |high| @vic.lightpen_level(high) }
-        @sid = SID.new(model: sid_model, pots: @control_ports)
-        @vdc = VDC.new(model: model.vdc_model, ram_kb: model.vdc_ram_kb, clock_hz: @region.clock_hz)
+        @sid = Chips::SID.new(model: sid_model, pots: @control_ports)
+        @vdc = Chips::VDC.new(model: model.vdc_model, ram_kb: model.vdc_ram_kb, clock_hz: @region.clock_hz)
       end
 
       def update_overlays!

data/lib/badline/c128/color_lines.rb

@@ -13,8 +13,8 @@ module Badline
         @cia2 = cia2
         @c64_characters = c64_characters
         @c128_characters = c128_characters
-        @bank0 = ColorMemory.new(vic)
-        @bank1 = ColorMemory.new(vic)
+        @bank0 = C64::ColorMemory.new(vic)
+        @bank1 = C64::ColorMemory.new(vic)
       end
 
       # Colour RAM bank +number+, 0 or 1.

data/lib/badline/c128/cpu.rb

@@ -4,7 +4,7 @@ module Badline
   class C128
     # The C128's 8502, on the C128::Bus, which holds its I/O port.
     class CPU
-      include Badline::CPU::Core
+      include Badline::Chips::CPU::Core
     end
   end
 end

data/lib/badline/c128/drives.rb

@@ -2,13 +2,13 @@
 
 module Badline
   class C128
-    # The true drives on the C128's serial bus: a Drive1541, the C128D's
-    # built-in 1571 (Drive1571) or a 1581 (Drive1581::Slot), each in a
+    # The true drives on the C128's serial bus: a Drives::Model1541, the C128D's
+    # built-in 1571 (Drives::Model1571) or a 1581 (Drives::Model1581::Slot), each in a
     # field of its own, so none makes another's per-cycle call a union.
     module Drives
       attr_reader :drive1571
 
-      # Plugs in a Drive1571, which then runs alongside the C128 on its own
+      # Plugs in a Drives::Model1571, which then runs alongside the C128 on its own
       # clock and talks to it over the serial bus, as attach_drive1541 does
       # for a 1541.
       def attach_drive1571(drive)
@@ -19,7 +19,7 @@ module Badline
         @serial_trap&.device = serial_trap_device
       end
 
-      # Unplugs the Drive1571.
+      # Unplugs the Drives::Model1571.
       def detach_drive1571
         return unless @drive1571
 
@@ -35,14 +35,14 @@ module Badline
       # returns it.
       def plug_true_drive
         detach_drive1581 if drive1581_on_device8?
-        Drive1571.new.tap { |drive| attach_drive1571(drive) }
+        Badline::Drives::Model1571.new.tap { |drive| attach_drive1571(drive) }
       end
 
       private
 
       # The serial bus, with no disk in device 8's traps and no true drive.
       def init_drives
-        @drive = nil
+        @dos = nil
         @serial_trap = nil
         @save_trap = nil
         @drive1541 = nil
@@ -61,7 +61,7 @@ module Badline
       # A 1581 plugged in holds the machine's on_init handlers back until
       # its DOS has booted, which takes longer than the C128 KERNAL's.
       def drive1581_attached
-        @init_threshold = [@init_threshold, Drive1581::BOOT_CYCLES].max if @cycles < @init_threshold
+        @init_threshold = [@init_threshold, Badline::Drives::Model1581::BOOT_CYCLES].max if @cycles < @init_threshold
       end
 
       # Unplugs the 1541 and the 1571 if either is device 8, for a 1581 to
@@ -72,36 +72,16 @@ module Badline
         detach_drive1571 if @drive1571&.device == device
       end
 
-      # A true 1541 (Computer::Attachments#save_serial_bus), then a 1571 and
-      # a 1581.
-      def save_serial_bus(out)
-        out.boolean(true).boolean(!@drive1541.nil?)
-        if @drive1541
-          out.int(@drive1541.device)
-          @drive1541.save_state(out)
-        end
-        out.boolean(!@drive1571.nil?)
-        if @drive1571
-          out.int(@drive1571.device)
-          @drive1571.save_state(out)
-        end
-        save_drive1581(out)
+      def save_drive1571_modules(sections)
+        drive1571 = @drive1571
+        drive1571&.save_modules(sections, "BL-D#{drive1571.device}")
+        sections
       end
 
-      def load_serial_bus(input)
-        input.boolean?
-        load_drive1541(input)
-        load_drive1571(input)
-        load_drive1581(input)
-      end
-
-      def load_drive1571(input)
-        return detach_drive1571 unless input.boolean?
-
-        device = input.int
+      def load_drive1571_modules(modules, input, device)
         detach_drive1571 if @drive1571 && @drive1571.device != device
-        attach_drive1571(Drive1571.new(device:)) unless @drive1571
-        @drive1571.load_state(input)
+        attach_drive1571(Badline::Drives::Model1571.new(device:)) unless @drive1571
+        @drive1571.load_modules(modules, input, "BL-D#{device}")
       end
     end
   end

data/lib/badline/c128/fast_serial.rb

@@ -6,7 +6,7 @@ module Badline
     # through buffers MCR's FSDIR turns round. Outwards, the machine pushes
     # the lines the pins pull into the bus as they move. Inwards, CIA 1
     # hears the lines whenever a drive moves its own fast serial pins
-    # (IECBus#on_fast_change).
+    # (Drives::SerialBus#on_fast_change).
     module FastSerial
       private
 
@@ -48,15 +48,15 @@ module Badline
         serial = @cia1.serial
         return 0 unless serial.output?
 
-        low = serial.cnt ? 0 : IECBus::SRQ
-        serial.sp_out ? low : low | IECBus::DATA
+        low = serial.cnt ? 0 : Badline::Drives::SerialBus::SRQ
+        serial.sp_out ? low : low | Badline::Drives::SerialBus::DATA
       end
 
       def hear_fast_serial
         low = @iec_bus.low_lines
         serial = @cia1.serial
-        serial.cnt_in = low.nobits?(IECBus::SRQ)
-        serial.sp_in = low.nobits?(IECBus::DATA)
+        serial.cnt_in = low.nobits?(Badline::Drives::SerialBus::SRQ)
+        serial.sp_in = low.nobits?(Badline::Drives::SerialBus::DATA)
       end
     end
   end

data/lib/badline/c128/keyed_modules.rb

@@ -0,0 +1,117 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The whole machine as keyed snapshot modules (Snapshot::Keyed), in the
+    # order a load applies them, as C64::KeyedModules: BL-MACHINE with the
+    # last bus access under bus.*, the RAM, both banks of colour RAM, the
+    # MMU, the cartridge, the 8502 with its port, the Z80, the chips, the
+    # datasette, device 8 through the traps and the true drives. The
+    # machine's own fields load after the Z80's, which z80_ahead counts
+    # from.
+    module KeyedModules
+      def save_modules
+        bus = @bus
+        sections = [Snapshot::Keyed.section("BL-MACHINE") do |out|
+          save_machine_fields(out)
+          bus.save_fields(out, "bus.")
+        end]
+        sections << Snapshot::Keyed.section("BL-RAM") { |out| bus.ram.save_fields(out, "ram") }
+        sections << Snapshot::Keyed.section("BL-COLORRAM") { |out| bus.save_color_fields(out) }
+        sections << Snapshot::Keyed.section("BL-MMU") { |out| bus.mmu.save_fields(out) }
+        cartridge = bus.cartridge
+        sections << Snapshot::Keyed.section("BL-CART") { |out| cartridge.save_fields(out) } if cartridge
+        save_chip_modules(sections, bus)
+        sections << Snapshot::Keyed.section("BL-TAPE") { |out| bus.datasette.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-TRAPDOS") { |out| save_trap_dos_fields(out) } if mounted?
+        save_drive_modules(sections)
+      end
+
+      # Raises Snapshot::FormatError for the modules of another model, SID
+      # or mode.
+      def load_modules(modules)
+        machine = modules.machine
+        check_snapshot_setup(Snapshot::C128Setup.read_fields(machine))
+        bus = @bus
+        bus.ram.load_fields(modules.required("BL-RAM"), "ram")
+        bus.load_color_fields(modules.required("BL-COLORRAM"))
+        bus.mmu.load_fields(modules.required("BL-MMU"))
+        load_cartridge_module(modules.optional("BL-CART"))
+        load_chip_modules(modules)
+        bus.load_fields(machine, "bus.")
+        load_machine_fields(machine)
+        bus.datasette.load_fields(modules.required("BL-TAPE"))
+        trap_dos = modules.optional("BL-TRAPDOS")
+        trap_dos ? load_trap_dos_fields(trap_dos, detached: modules.detached?) : unmount
+        load_drive_modules(modules)
+        modules_restored!
+        self
+      end
+
+      private
+
+      def save_chip_modules(sections, bus)
+        sections << Snapshot::Keyed.section("BL-CPU") do |out|
+          @cpu.save_fields(out)
+          bus.save_port_fields(out)
+        end
+        sections << Snapshot::Keyed.section("BL-Z80") { |out| @z80.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-VIC") { |out| @vic.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-VDC") { |out| @vdc.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-CIA1") { |out| @cia1.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-CIA2") { |out| @cia2.save_fields(out) }
+        sections << Snapshot::Keyed.section("BL-SID") { |out| @sid.save_fields(out) }
+      end
+
+      # The port goes in ahead of the chips, as the C64's does, and the bus
+      # maps its banks and the keyboard's extra rows once they are in. That
+      # hands the bus to the CPU the MMU names, which resets the Z80's
+      # schedule and can reset the 8502, so the CPUs, the last bus access
+      # and the machine's own fields load after it.
+      def load_chip_modules(modules)
+        cpu = modules.required("BL-CPU")
+        @bus.load_port_fields(cpu)
+        @vic.load_fields(modules.required("BL-VIC"))
+        @vdc.load_fields(modules.required("BL-VDC"))
+        @cia1.load_fields(modules.required("BL-CIA1"))
+        @cia2.load_fields(modules.required("BL-CIA2"))
+        @sid.load_fields(modules.required("BL-SID"))
+        @bus.restored!
+        @cpu.load_fields(cpu)
+        @z80.load_fields(modules.required("BL-Z80"))
+      end
+
+      # The cartridge comes back built afresh from the CRT image the module
+      # holds, before its state goes in. No module means no cartridge.
+      def load_cartridge_module(input)
+        if input
+          cartridge = C64::Cartridge.from_fields(input)
+          connect_cartridge(cartridge)
+          cartridge.load_fields(input)
+        elsif @bus.cartridge
+          @bus.detach_cartridge
+        end
+      end
+
+      def modules_restored!
+        @cpu.restored!
+        @z80.restored!
+        @vic.restored!
+        @vdc.restored!
+        @cia1.restored!
+        @cia2.restored!
+        @sid.restored!
+        machine_restored!
+      end
+
+      def check_snapshot_setup(setup)
+        ours = snapshot_setup
+        return if setup == ours
+
+        raise Snapshot::FormatError, "the snapshot is of a #{setup}, not a #{ours}"
+      end
+    end
+
+    include KeyedModules
+  end
+end

data/lib/badline/c128/keyed_state.rb

@@ -0,0 +1,91 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The machine's own fields in a keyed snapshot module (Snapshot::Keyed,
+    # BL-MACHINE): the family, its model, SID and mode by name, the cycle
+    # count, $D030's clock bits on their way, the NMI glue, the two
+    # schedulers' offsets (z80_ahead, the Z80's T-states past when it was
+    # due, and chips_ahead), an 8502 reset waiting for the bus, and under
+    # host.* the host's typing (the codes still to type, whether it is
+    # typing, and where Input::MatrixTypist is in a code on the key
+    # matrix), C= held from power-on and the on_init handlers still to run.
+    # They load after the Z80's own fields, which z80_ahead counts from.
+    module KeyedState
+      # How many more on_init handlers the machine a snapshot was taken of had
+      # yet to run than this one has. Nil until the machine is restored.
+      attr_reader :init_handlers_lost
+
+      # Whether a snapshot saves now (Machine::Settling): the 8502 between
+      # instructions or jammed. While the Z80 runs, the 8502 waits at the
+      # boundary it handed the bus over at, and the Z80 runs whole
+      # instructions.
+      def settled_for_snapshot? = @cpu.boundary? || @cpu.jammed?
+
+      # The SID's deferred cycles and writes, run up to this cycle, and the
+      # VIC's sprite collisions latched up to the beam.
+      def settle_chips_for_snapshot
+        sid.catch_up!
+        @vic.fold_collisions!
+      end
+
+      def save_machine_fields(out)
+        out.text("family", "c128").text("written_by", VERSION)
+        snapshot_setup.write_fields(out)
+        out.int("cycles", @cycles).int("clock_bits", @clock_bits).bool("nmi_asserted", @nmi_asserted)
+        out.bool("cartridge_nmi", @cartridge_nmi).bool("restore_pulse", @restore_pulse)
+        out.int("z80_ahead", @z80.cycles - @z80_due).int("chips_ahead", @chips_ahead)
+        out.bool("cpu_reset_pending", @cpu_reset_pending)
+        pending = @pending_keys
+        out.ints("host.pending_keys", pending) if pending
+        out.bool("host.typing", !pending.nil?)
+        out.int("host.init_pending", @cycles <= init_threshold ? @init_handlers.length : 0)
+        out.bool("host.holding_commodore", @holding_commodore)
+        @typist.save_fields(out, "host.typist.")
+      end
+
+      def load_machine_fields(input)
+        @cycles = input.int("cycles", @cycles)
+        @clock_bits = input.int("clock_bits", @clock_bits)
+        @nmi_asserted = input.bool("nmi_asserted", @nmi_asserted)
+        @cartridge_nmi = input.bool("cartridge_nmi", @cartridge_nmi)
+        @restore_pulse = input.bool("restore_pulse", @restore_pulse)
+        @z80_due = @z80.cycles - input.int("z80_ahead", @z80.cycles - @z80_due)
+        @chips_ahead = input.int("chips_ahead", @chips_ahead)
+        @cpu_reset_pending = input.bool("cpu_reset_pending", @cpu_reset_pending)
+        pending = input.ints("host.pending_keys", [])
+        @pending_keys = input.bool("host.typing", !pending.empty?) ? pending.dup : nil
+        @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
+        load_holding_fields(input)
+        @typist.load_fields(input, "host.typist.")
+      end
+
+      # Which CPU has the bus and whose turn it is, from the MMU and the
+      # schedulers' offsets, and the serial bus's lines.
+      def machine_restored!
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running || @chips_ahead.positive?
+        push_serial_lines
+        push_fast_serial
+      end
+
+      private
+
+      # C= held from power-on until the machine reaches C64 mode
+      # (Modes#hold_commodore_key).
+      def load_holding_fields(input)
+        holding = input.bool("host.holding_commodore", @holding_commodore)
+        keyboard.release(:cbm) if @holding_commodore && !holding
+        keyboard.press(:cbm) if holding && !@holding_commodore
+        @holding_commodore = holding
+      end
+
+      # How this machine was built.
+      def snapshot_setup
+        Snapshot::C128Setup.new(model: @model.name, sid_model: @sid.model, mode: @c64_built ? :c64 : :c128)
+      end
+    end
+
+    include KeyedState
+  end
+end

data/lib/badline/c128/keys.rb

@@ -21,6 +21,11 @@ module Badline
         @bus.caps_lock = false
       end
 
+      # Pushes CAPS LOCK, down if it was up and up if it was down.
+      def push_caps_lock
+        @bus.caps_lock = !@bus.caps_lock
+      end
+
       # The 40/80 DISPLAY key locks down and up. The KERNAL reads it at reset
       # and starts the screen editor on the VDC's 80 columns while it is down.
       def press_display_key
@@ -30,6 +35,10 @@ module Badline
       def release_display_key
         @bus.mmu.display_key = false
       end
+
+      def push_display_key
+        @bus.mmu.display_key = !@bus.mmu.display_key
+      end
     end
   end
 end

data/lib/badline/c128/mmu.rb

@@ -151,16 +151,17 @@ module Badline
         end
       end
 
-      # The registers and the P0H and P1H writes waiting for P0L and P1L.
-      # The bus maps the restored registers once its own state is back.
-      def save_state(out)
-        out.ints(@registers).int(@p0h_latch).int(@p1h_latch)
+      # The registers and the page pointers' high bytes waiting for their
+      # low bytes, in a keyed snapshot module (Snapshot::Keyed). The bus
+      # maps its banks from them afterwards.
+      def save_fields(out)
+        out.bytes("registers", @registers).int("p0h_latch", @p0h_latch).int("p1h_latch", @p1h_latch)
       end
 
-      def load_state(input)
-        input.ints_into(@registers)
-        @p0h_latch = input.int
-        @p1h_latch = input.int
+      def load_fields(input)
+        input.bytes_into("registers", @registers)
+        @p0h_latch = input.masked("p0h_latch", @p0h_latch, 0x0f)
+        @p1h_latch = input.masked("p1h_latch", @p1h_latch, 0x0f)
       end
 
       # CR and the LCRs at $FF00-$FF04: an LCR reads its PCR.

data/lib/badline/c128/mmu_pages.rb

@@ -6,7 +6,7 @@ module Badline
       # What the MMU maps. For the CPU: the RAM bank, common RAM and the
       # pages page 0 and page 1 move to in both modes, and CR's ROMs and I/O
       # in C128 mode. C64 mode lays the PLA's ROMs and I/O over the same RAM
-      # (AddressBus::PLA).
+      # (C64::Bus::PLA).
       module MMUPages
         private
 
@@ -46,6 +46,26 @@ module Badline
           end
         end
 
+        # The system ROM's byte at +addr+, $8000 or above, as CR value 0 maps it.
+        def system_rom_peek(addr)
+          if addr < 0xc000
+            @basic_high_rom.peek(addr)
+          elsif addr < 0xd000
+            @editor_rom.peek(addr)
+          elsif addr < 0xe000
+            @c128_character_rom.peek(addr)
+          else
+            @c128_kernal_rom.peek(addr)
+          end
+        end
+
+        # The chip's byte at +addr+, in $D000-$DFFF, as C128 mode's I/O maps it.
+        def bank_io_peek(addr)
+          lay_out_io(@bank_io_reads, @bank_io_writes)
+          @bank_io_reads[0xd5] = @mmu
+          @bank_io_reads[addr >> 8].peek(addr)
+        end
+
         # The bank CR picks, with common RAM in bank 0, then the pages page 0
         # and page 1 move to.
         def map_ram_pages

data/lib/badline/c128/modes.rb

@@ -33,7 +33,7 @@ module Badline
       def mode_changed
         layout = trap_layout
         @capture_output&.layout = layout
-        if @drive
+        if @dos
           remove_kernal_traps
           install_kernal_traps(layout)
         end
@@ -41,20 +41,30 @@ module Badline
 
         keyboard.release(:cbm)
         @holding_commodore = false
-        @init_threshold = @cycles + Computer::INIT_THRESHOLD if @cycles < @init_threshold
+        @init_threshold = @cycles + C64::INIT_THRESHOLD if @cycles < @init_threshold
       end
 
       # The keyboard buffer of the KERNAL the machine runs: the C64's, or in
       # C128 mode BASIC 7.0's.
-      def feed_keyboard
-        c64 = mode == :c64
-        count = c64 ? KeyboardBuffer::COUNT : C128_KEYBOARD_COUNT
-        return unless ram.peek(count).zero?
-
-        chunk = @pending_keys.shift(KeyboardBuffer::CAPACITY)
-        ram.write(c64 ? KeyboardBuffer::ADDRESS : C128_KEYBOARD_BUFFER, chunk)
-        ram.poke(count, chunk.length)
-        @pending_keys = nil if @pending_keys.empty?
+      def keyboard_buffer
+        mode == :c64 ? Machine::KeyboardBuffer::C64_LAYOUT : Machine::KeyboardBuffer::C128_LAYOUT
+      end
+
+      # Types the text type_text left: into the keyboard buffer, or while
+      # the Z80 runs, as under CP/M, where no KERNAL reads the buffer, on
+      # the key matrix, all of it once begun there.
+      def type_pending
+        if @z80_running || @typist.typing?
+          type_on_matrix
+        else
+          feed_keyboard
+        end
+      end
+
+      def type_on_matrix
+        pending = @pending_keys
+        @typist.cycle!(pending)
+        @pending_keys = nil if pending.empty? && !@typist.typing?
       end
     end
   end

data/lib/badline/c128/z80.rb

@@ -1,12 +1,12 @@
 # frozen_string_literal: true
 
-require "badline/z80/core"
+require "badline/chips/z80/core"
 
 module Badline
   class C128
     # The C128's Z80A, on the Z80's side of the C128::Bus.
     class Z80
-      include Badline::Z80::Core
+      include Badline::Chips::Z80::Core
     end
 
     # The Z80's accesses, through the pages C128::Bus lays out for it

data/lib/badline/c128/z80_turns.rb

@@ -58,7 +58,7 @@ module Badline
       # interrupt lines going to the Z80.
       def clock_chips
         handle_init if @cycles == @init_threshold
-        feed_keyboard if @pending_keys
+        type_pending if @pending_keys
 
         clock_bits = @clock_bits
         @clock_bits = @vic.clock_bits