badline 0.12.1 → 0.14.0

data/lib/badline/drive1541/sector_reader.rb

@@ -1,76 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1541
-    # Reads a track's blocks back out of its GCR, as the DOS finds them:
-    # each SYNC mark is ten or more 1 bits, and the block after it starts
-    # at the first 0 bit. Writes land wherever the head was, so a block
-    # can start at any bit of the stored bytes, and the reader works on
-    # the bits.
-    #
-    # A header block starts with $08, and the next block after a header is
-    # that sector's data block, whatever it holds.
-    module SectorReader
-      HEADER_BITS = 10 * 8
-      DATA_BITS = 325 * 8
-      SYNC = /1{10,}/
-
-      # A sector as read: its decoded header, [ID, checksum, sector, track,
-      # the second ID byte, the first, ...], and its decoded data block,
-      # [ID, 256 data bytes, checksum, ...], nil when there isn't one that
-      # decodes.
-      Sector = Struct.new(:header, :data)
-
-      module_function
-
-      # The sectors found on the track's bytes, by sector number. Headers
-      # for another track are left out.
-      def read(bytes, track)
-        ring = ring(bytes)
-        return {} unless ring
-
-        sectors = {}
-        each_block(ring) do |header, data|
-          next unless header[3] == track
-
-          sectors[header[2]] ||= Sector.new(header, data)
-        end
-        sectors
-      end
-
-      # The track's bits, starting at a 0 bit so no SYNC mark straddles the
-      # start, twice over so a block can run on past the end. Nil for a
-      # track without a 0 bit.
-      def ring(bytes)
-        bits = bytes.pack("C*").unpack1("B*")
-        zero = bits.index("0")
-        return unless zero
-
-        bits = bits[zero..] + bits[0, zero]
-        [bits * 2, bits.length]
-      end
-
-      # Yields each header whose SYNC mark starts in the first turn, with
-      # the data block after it.
-      def each_block(ring)
-        bits, length = ring
-        pos = 0
-        while (sync = SYNC.match(bits, pos)) && sync.begin(0) < length
-          pos = sync.end(0)
-          header = decode(bits, pos, HEADER_BITS)
-          next unless header && header[0] == Disk::HEADER_ID
-
-          data_sync = SYNC.match(bits, pos + HEADER_BITS)
-          yield header, data_sync && decode(bits, data_sync.end(0), DATA_BITS)
-        end
-      end
-
-      def decode(bits, pos, count)
-        slice = bits[pos, count]
-        return unless slice.length == count
-
-        GCR.decode([slice].pack("B*").bytes)
-      end
-    end
-  end
-end

data/lib/badline/drive1541/serial_port.rb

@@ -1,18 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1541
-    # What VIA 1's ports read from outside the chip. Port B carries the
-    # serial bus inputs and the device number jumpers (Drive::SerialLines);
-    # port A goes to the unused parallel header and floats high.
-    class SerialPort
-      include Drive::SerialLines
-
-      def initialize(device: 8, bus: IECBus.new)
-        init_serial_lines(device, bus)
-      end
-
-      def read_a(_lines) = 0xff
-    end
-  end
-end

data/lib/badline/drive1541/track.rb

@@ -1,98 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1541
-    # One ring of flux on the disk, as the GCR bytes the head reads from it,
-    # most significant bit first, and the speed zone it was written in
-    # (0-3). The bytes wrap around: the last one's bits run into the
-    # first's. A track is as long as its bytes, which is what a .g64 image
-    # stores for each half track.
-    #
-    # The disk turns at 300 rpm, so every track passes under the head in
-    # the same 200 ms, and its bits pass at the rate they were written at.
-    # Each bit is a cell of time, starting at the track's index angle with
-    # the first byte's top bit, and a 1 bit is a flux transition at the
-    # start of its cell. The cells are spread evenly over the turn, so a
-    # track as long as a turn holds at its zone's rate
-    # (Disk::TRACK_LENGTHS) passes at that rate, within the part of a byte
-    # the length rounds off, and a longer or shorter one faster or slower.
-    # A .g64 speed map gives each byte the zone it was written in, and the
-    # cells of each byte are as wide as their zone's, scaled together to
-    # fill the turn.
-    #
-    # Times are in TICKs, 1/65536 of a tick of the drive's 16 MHz crystal,
-    # so the cells add up to a turn within a tick.
-    class Track
-      TICK = 1 << 16
-      TURN = 200_000 * 16 * TICK
-
-      # A bit cell at the zone's rate, in TICKs.
-      def self.cell(zone) = 4 * (16 - zone) * TICK
-
-      attr_reader :bytes, :zone, :speeds, :width, :widths
-
-      # +speeds+ holds each byte's zone, where the track's rate changes
-      # along it.
-      def initialize(bytes, zone, speeds = nil)
-        @bytes = bytes
-        @zone = zone
-        @speeds = speeds
-        @widths = speeds && scaled_widths(speeds)
-        @width = speeds ? @widths[0] : TURN / (bytes.length * 8)
-      end
-
-      def length = @bytes.length
-
-      # Whether the whole track was written at the +zone+'s rate.
-      def written_at?(zone) = @widths.nil? && @zone == zone
-
-      # The bit cell under the head +time+ TICKs into the turn, as
-      # [byte, mask, the time the cell ends].
-      def cell_at(time)
-        start = 0
-        index = 0
-        if @widths
-          while index < length - 1 && time >= start + (@widths[index] * 8)
-            start += @widths[index] * 8
-            index += 1
-          end
-        else
-          index = [time / (@width * 8), length - 1].min
-          start = index * @width * 8
-        end
-        width = @widths ? @widths[index] : @width
-        bit = [(time - start) / width, 7].min
-        cell_end = index == length - 1 && bit == 7 ? TURN : start + ((bit + 1) * width)
-        [index, 0x80 >> bit, cell_end]
-      end
-
-      # The track laid out again as one turn at the +zone+'s rate, each
-      # flux transition in the cell under it.
-      def relaid(zone)
-        bits = Disk::TRACK_LENGTHS[zone] * 8
-        cell = TURN / bits
-        relaid = Array.new(bits / 8, 0)
-        time = 0
-        @bytes.each_with_index do |byte, index|
-          width = @widths ? @widths[index] : @width
-          8.times do |bit|
-            if byte.anybits?(0x80 >> bit)
-              cell_index = [time / cell, bits - 1].min
-              relaid[cell_index >> 3] |= 0x80 >> (cell_index & 7)
-            end
-            time += width
-          end
-        end
-        Track.new(relaid, zone)
-      end
-
-      private
-
-      def scaled_widths(speeds)
-        units = 0
-        speeds.each { |zone| units += 16 - zone }
-        speeds.map { |zone| TURN * (16 - zone) / (units * 8) }
-      end
-    end
-  end
-end

data/lib/badline/drive1541.rb

@@ -1,111 +0,0 @@
-# frozen_string_literal: true
-
-require "badline/drive"
-require "badline/drive1541/bus"
-require "badline/drive1541/cpu"
-require "badline/drive1541/serial_port"
-require "badline/drive1541/gcr"
-require "badline/drive1541/track"
-require "badline/drive1541/disk"
-require "badline/drive1541/mechanism"
-require "badline/drive1541/disk_via"
-
-module Badline
-  # The 1541 disk drive as a machine of its own: a 6502 running the DOS
-  # ROM at 1 MHz, with 2 KB of RAM and two VIAs on its bus. Drive::Core
-  # clocks it against the host and sleeps through the DOS's idle loop.
-  class Drive1541
-    include Drive::Core
-    include Drive::VIAs
-
-    CLOCK_HZ = 1_000_000
-
-    # Where the DOS 2.6 idle loop starts over (see Drive::Idle).
-    IDLE_LOOP = 0xebff
-
-    def model_name = "1541"
-
-    # +rom+ covers $C000-$FFFF, and defaults to the DOS image in the ROM
-    # path. +device+ is the number the jumpers on VIA 1's PB5 and PB6 set,
-    # 8 to 11.
-    def initialize(rom: nil, host_clock_hz: CLOCK_HZ, device: 8, debug: false)
-      @device = device
-      @serial_port = SerialPort.new(device:)
-      @via1 = VIA.new(start: 0x1800, peripheral: @serial_port)
-      @mechanism = Mechanism.new
-      @via2 = DiskVIA.new(start: 0x1c00, mechanism: @mechanism)
-      @bus = Bus.new(rom: rom || ROM.load("dos1541.rom", 0xc000), via1: @via1, via2: @via2)
-      @cpu = CPU.new(@bus, debug:)
-      @clock_hz = CLOCK_HZ
-      @idle_loop = IDLE_LOOP
-      @host_clock_hz = host_clock_hz
-      @phase = 0
-      @cycles = 0
-      @serial_bus = nil
-      init_idle(debug)
-      # CA1 powers up at the level of a released ATN, without an edge.
-      @via1.ca1 = false
-      @via1.reset!
-      connect(IECBus.new)
-    end
-
-    # The drive's whole state: its clock phase, the CPU, RAM, both VIAs,
-    # the serial port's latch of the C64's lines and the mechanism with its
-    # disk. The drive settles first, so it is awake and not recording a
-    # pass, and a restored drive starts the same way, its orbits forgotten
-    # from the state it takes: Idle's and Orbit's bookkeeping
-    # isn't stored. The device number, the host's clock rate and whether
-    # the drive may sleep are the machine's wiring.
-    def save_state(out)
-      settle!
-      out.marker("DRIVE1541")
-      out.int(@phase).int(@cycles).boolean(@mechanism.so_pending)
-      @serial_port.save_state(out)
-      @via1.save_state(out)
-      @via2.save_state(out)
-      @bus.save_state(out)
-      @cpu.save_state(out)
-      @mechanism.save_state(out)
-    end
-
-    def load_state(input)
-      settle!
-      input.marker("DRIVE1541")
-      @phase = input.int
-      @cycles = input.int
-      @mechanism.so_pending = input.boolean?
-      @serial_port.load_state(input)
-      @via1.load_state(input)
-      @via2.load_state(input)
-      @bus.load_state(input)
-      @cpu.load_state(input)
-      @mechanism.load_state(input)
-      forget_orbits
-    end
-
-    private
-
-    # One drive cycle. The VIAs clock ahead of the CPU, as the C64's chips
-    # do, and either one pulls IRQ. Nothing drives NMI on the 1541. The CPU
-    # runs whether or not the motor turns, since it answers ATN.
-    #
-    # The disk mechanism runs first, so BYTE READY lands on the VIA ahead
-    # of the CPU's cycle. The CPU samples SO a cycle late: BYTE READY sets
-    # V for the next cycle's instruction step.
-    #
-    # ATN reaches VIA 1's CA1 through the same inverter as PB7, so CA1 goes
-    # high as the C64 asserts ATN, as the serial port sees it: from the
-    # host cycle after the one that asserts it.
-    def step
-      so = @mechanism.take_so
-      @mechanism.cycle!
-      @via1.ca1 = @serial_port.atn_low?
-      @via1.cycle!
-      @via2.cycle!
-      @cpu.irq = @via1.irq? || @via2.irq?
-      @cpu.so! if so
-      @cpu.cycle!
-      @cycles += 1
-    end
-  end
-end

data/lib/badline/drive1571/bus.rb

@@ -1,111 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1571
-    # The drive CPU's bus:
-    #
-    # $0000-$07FF - 2 KB of RAM
-    # $0800-$17FF - nothing: open bus
-    # $1800-$1BFF - VIA 1, its sixteen registers mirrored
-    # $1C00-$1FFF - VIA 2, its sixteen registers mirrored
-    # $2000-$3FFF - the WD1770, its four registers mirrored
-    # $4000-$7FFF - the CIA, its sixteen registers mirrored
-    # $8000-$FFFF - the DOS ROM
-    #
-    # Writes to the ROM and to open bus go nowhere, and a read from open
-    # bus finds the last byte on the data bus, as on the 1541. Any access
-    # to VIA 2 clears the BYTE READY latch VIA 1's PA7 reads (SerialPort).
-    #
-    # While Idle records a pass of the DOS's idle loop, the bus watches it,
-    # and while Idle looks for an orbit, it guards the drive (see
-    # Drive::Watch). Any access to the CIA or the WD1770 makes the pass
-    # volatile and taints the drive.
-    class Bus
-      include Addressable
-      include Drive::Watch
-
-      attr_reader :ram, :rom, :via1, :via2, :cia, :fdc, :data
-
-      def initialize(rom:, via1:, via2:, cia:, fdc:)
-        addressable_at(0, length: 2**16)
-        @ram = Memory.new([], length: 0x0800, start: 0)
-        @rom = rom
-        @via1 = via1
-        @via2 = via2
-        @cia = cia
-        @fdc = fdc
-        @mechanism = via2.mechanism
-        @data = 0
-        init_watch
-      end
-
-      # The last byte on the data bus and the RAM. What a watched stretch
-      # touched is Idle's, and a restored bus isn't watching.
-      def save_state(out)
-        out.int(@data)
-        @ram.save_state(out)
-      end
-
-      def load_state(input)
-        @data = input.int
-        @ram.load_state(input)
-        @watching = false
-      end
-
-      def peek(addr)
-        return @data = @rom.peek(addr) if addr >= 0x8000
-        return @data = chip_peek(addr) if addr >= 0x2000
-
-        watch_read(addr) if @watching
-        @data = if addr < 0x0800
-                  @ram.peek(addr)
-                elsif addr < 0x1800
-                  @data
-                elsif addr < 0x1c00
-                  @via1.peek(addr)
-                else
-                  @mechanism.release_byte_latch
-                  @via2.peek(addr)
-                end
-      end
-
-      def poke(addr, value)
-        @data = value
-        return if addr >= 0x8000
-        return chip_poke(addr, value) if addr >= 0x2000
-
-        low_poke(addr, value)
-      end
-
-      private
-
-      # A write below $2000: RAM or a VIA.
-      def low_poke(addr, value)
-        if addr < 0x0800
-          touch(addr) if @recording
-          @ram.poke(addr, value)
-        elsif addr >= 0x1c00
-          @mechanism.release_byte_latch
-          @via2.poke(addr, value)
-        elsif addr >= 0x1800
-          @via1.poke(addr, value)
-        end
-        watch_write(addr) if @watching
-      end
-
-      def chip_peek(addr)
-        watch_chip if @watching
-        addr >= 0x4000 ? @cia.peek(0x4000 | (addr & 0x0f)) : @fdc.peek(addr & 0x03)
-      end
-
-      def chip_poke(addr, value)
-        if addr >= 0x4000
-          @cia.poke(0x4000 | (addr & 0x0f), value)
-        else
-          @fdc.poke(addr & 0x03, value)
-        end
-        watch_chip if @watching
-      end
-    end
-  end
-end

data/lib/badline/drive1571/cpu.rb

@@ -1,11 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1571
-    # The drive's 6502, on the drive's Bus.
-    class CPU
-      include Badline::CPU::Core
-      include Drive::IdleCPU
-    end
-  end
-end

data/lib/badline/drive1571/serial_port.rb

@@ -1,37 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1571
-    # What VIA 1's ports read from outside the chip. Port B carries the
-    # serial bus inputs and the device number jumpers, as on the 1541
-    # (Drive::SerialLines). Port A reads the mechanism on two inputs:
-    #
-    #   PA0  track 0 sensor, low while the head sits on track 1
-    #   PA7  BYTE READY, latched low from a whole byte until the CPU next
-    #        reads or writes VIA 2
-    #
-    # The DOS steps the head out until PA0 reads low with the stepper on
-    # phase 0, and polls PA7 for each byte at 2 MHz, taking the byte from
-    # VIA 2's port A or putting the next one there after each. PA1 (fast serial
-    # direction), PA2 (side) and PA5 (1 or 2 MHz) are outputs, which
-    # Drive1571 follows (SerialVIA).
-    class SerialPort
-      include Drive::SerialLines
-
-      TRACK0 = 0x01
-      BYTE_READY = 0x80
-
-      def initialize(mechanism, device: 8, bus: IECBus.new)
-        @mechanism = mechanism
-        init_serial_lines(device, bus)
-      end
-
-      def read_a(_lines)
-        value = 0xff
-        value &= ~TRACK0 if @mechanism.half_track == Drive1541::Mechanism::MIN_HALF_TRACK
-        value &= ~BYTE_READY if @mechanism.byte_latched?
-        value
-      end
-    end
-  end
-end

data/lib/badline/drive1571/serial_via.rb

@@ -1,25 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1571
-    # VIA 1, the one facing the serial bus. Its port A also selects the
-    # side, the clock rate and the fast serial direction, so the drive
-    # hears port A after every write and reset (Drive1571#port_a_written).
-    class SerialVIA < VIA
-      def initialize(start:, peripheral:, drive:)
-        @drive = drive
-        super(start:, peripheral:)
-      end
-
-      def reset!
-        super
-        @drive.port_a_written(port_a_output)
-      end
-
-      def poke(addr, value)
-        super
-        @drive.port_a_written(port_a_output)
-      end
-    end
-  end
-end

data/lib/badline/drive1571/wd1770.rb

@@ -1,120 +0,0 @@
-# frozen_string_literal: true
-
-module Badline
-  class Drive1571
-    # The WD1770 floppy controller at $2000, which DOS 3.0 drives for MFM
-    # disks. The 1571 here only ever holds GCR disks, so the controller
-    # never finds an MFM sector: it runs each command for its time and ends
-    # it as the WD177x data sheet does on a disk without one.
-    #
-    #   $2000  status (read), command (write)
-    #   $2001  track
-    #   $2002  sector
-    #   $2003  data
-    #
-    # BUSY sets as a command is written. A restore, seek or step (type I)
-    # moves the track register and ends a few milliseconds later, with
-    # TRACK 0 reported at track 0. A sector read or write, a read address
-    # or a read track ends with RECORD NOT FOUND after five turns of the
-    # disk, and a write track after one, with nothing written. A force
-    # interrupt ends the command at once. Time is the drive CPU's cycles.
-    class WD1770
-      BUSY = 0x01
-      TRACK0 = 0x04
-      NOT_FOUND = 0x10
-      MOTOR_ON = 0x80
-
-      # Cycles at 2 MHz, the 1571's clock in 1571 mode: a turn of the disk
-      # at 300 rpm, and a step with the head settling.
-      TURN = 400_000
-      STEP = 12_000
-
-      # The CPU whose cycles time the commands.
-      attr_writer :cpu
-
-      def initialize
-        @registers = [0, 0, 0, 0]
-        @status = 0
-        @due = 0
-        @result = 0
-        @cpu = nil
-      end
-
-      # Register +offset+, 0 to 3: the status, settled to the command's end
-      # once its time has run out.
-      def peek(offset)
-        return @registers[offset] unless offset.zero?
-
-        finish if @status.anybits?(BUSY) && @cpu.cycles >= @due
-        @status
-      end
-
-      def poke(offset, value)
-        offset.zero? ? command(value) : @registers[offset] = value
-      end
-
-      def save_state(out)
-        out.ints([*@registers, @status, @due, @result])
-      end
-
-      # A state from before the controller ran commands holds the four
-      # registers alone.
-      def load_state(input)
-        values = input.ints
-        @registers = values[0, 4]
-        @status = values[4] || 0
-        @due = values[5] || 0
-        @result = values[6] || 0
-      end
-
-      private
-
-      def command(value)
-        return interrupt if (value & 0xf0) == 0xd0
-
-        @registers[0] = value
-        value < 0x80 ? step(value) : search(value)
-      end
-
-      # A restore ($0x), seek ($1x) or step ($2x to $7x), its track register
-      # moved at once.
-      def step(value)
-        track = @registers[1]
-        target = case value >> 4
-                 when 0 then 0
-                 when 1 then @registers[3]
-                 else track + step_direction(value)
-                 end
-        @registers[1] = target.clamp(0, 255) if value < 0x20 || value.anybits?(0x10)
-        start(STEP * [(target - track).abs, 1].max, @registers[1].zero? ? TRACK0 : 0)
-      end
-
-      # Step in ($4x) moves toward higher tracks, step out ($6x) toward
-      # track 0, and step ($2x) the way the last one went.
-      def step_direction(value)
-        @direction = 1 if (value >> 5) == 2
-        @direction = -1 if (value >> 5) == 3
-        @direction || 1
-      end
-
-      # A sector or track command that finds no MFM sector.
-      def search(value)
-        value >= 0xf0 ? start(TURN, 0) : start(TURN * 5, NOT_FOUND)
-      end
-
-      def start(cycles, result)
-        @status = BUSY | MOTOR_ON
-        @due = @cpu.cycles + cycles
-        @result = result
-      end
-
-      def finish
-        @status = @result
-      end
-
-      def interrupt
-        @status &= ~BUSY & 0xff
-      end
-    end
-  end
-end