badline 0.12.1 → 0.14.0

data/lib/badline/chips/cpu/instruction_set/bitwise.rb

@@ -0,0 +1,130 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Bitwise
+          # Performs bitwise AND on accumulator with memory.
+          #
+          # Opcodes:
+          #   $21 - indirect_x - 6 cycles
+          #   $25 - zeropage   - 3 cycles
+          #   $29 - immediate  - 2 cycles
+          #   $2D - absolute   - 4 cycles
+          #   $31 - indirect_y - 5+ cycles
+          #   $35 - zeropage_x - 4 cycles
+          #   $39 - absolute_y - 4+ cycles
+          #   $3D - absolute_x - 4+ cycles
+          def and(_addr, value)
+            @a &= value
+            update_number_flags(@a)
+          end
+
+          # Arithmetic shift left. Shifts bits left by one position.
+          #
+          # Opcodes:
+          #   $06 - zeropage   - 5 cycles
+          #   $0A - accumulator- 2 cycles
+          #   $0E - absolute   - 6 cycles
+          #   $16 - zeropage_x - 6 cycles
+          #   $1E - absolute_x - 7 cycles
+          def asl(addr, value)
+            result = (value << 1) & 0xff
+            status.carry = value[7]
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+
+          # Tests bits in memory with accumulator.
+          #
+          # Opcodes:
+          #   $24 - zeropage - 3 cycles
+          #   $2C - absolute - 4 cycles
+          def bit(_addr, value)
+            status.value = ((status.value & 0b00111111) +
+                            (value & 0b11000000)).to_i
+            status.zero = (a & value).nobits?(0xff)
+          end
+
+          # Performs bitwise XOR on accumulator with memory.
+          #
+          # Opcodes:
+          #   $41 - indirect_x - 6 cycles
+          #   $45 - zeropage   - 3 cycles
+          #   $49 - immediate  - 2 cycles
+          #   $4D - absolute   - 4 cycles
+          #   $51 - indirect_y - 5+ cycles
+          #   $55 - zeropage_x - 4 cycles
+          #   $59 - absolute_y - 4+ cycles
+          #   $5D - absolute_x - 4+ cycles
+          def eor(_addr, value)
+            @a = (@a ^ value) & 0xff
+            update_number_flags(@a)
+          end
+
+          # Logical shift right. Shifts bits right by one position.
+          #
+          # Opcodes:
+          #   $46 - zeropage   - 5 cycles
+          #   $4A - accumulator- 2 cycles
+          #   $4E - absolute   - 6 cycles
+          #   $56 - zeropage_x - 6 cycles
+          #   $5E - absolute_x - 7 cycles
+          def lsr(addr, value)
+            result = (value >> 1) & 0xff
+            status.carry = value[0]
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+
+          # Performs bitwise OR on accumulator with memory.
+          #
+          # Opcodes:
+          #   $01 - indirect_x - 6 cycles
+          #   $05 - zeropage   - 3 cycles
+          #   $09 - immediate  - 2 cycles
+          #   $0D - absolute   - 4 cycles
+          #   $11 - indirect_y - 5+ cycles
+          #   $15 - zeropage_x - 4 cycles
+          #   $19 - absolute_y - 4+ cycles
+          #   $1D - absolute_x - 4+ cycles
+          def ora(_addr, value)
+            @a |= value
+            update_number_flags(@a)
+          end
+
+          # Rotate left through carry.
+          #
+          # Opcodes:
+          #   $26 - zeropage   - 5 cycles
+          #   $2A - accumulator- 2 cycles
+          #   $2E - absolute   - 6 cycles
+          #   $36 - zeropage_x - 6 cycles
+          #   $3E - absolute_x - 7 cycles
+          def rol(addr, value)
+            result = ((value << 1) + status.carry) & 0xff
+            status.carry = value[7]
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+
+          # Rotate right through carry.
+          #
+          # Opcodes:
+          #   $66 - zeropage   - 5 cycles
+          #   $6A - accumulator- 2 cycles
+          #   $6E - absolute   - 6 cycles
+          #   $76 - zeropage_x - 6 cycles
+          #   $7E - absolute_x - 7 cycles
+          def ror(addr, value)
+            result = ((value >> 1) + (status.carry? ? 0x80 : 0)) & 0xff
+            status.carry = value[0]
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/branch.rb

@@ -0,0 +1,83 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Branch
+          # Branch if carry clear (C=0).
+          #
+          # Opcodes:
+          #   $90 - relative - 2+ cycles
+          def bcc(_addr, _value)
+            take_branch unless status.carry?
+          end
+
+          # Branch if carry set (C=1).
+          #
+          # Opcodes:
+          #   $B0 - relative - 2+ cycles
+          def bcs(_addr, _value)
+            take_branch if status.carry?
+          end
+
+          # Branch if equal (Z=1).
+          #
+          # Opcodes:
+          #   $F0 - relative - 2+ cycles
+          def beq(_addr, _value)
+            take_branch if status.zero?
+          end
+
+          # Branch if minus (N=1).
+          #
+          # Opcodes:
+          #   $30 - relative - 2+ cycles
+          def bmi(_addr, _value)
+            take_branch if status.negative?
+          end
+
+          # Branch if not equal (Z=0).
+          #
+          # Opcodes:
+          #   $D0 - relative - 2+ cycles
+          def bne(_addr, _value)
+            take_branch unless status.zero?
+          end
+
+          # Branch if plus (N=0).
+          #
+          # Opcodes:
+          #   $10 - relative - 2+ cycles
+          def bpl(_addr, _value)
+            take_branch unless status.negative?
+          end
+
+          # Branch if overflow clear (V=0).
+          #
+          # Opcodes:
+          #   $50 - relative - 2+ cycles
+          def bvc(_addr, _value)
+            take_branch unless status.overflow?
+          end
+
+          # Branch if overflow set (V=1).
+          #
+          # Opcodes:
+          #   $70 - relative - 2+ cycles
+          def bvs(_addr, _value)
+            take_branch if status.overflow?
+          end
+
+          private
+
+          # Marks the branch as taken. Operations#op_relative reads the flag
+          # and runs the extra cycles.
+          def take_branch
+            @branch_taken = true
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/flag.rb

@@ -0,0 +1,67 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Flag
+          # Clear carry flag.
+          #
+          # Opcodes:
+          #   $18 - implied - 2 cycles
+          def clc(_addr, _value)
+            status.carry = false
+          end
+
+          # Clear decimal mode flag.
+          #
+          # Opcodes:
+          #   $D8 - implied - 2 cycles
+          def cld(_addr, _value)
+            status.decimal = false
+          end
+
+          # Clear interrupt disable flag.
+          #
+          # Opcodes:
+          #   $58 - implied - 2 cycles
+          def cli(_addr, _value)
+            status.interrupt = false
+          end
+
+          # Clear overflow flag.
+          #
+          # Opcodes:
+          #   $B8 - implied - 2 cycles
+          def clv(_addr, _value)
+            status.overflow = false
+          end
+
+          # Set carry flag.
+          #
+          # Opcodes:
+          #   $38 - implied - 2 cycles
+          def sec(_addr, _value)
+            status.carry = true
+          end
+
+          # Set decimal mode flag.
+          #
+          # Opcodes:
+          #   $F8 - implied - 2 cycles
+          def sed(_addr, _value)
+            status.decimal = true
+          end
+
+          # Set interrupt disable flag.
+          #
+          # Opcodes:
+          #   $78 - implied - 2 cycles
+          def sei(_addr, _value)
+            status.interrupt = true
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/illegal.rb

@@ -0,0 +1,274 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        # Illegal opcodes
+        module Illegal
+          # Combination of AND and LSR.
+          #
+          # Opcodes:
+          #   $4B - immediate - 2 cycles
+          def alr(_addr, value)
+            @a &= value
+            status.carry = @a[0]
+            @a = (@a >> 1) & 0xff
+            update_number_flags(@a)
+          end
+
+          # Combination of AND where carry is set to bit 7 of result.
+          #
+          # Opcodes:
+          #   $0B, $2B - immediate - 2 cycles
+          def anc(addr, value)
+            self.and(addr, value)
+            status.carry = status.negative
+          end
+
+          # Unstable instruction. AND's value with A|magic_const and X.
+          # Magic constant varies by CPU. A VIC stall between the opcode and
+          # operand fetches clears its bits 0 and 4.
+          #
+          # Opcodes:
+          #   $8B - immediate - 2 cycles
+          def ane(_addr, value)
+            magic_const = stalled_before_this_cycle? ? @ane_constant & 0xee : @ane_constant
+            @a = (a | magic_const) & x & value
+            update_number_flags(@a)
+          end
+
+          # Combination of AND and ROR.
+          #
+          # Opcodes:
+          #   $6B - immediate - 2 cycles
+          def arr(_addr, value)
+            tmp = a & value
+            result = (tmp >> 1) | (status.carry? ? 0x80 : 0)
+            status.zero = result.zero?
+            status.negative = status.carry
+
+            if status.decimal?
+              status.overflow = (result ^ tmp).anybits?(0x40)
+
+              # Low nibble
+              result = (result & 0xf0) | ((result + 0x06) & 0x0f) if ((tmp & 0x0f) + (tmp & 0x01)) > 0x05
+
+              # High nibble + carry
+              if ((tmp & 0xf0) + (tmp & 0x10)) > 0x50
+                result = (result & 0x0f) | ((result + 0x60) & 0xf0)
+                status.carry = true
+              else
+                status.carry = false
+              end
+            else
+              status.carry = tmp[7] == 1
+              status.overflow = tmp[7] ^ tmp[6]
+            end
+
+            @a = result
+          end
+
+          # Combination of DEC and CMP operations.
+          #
+          # Opcodes:
+          #   $C3 - indirect_x - 8 cycles
+          #   $C7 - zeropage   - 5 cycles
+          #   $CF - absolute   - 6 cycles
+          #   $D3 - indirect_y - 8 cycles
+          #   $D7 - zeropage_x - 6 cycles
+          #   $DB - absolute_y - 7 cycles
+          #   $DF - absolute_x - 7 cycles
+          def dcp(addr, value)
+            cmp(addr, dec(addr, value))
+          end
+
+          # Combination of INC and SBC operations.
+          #
+          # Opcodes:
+          #   $E3 - indirect_x - 8 cycles
+          #   $E7 - zeropage   - 5 cycles
+          #   $EF - absolute   - 6 cycles
+          #   $F3 - indirect_y - 8 cycles
+          #   $F7 - zeropage_x - 6 cycles
+          #   $FB - absolute_y - 7 cycles
+          #   $FF - absolute_x - 7 cycles
+          def isc(addr, value)
+            sbc(addr, inc(addr, value))
+          end
+
+          # Loads A and S with value AND stack pointer.
+          #
+          # Opcodes:
+          #   $BB - absolute_y - 4 cycles
+          def las(_addr, value)
+            @a = @x = @stack_pointer = value & stack_pointer
+            update_number_flags(@a)
+          end
+
+          # Combination of LDA and LDX with same value.
+          #
+          # Opcodes:
+          #   $A3 - indirect_x - 6 cycles
+          #   $A7 - zeropage   - 3 cycles
+          #   $AF - absolute   - 4 cycles
+          #   $B3 - indirect_y - 5+ cycles
+          #   $B7 - zeropage_y - 4 cycles
+          #   $BF - absolute_y - 4+ cycles
+          def lax(_addr, value)
+            @a = @x = value
+
+            update_number_flags(@a)
+          end
+
+          # Unstable immediate form of LAX. Loads A and X with
+          # (A | magic_const) AND value. Magic constant varies by CPU.
+          #
+          # Opcodes:
+          #   $AB - immediate - 2 cycles
+          def lxa(_addr, value)
+            magic_const = 0xee
+            @a = @x = (a | magic_const) & value
+            update_number_flags(@a)
+          end
+
+          # Special no-operation instruction that does not consume a CPU cycle,
+          # unlike the standard NOP. Used by some illegal opcodes.
+          #
+          # Opcodes:
+          #   $80, $82, $89, $C2, $E2 - immediate - 2 cycles
+          def nop_nocycle(_addr, _value); end
+
+          # Combination of ROL and AND operations.
+          #
+          # Opcodes:
+          #   $23 - indirect_x - 8 cycles
+          #   $27 - zeropage   - 5 cycles
+          #   $2F - absolute   - 6 cycles
+          #   $33 - indirect_y - 8 cycles
+          #   $37 - zeropage_x - 6 cycles
+          #   $3B - absolute_y - 7 cycles
+          #   $3F - absolute_x - 7 cycles
+          def rla(addr, value)
+            self.and(addr, rol(addr, value))
+          end
+
+          # Combination of ROR and ADC operations.
+          #
+          # Opcodes:
+          #   $63 - indirect_x - 8 cycles
+          #   $67 - zeropage   - 5 cycles
+          #   $6F - absolute   - 6 cycles
+          #   $73 - indirect_y - 8 cycles
+          #   $77 - zeropage_x - 6 cycles
+          #   $7B - absolute_y - 7 cycles
+          #   $7F - absolute_x - 7 cycles
+          def rra(addr, value)
+            adc(addr, ror(addr, value))
+          end
+
+          # Store A AND X.
+          #
+          # Opcodes:
+          #   $83 - indirect_x - 6 cycles
+          #   $87 - zeropage   - 3 cycles
+          #   $8F - absolute   - 4 cycles
+          #   $97 - zeropage_y - 4 cycles
+          def sax(addr, _value)
+            write_byte(addr, @a & @x)
+          end
+
+          # AND X register with accumulator and subtract value.
+          #
+          # Opcodes:
+          #   $CB - immediate - 2 cycles
+          def sbx(_addr, value)
+            result = (@x & @a) - value
+            status.carry = result >= 0
+            @x = result & 0xff
+            update_number_flags(@x)
+          end
+
+          # Stores A AND X AND (high byte of base address + 1) at addr.
+          #
+          # Opcodes:
+          #   $93 - indirect_y - 6 cycles
+          #   $9F - absolute_y - 5 cycles
+          def sha(addr, _value)
+            store_high_and(a & x, addr)
+          end
+
+          # Stores X AND (high byte of base address + 1) at addr.
+          #
+          # Opcodes:
+          #   $9E - absolute_y - 5 cycles
+          def shx(addr, _value)
+            store_high_and(x, addr)
+          end
+
+          # Stores Y AND (high byte of base address + 1) at addr.
+          #
+          # Opcodes:
+          #   $9C - absolute_x - 5 cycles
+          def shy(addr, _value)
+            store_high_and(y, addr)
+          end
+
+          # Combination of ASL and ORA operations.
+          #
+          # Opcodes:
+          #   $03 - indirect_x - 8 cycles
+          #   $07 - zeropage   - 5 cycles
+          #   $0F - absolute   - 6 cycles
+          #   $13 - indirect_y - 8 cycles
+          #   $17 - zeropage_x - 6 cycles
+          #   $1B - absolute_y - 7 cycles
+          #   $1F - absolute_x - 7 cycles
+          def slo(addr, value)
+            ora(addr, asl(addr, value))
+          end
+
+          # Combination of LSR and EOR operations.
+          #
+          # Opcodes:
+          #   $43 - indirect_x - 8 cycles
+          #   $47 - zeropage   - 5 cycles
+          #   $4F - absolute   - 6 cycles
+          #   $53 - indirect_y - 8 cycles
+          #   $57 - zeropage_x - 6 cycles
+          #   $5B - absolute_y - 7 cycles
+          #   $5F - absolute_x - 7 cycles
+          def sre(addr, value)
+            eor(addr, lsr(addr, value))
+          end
+
+          # Stores A AND X in SP, then stores SP AND (high byte of base + 1) at
+          # addr.
+          #
+          # Opcodes:
+          #   $9B - absolute_y - 5 cycles
+          def tas(addr, _value)
+            @stack_pointer = @a & @x
+            store_high_and(stack_pointer, addr)
+          end
+
+          private
+
+          # A VIC stall right before the dummy read, the second-to-last cycle,
+          # drops the & (H+1) from the stored value but not from the high byte
+          # of a page-crossing target.
+          def store_high_and(register, addr)
+            base_high = if boundary_crossed
+                          (high_byte(addr) - 1) & 0xff
+                        else
+                          high_byte(addr)
+                        end
+            result = register & ((base_high + 1) & 0xff)
+            target = boundary_crossed ? uint16(low_byte(addr), result) : addr
+            write_byte(target, stalled_before_previous_cycle? ? register : result)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/inc_dec.rb

@@ -0,0 +1,73 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module IncDec
+          # Decrements memory location by one.
+          #
+          # Opcodes:
+          #   $C6 - zeropage   - 5 cycles
+          #   $CE - absolute   - 6 cycles
+          #   $D6 - zeropage_x - 6 cycles
+          #   $DE - absolute_x - 7 cycles
+          def dec(addr, value)
+            result = (value - 1) & 0xff
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+
+          # Decrements X register by one.
+          #
+          # Opcodes:
+          #   $CA - implied - 2 cycles
+          def dex(_addr, _value)
+            @x = (@x - 1) & 0xff
+            update_number_flags(@x)
+          end
+
+          # Decrements Y register by one.
+          #
+          # Opcodes:
+          #   $88 - implied - 2 cycles
+          def dey(_addr, _value)
+            @y = (@y - 1) & 0xff
+            update_number_flags(@y)
+          end
+
+          # Increments memory location by one.
+          #
+          # Opcodes:
+          #   $E6 - zeropage   - 5 cycles
+          #   $EE - absolute   - 6 cycles
+          #   $F6 - zeropage_x - 6 cycles
+          #   $FE - absolute_x - 7 cycles
+          def inc(addr, value)
+            result = (value + 1) & 0xff
+            write_modified(addr, result)
+            update_number_flags(result)
+          end
+
+          # Increments X register by one.
+          #
+          # Opcodes:
+          #   $E8 - implied - 2 cycles
+          def inx(_addr, _value)
+            @x = (@x + 1) & 0xff
+            update_number_flags(@x)
+          end
+
+          # Increments Y register by one.
+          #
+          # Opcodes:
+          #   $C8 - implied - 2 cycles
+          def iny(_addr, _value)
+            @y = (@y + 1) & 0xff
+            update_number_flags(@y)
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/cpu/instruction_set/stack.rb

@@ -0,0 +1,56 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CPU
+      module InstructionSet
+        module Stack
+          # Push accumulator onto the stack.
+          #
+          # Opcodes:
+          #   $48 - implied - 3 cycles
+          def pha(_addr, _value)
+            stack_push(@a)
+          end
+
+          # Push processor status onto the stack.
+          #
+          # Opcodes:
+          #   $08 - implied - 3 cycles
+          def php(_addr, _value)
+            stack_push(p | 0b00010000)
+          end
+
+          # Pull accumulator from stack.
+          #
+          # Opcodes:
+          #   $68 - implied - 4 cycles
+          def pla(_addr, _value)
+            @a = stack_pull
+            update_number_flags(@a)
+          end
+
+          # Pull processor status from stack.
+          #
+          # Opcodes:
+          #   $28 - implied - 4 cycles
+          def plp(_addr, _value)
+            status.value = stack_pull & 0b11101111
+          end
+
+          private
+
+          def stack_pull
+            @stack_pointer = (@stack_pointer + 1) & 0xff
+            @memory.peek(stack_address)
+          end
+
+          def stack_push(value)
+            write_byte(stack_address, value)
+            @stack_pointer = (@stack_pointer - 1) & 0xff
+          end
+        end
+      end
+    end
+  end
+end