badline 0.12.1 → 0.14.0

data/lib/badline/chips/ted/beam.rb

@@ -0,0 +1,119 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class TED
+      # The raster and the clock the TED gives the CPU, a single clock
+      # cycle at a time.
+      #
+      # A line is 456 dots, horizontal counts 0-455, and a single clock
+      # cycle 8 of them, so a line is 57 cycles; #column counts them, the
+      # cycle at count 8 * column. The line count steps at count 376, in
+      # column 47, and runs 0-311 on PAL and 0-261 with $FF07 bit 6 set
+      # (NTSC). The datasheet's horizontal and vertical decode tables give
+      # those counts.
+      #
+      # The CPU runs once in a single clock cycle and twice in a double
+      # clock one. The datasheet's "System Clock Doubling": in the display
+      # window's lines the clock is single from count 400 round to 344,
+      # columns 50-56 and 0-42, and double in columns 43-49. The window is
+      # lines 0-203: the datasheet says 0-204, but xplus4 runs line 204 at
+      # double clock, as the lines below it. In the other lines it is double
+      # but for the five refresh cycles at counts 304-344, columns 38-42,
+      # which are single everywhere. With $FF06 bit 4 clear (blank) every
+      # line is double but for refresh, and $FF13 bit 1 or $FF07 bit 5
+      # (freeze) makes every cycle single.
+      #
+      # So a display line gives the CPU 64 cycles and a border line 109,
+      # the counts measured on real machines.
+      #
+      # DMA: each character row takes the bus for 40 cycles on two lines,
+      # the line before the row for the attributes and the row's first
+      # line for the character pointers (the datasheet's register 20). A
+      # row starts on the line after one whose low three bits match $FF06
+      # bits 0-2, as the KERNAL's scroll of 3 puts the first row on line 4,
+      # where the datasheet's 25-row window starts, and a row starts only
+      # in lines 0-203. xplus4 takes the bus on the same lines. The fetches run in columns 54-56 and 0-36, and BA
+      # goes low 3 cycles before the first, in column 51, so the CPU stops
+      # at its next read. A DMA line leaves the CPU 24 cycles.
+      module Beam
+        CYCLES_PER_LINE = 57
+        LINE_STEP_COLUMN = 47
+        BA_COLUMN = 51
+        DMA_COLUMN = 54
+        DMA_END_COLUMN = 36
+        REFRESH_COLUMNS = (38..42)
+        DOUBLE_COLUMNS = (43..49)
+        LAST_DISPLAY_LINE = 203
+
+        # The single clock cycle in the line, 0-56.
+        attr_reader :column
+
+        # The raster line.
+        attr_reader :line
+
+        # How many cycles the CPU runs in this cycle: 0 while the TED holds
+        # the bus for DMA, 1 at single clock and 2 at double clock.
+        attr_reader :cpu_slots
+
+        # Whether BA is low, from 3 cycles before DMA to its end.
+        def ba_low? = @ba_low
+
+        # Lines a frame, by $FF07 bit 6.
+        def lines_per_frame = @registers[0x07].anybits?(0x40) ? 262 : 312
+
+        private
+
+        def reset_beam
+          @column = 0
+          @line = 0
+          @dma_line = false
+          @ba_low = false
+          @cpu_slots = 1
+        end
+
+        def move_beam
+          column = @column + 1
+          column = 0 if column == CYCLES_PER_LINE
+          @column = column
+          return unless column == LINE_STEP_COLUMN
+
+          line = @line + 1
+          line = 0 if line >= lines_per_frame
+          self.line = line
+        end
+
+        def decide_clock
+          column = @column
+          @dma_line = dma_line? if column == BA_COLUMN
+          if @dma_line && (column >= BA_COLUMN || column <= DMA_END_COLUMN)
+            @ba_low = true
+            @cpu_slots = column >= DMA_COLUMN || column <= DMA_END_COLUMN ? 0 : 1
+            return
+          end
+
+          @ba_low = false
+          @cpu_slots = single_clock?(column) ? 1 : 2
+        end
+
+        def single_clock?(column)
+          return true if REFRESH_COLUMNS.include?(column) || @registers[0x13].anybits?(0x02) || frozen?
+
+          display_window? && !DOUBLE_COLUMNS.include?(column)
+        end
+
+        def display_window? = @registers[0x06].anybits?(0x10) && @line <= LAST_DISPLAY_LINE
+
+        def dma_line?
+          return false unless @registers[0x06].anybits?(0x10)
+
+          phase = (@line - (@registers[0x06] & 0x07)) & 0x07
+          return false if phase > 1
+
+          row = phase.zero? ? @line + 1 : @line
+          row <= LAST_DISPLAY_LINE
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/ted/timers.rb

@@ -0,0 +1,66 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class TED
+      # The three 16-bit timers at $FF00-$FF05, which count down once a
+      # single clock cycle whatever clock the CPU runs at. Each raises its
+      # interrupt flag as it counts down to zero. Timer 1's next count then
+      # loads the value last written to it, and timers 2 and 3 roll over to
+      # $FFFF.
+      #
+      # A write to a timer's low byte stops it until its high byte is
+      # written. Timer 1's writes set its reload value and its count
+      # together, and timers 2 and 3's set the count.
+      module Timers
+        # The interrupt flag each timer raises in $FF09.
+        TIMER_FLAGS = [0x08, 0x10, 0x40].freeze
+
+        # The counts, the reload value of timer 1, and which timers run.
+        attr_reader :timer_counts, :timer_running
+
+        private
+
+        def reset_timers
+          @timer_counts = [0, 0, 0]
+          @timer_running = [false, false, false]
+          @timer1_reload = 0
+        end
+
+        def count_timers
+          i = 0
+          while i < 3
+            count_timer(i) if @timer_running[i]
+            i += 1
+          end
+        end
+
+        def count_timer(index)
+          count = @timer_counts[index]
+          if count.zero? && index.zero?
+            @timer_counts[0] = @timer1_reload
+            return
+          end
+
+          count = (count - 1) & 0xffff
+          @timer_counts[index] = count
+          @interrupt_flags |= TIMER_FLAGS[index] if count.zero?
+        end
+
+        def read_timer(register)
+          count = @timer_counts[register >> 1]
+          register.even? ? count & 0xff : count >> 8
+        end
+
+        def write_timer(register, value)
+          index = register >> 1
+          count = @timer_counts[index]
+          count = register.even? ? (count & 0xff00) | value : (count & 0x00ff) | (value << 8)
+          @timer_counts[index] = count
+          @timer1_reload = count if index.zero?
+          @timer_running[index] = register.odd?
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/ted.rb

@@ -0,0 +1,143 @@
+# frozen_string_literal: true
+
+require "badline/chips/ted/timers"
+require "badline/chips/ted/beam"
+
+module Badline
+  module Chips
+    # The TED of the Commodore 264 series, the 7360 and 8360: its registers
+    # at $FF00-$FF1F, the raster, the three timers, the interrupt, the
+    # keyboard latch and the clock it gives the CPU (Beam). It paints no
+    # picture and plays no sound yet: those registers keep what is written
+    # to them.
+    #
+    # The machine clocks it once a single clock cycle, 57 to a line, and
+    # asks it then how many cycles the CPU runs in that one (#cpu_slots)
+    # and whether BA is low (#ba_low?).
+    #
+    # $FF08 is the keyboard latch: a write latches the K0-K7 inputs, which
+    # the keyboard port answers for the byte written (KeyboardPort#latch),
+    # and a read returns them. $FF09 holds the interrupt flags, each
+    # cleared by writing a 1 to it, with bit 7 set while the interrupt
+    # line is pulled. $FF0A holds the mask and bit 8 of the raster compare,
+    # and $FF0B the compare's low byte. $FF13 bit 0 reads whether the CPU
+    # sees ROM at $8000-$FFFF (#rom_selected=). $FF1C and $FF1D read and
+    # set the raster line, and $FF1E reads the horizontal position's top 8
+    # bits.
+    class TED
+      include Timers
+      include Beam
+
+      # The clock a TED is fed, its single clock: the crystal divided by 20
+      # on PAL machines and by 16 on NTSC ones (the Plus/4 hardware manual's
+      # TED datasheet).
+      Profile = Data.define(:name, :clock_hz)
+
+      PAL = Profile.new(name: :pal, clock_hz: 886_724)
+      NTSC = Profile.new(name: :ntsc, clock_hz: 894_886)
+
+      RASTER_FLAG = 0x02
+
+      # The interrupt sources a mask bit can enable: the raster, the light
+      # pen and the three timers.
+      SOURCES = 0x5e
+
+      attr_reader :profile, :interrupt_flags, :interrupt_mask
+
+      # What answers the keyboard latch: an object with #latch(value).
+      attr_writer :keyboard_port
+
+      # Whether the CPU sees ROM at $8000-$FFFF, which $FF13 bit 0 reads.
+      attr_writer :rom_selected
+
+      def initialize(profile = PAL)
+        @profile = profile
+        @keyboard_port = nil
+        @rom_selected = true
+        power_on!
+      end
+
+      def power_on!
+        @registers = Array.new(0x20, 0)
+        @interrupt_flags = 0
+        @interrupt_mask = 0
+        @raster_compare = 0
+        @key_latch = 0xff
+        reset_timers
+        reset_beam
+      end
+
+      # Counts the timers and moves the beam on a cycle, unless $FF07's
+      # freeze bit holds them, then decides the CPU's clock for the cycle.
+      def cycle!
+        unless frozen?
+          count_timers
+          move_beam
+        end
+        decide_clock
+      end
+
+      # Whether the interrupt line is pulled: a flag raised whose mask bit
+      # is set.
+      def irq? = @interrupt_flags.anybits?(@interrupt_mask & SOURCES)
+
+      def peek(addr)
+        register = addr & 0x3f
+        return 0xff if register >= 0x20
+
+        case register
+        when 0x00..0x05 then read_timer(register)
+        when 0x08 then @key_latch
+        when 0x09 then read_interrupt_flags
+        when 0x0a then @interrupt_mask | 0xa0
+        when 0x0b then @raster_compare & 0xff
+        when 0x13 then (@registers[0x13] & 0xfe) | (@rom_selected ? 1 : 0)
+        when 0x1c then 0xfe | (@line >> 8)
+        when 0x1d then @line & 0xff
+        when 0x1e then @column << 2
+        else @registers[register]
+        end
+      end
+
+      def poke(addr, value)
+        register = addr & 0x3f
+        return if register >= 0x20
+
+        @registers[register] = value
+        case register
+        when 0x00..0x05 then write_timer(register, value)
+        when 0x08 then @key_latch = @keyboard_port ? @keyboard_port.latch(value) : 0xff
+        when 0x09 then @interrupt_flags &= ~value
+        when 0x0a then write_interrupt_mask(value)
+        when 0x0b then @raster_compare = (@raster_compare & 0x100) | value
+        when 0x1c then self.line = (@line & 0xff) | ((value & 0x01) << 8)
+        when 0x1d then self.line = (@line & 0x100) | value
+        end
+      end
+
+      private
+
+      # $FF07 bit 5 stops the beam and the timers.
+      def frozen? = @registers[0x07].anybits?(0x20)
+
+      def read_interrupt_flags
+        value = @interrupt_flags | 0x21
+        irq? ? value | 0x80 : value
+      end
+
+      def write_interrupt_mask(value)
+        @interrupt_mask = value & 0x5f
+        @raster_compare = (@raster_compare & 0xff) | ((value & 0x01) << 8)
+      end
+
+      def line=(value)
+        @line = value
+        raster_reached
+      end
+
+      def raster_reached
+        @interrupt_flags |= RASTER_FLAG if @line == @raster_compare
+      end
+    end
+  end
+end

data/lib/badline/chips/tia.rb

@@ -0,0 +1,49 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    # The 6523 TIA, a tri-port interface adapter: three 8-bit ports, A, B
+    # and C at registers 0-2, each with its direction register at 3-5, a 1
+    # making the pin an output. Its three address lines repeat the
+    # registers every 8 bytes, and registers 6 and 7 read $FF.
+    #
+    # A pin read as an output returns what the port drives, and one read as
+    # an input returns what the other side drives, #inputs, per port.
+    class TIA
+      attr_reader :ports, :directions
+
+      # What the other side drives onto each port's pins.
+      attr_reader :inputs
+
+      def initialize
+        @inputs = [0, 0, 0]
+        reset!
+      end
+
+      def reset!
+        @ports = [0, 0, 0]
+        @directions = [0, 0, 0]
+      end
+
+      def peek(addr)
+        register = addr & 0x07
+        return 0xff if register > 5
+        return @directions[register - 3] if register >= 3
+
+        direction = @directions[register]
+        (@ports[register] & direction) | (@inputs[register] & ~direction & 0xff)
+      end
+
+      def poke(addr, value)
+        register = addr & 0x07
+        return if register > 5
+
+        if register >= 3
+          @directions[register - 3] = value
+        else
+          @ports[register] = value
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/vdc/keyed_parts.rb

@@ -0,0 +1,105 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class VDC
+      class Raster
+        # The raster's fields in a keyed snapshot module, under `prefix`:
+        # the frame count, where the beam is in the character rows and the
+        # frame, and the frame's size and sync as it latched them.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}frame", @frame).int("#{prefix}row", @row).int("#{prefix}row_line", @row_line)
+            out.bool("#{prefix}adjusting", @adjusting).int("#{prefix}frame_line", @frame_line)
+            out.int("#{prefix}frame_lines", @frame_lines).int("#{prefix}sync_start", @sync_start)
+            out.int("#{prefix}sync_lines", @sync_lines)
+          end
+
+          def load_fields(input, prefix)
+            @frame = input.int("#{prefix}frame", @frame)
+            @row = input.int("#{prefix}row", @row)
+            @row_line = input.int("#{prefix}row_line", @row_line)
+            @adjusting = input.bool("#{prefix}adjusting", @adjusting)
+            @frame_line = input.int("#{prefix}frame_line", @frame_line)
+            @frame_lines = input.int("#{prefix}frame_lines", @frame_lines)
+            @sync_start = input.int("#{prefix}sync_start", @sync_start)
+            @sync_lines = input.int("#{prefix}sync_lines", @sync_lines)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Window
+        # The start addresses the frame latched, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.int("#{prefix}display_start", @display_start).int("#{prefix}attribute_start", @attribute_start)
+          end
+
+          def load_fields(input, prefix)
+            @display_start = input.word("#{prefix}display_start", @display_start)
+            @attribute_start = input.word("#{prefix}attribute_start", @attribute_start)
+          end
+        end
+
+        include KeyedState
+      end
+
+      class Painter
+        # The display's size, as the frame latched it, and the window's
+        # start addresses. The picture is painted again.
+        module KeyedState
+          def save_fields(out)
+            out.int("display.width", @width).int("display.height", @height)
+            @window.save_fields(out, "window.")
+          end
+
+          def load_fields(input)
+            resize(input.int("display.width", @width), input.int("display.height", @height))
+            @window.load_fields(input, "window.")
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The VDC's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers, the RAM, the register selected, the data latches, the
+      # dot clock's phase and the line's length in the same units
+      # (dots·Hz, the line latched at its start), how long an access or
+      # block operation stays busy from now, the raster under raster.* and
+      # the display's size and window under display.* and window.*. The
+      # RAM's layout comes from R28 on load.
+      module KeyedState
+        def save_fields(out)
+          out.bytes("registers", @registers).bytes("ram", @memory.ram).int("selected", @selected)
+          out.int("read_latch", @read_latch).int("write_data", @write_data).int("phase", @phase)
+          out.int("line_units", @line_units).int("busy_for", @busy_until - @phase)
+          @raster.save_fields(out, "raster.")
+          @painter.save_fields(out)
+          out
+        end
+
+        def load_fields(input)
+          input.bytes_into("registers", @registers)
+          input.bytes_into("ram", @memory.ram)
+          @selected = input.masked("selected", @selected, 0x3f)
+          @read_latch = input.byte("read_latch", @read_latch)
+          @write_data = input.byte("write_data", @write_data)
+          @phase = input.int("phase", @phase)
+          @line_units = input.int("line_units", @line_units)
+          @busy_until = @phase + input.int("busy_for", @busy_until - @phase)
+          @raster.load_fields(input, "raster.")
+          @painter.load_fields(input)
+        end
+
+        def restored!
+          @memory.mode64 = @registers[28].anybits?(0x10)
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/{c128 → chips}/vdc/memory.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # The VDC's own DRAM: 16K of two 4416s (16K by 4) or 64K of 4164s or
       # 4464s, behind the 16-bit addresses the VDC computes.

data/lib/badline/{c128 → chips}/vdc/painter.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # Paints the VDC's scan lines into its display, one line at a time,
       # from the registers as they stand when the line ends. Each pixel of
@@ -56,18 +56,6 @@ module Badline
           [0, 0, shown.clamp(1, @width), (frame_lines - sync_lines).clamp(1, @height)]
         end
 
-        # The display's size and the window's start addresses. The display
-        # starts again cleared, to be painted while the VDC renders.
-        def save_state(out)
-          out.int(@width).int(@height)
-          @window.save_state(out)
-        end
-
-        def load_state(input)
-          resize(input.int, input.int)
-          @window.load_state(input)
-        end
-
         def clear_dirty_lines!
           @dirty_lines.fill(false)
         end

data/lib/badline/{c128 → chips}/vdc/raster.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # The VDC's raster: R0 + 1 characters a line, R9 + 1 lines a row,
       # R4 + 1 rows a frame and then R5 more lines, with the frame's size
@@ -30,22 +30,6 @@ module Badline
         # Outside the displayed rows, as status bit 5 reads.
         def vertical_blank? = @adjusting || @row >= @registers[6]
 
-        def save_state(out)
-          out.int(@frame).int(@row).int(@row_line).boolean(@adjusting).int(@frame_line).int(@frame_lines)
-          out.int(@sync_start).int(@sync_lines)
-        end
-
-        def load_state(input)
-          @frame = input.int
-          @row = input.int
-          @row_line = input.int
-          @adjusting = input.boolean?
-          @frame_line = input.int
-          @frame_lines = input.int
-          @sync_start = input.int
-          @sync_lines = input.int
-        end
-
         def end_line(render)
           paint_line if render
           @frame_line += 1

data/lib/badline/{c128 → chips}/vdc/window.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class C128
+  module Chips
     class VDC
       # Paints the characters of a displayed line, R1 of them from the
       # line's first dot, in text mode or, with R25 bit 7, bitmap mode.
@@ -57,15 +57,6 @@ module Badline
           @attribute_start = (regs[20] << 8) | regs[21]
         end
 
-        def save_state(out)
-          out.int(@display_start).int(@attribute_start)
-        end
-
-        def load_state(input)
-          @display_start = input.int
-          @attribute_start = input.int
-        end
-
         def paint(line, row, row_line, frame)
           regs = @registers
           lay_out_cell

data/lib/badline/{c128 → chips}/vdc.rb

@@ -1,12 +1,13 @@
 # frozen_string_literal: true
 
-require "badline/c128/vdc/memory"
-require "badline/c128/vdc/window"
-require "badline/c128/vdc/painter"
-require "badline/c128/vdc/raster"
+require "badline/chips/vdc/memory"
+require "badline/chips/vdc/window"
+require "badline/chips/vdc/painter"
+require "badline/chips/vdc/raster"
+require "badline/chips/vdc/keyed_parts"
 
 module Badline
-  class C128
+  module Chips
     # The 8563 or 8568 VDC: the address register at $D600 and the data
     # register at $D601, mirrored through $D6FF, in front of 37 internal
     # registers (38 on the 8568), the VDC's own RAM (Memory) and its 80
@@ -112,32 +113,6 @@ module Badline
         @painter.clear!
       end
 
-      # Everything the VDC holds but its display, which it paints again
-      # while it renders: the registers, the RAM, the data port and the
-      # raster. Whether it renders is the host's.
-      def save_state(out)
-        out.marker("VDC")
-        out.ints(@registers).blob(@memory.ram)
-        out.int(@selected).int(@read_latch).int(@write_data).int(@busy_until).int(@phase).int(@line_units)
-        @raster.save_state(out)
-        @painter.save_state(out)
-      end
-
-      def load_state(input)
-        input.marker("VDC")
-        input.ints_into(@registers)
-        input.blob_into(@memory.ram)
-        @memory.mode64 = @registers[28].anybits?(0x10)
-        @selected = input.int
-        @read_latch = input.int
-        @write_data = input.int
-        @busy_until = input.int
-        @phase = input.int
-        @line_units = input.int
-        @raster.load_state(input)
-        @painter.load_state(input)
-      end
-
       # The frames the raster has finished, which the blinking counts.
       def frame = @raster.frame