badline 0.12.1 → 0.14.0

data/lib/badline/c64/reu.rb

@@ -0,0 +1,289 @@
+# frozen_string_literal: true
+
+require "badline/c64/reu/ram"
+require "badline/c64/reu/dma"
+require "badline/c64/reu/trigger"
+require "badline/c64/reu/keyed_state"
+
+module Badline
+  class C64
+    # A RAM Expansion Unit: the Commodore 1700 (128K), 1764 (256K) and 1750
+    # (512K), and the bigger units built around the same 8726 RAM Expansion
+    # Controller (REC), such as the CMD 1750XL, up to 16M.
+    #
+    # The REC's eleven registers sit in I/O 2 from $DF00, repeated every 32
+    # bytes up to $DFFF, as the 1764 and 1750 manuals map them. It moves
+    # bytes between the C64 and its RAM by DMA, one bus cycle each, with the
+    # CPU held off the bus. A command with the execute bit set starts a
+    # transfer, or with bit 4 clear arms the REC to start one on the next
+    # write to $FF00, so a program can bank the ROMs out first. A transfer
+    # waits for the CPU's next read cycle with BA high, and C64 then
+    # clocks it through #dma_cycle! until it hands the bus back.
+    class REU
+      SIZES_KB = [128, 256, 512, 1024, 2048, 4096, 8192, 16_384].freeze
+
+      # The registers, by offset.
+      STATUS = 0x00
+      COMMAND = 0x01
+      C64_LOW = 0x02
+      C64_HIGH = 0x03
+      EXPANSION_LOW = 0x04
+      EXPANSION_HIGH = 0x05
+      EXPANSION_BANK = 0x06
+      LENGTH_LOW = 0x07
+      LENGTH_HIGH = 0x08
+      INTERRUPT_MASK = 0x09
+      ADDRESS_CONTROL = 0x0a
+
+      # Status: an interrupt is pending, the block ended, a verify found a
+      # difference (the manual's fault bit), and the unit is built from 256K
+      # chips, which only the 1700 isn't. Reading the status clears the top
+      # three.
+      INTERRUPT_PENDING = 0x80
+      END_OF_BLOCK = 0x40
+      FAULT = 0x20
+      CHIPS_256K = 0x10
+
+      # Command: execute, reload the registers after the transfer, don't wait
+      # for $FF00, and the transfer type in the bottom two bits.
+      EXECUTE = 0x80
+      AUTOLOAD = 0x20
+      NO_FF00_TRIGGER = 0x10
+      TRANSFER_TYPE = 0x03
+
+      # Interrupt mask: interrupts on at all, then on the end of a block and
+      # on a fault. The low five bits aren't there and read as 1.
+      INTERRUPTS_ON = 0x80
+      INTERRUPT_ON_END = 0x40
+      INTERRUPT_ON_FAULT = 0x20
+
+      # Address control: hold the C64 address or the expansion address where
+      # it is. The low six bits aren't there and read as 1.
+      FIX_C64 = 0x80
+      FIX_EXPANSION = 0x40
+
+      # The REC's bank register has three bits, and the other five read as
+      # 1. A unit past 512K latches all eight onto its own address lines.
+      BANK_STUCK = 0xf8
+
+      attr_reader :trigger
+
+      # bus is the bus the REC reaches C64 memory through, and vic the VIC,
+      # whose phi1 fetch is what a register read finds on the bus during a
+      # transfer.
+      def initialize(size_kb, bus:, vic:)
+        raise ArgumentError, "No #{size_kb}K REU. Pick one of #{SIZES_KB.join(', ')}." unless SIZES_KB.include?(size_kb)
+
+        # The 1700's REC counts 17 address bits, the others' 19.
+        span = size_kb == 128 ? 0x20000 : 0x80000
+        @size_kb = size_kb
+        size = size_kb * 1024
+        @address_mask = [size, span].max - 1
+        @bank_bits = size > span ? 0xff : 0x07
+        @chips = size_kb == 128 ? 0 : CHIPS_256K
+        @ram = RAM.new(size, span)
+        @dma = DMA.new(@ram, span, bus)
+        @trigger = Trigger.new(self)
+        @vic = vic
+        @on_irq_change = nil
+        @on_dma = nil
+        @irq = false
+        reset!
+      end
+
+      def on_irq_change(&block)
+        @on_irq_change = block
+      end
+
+      # Called when the REC asks for the bus.
+      def on_dma(&block)
+        @on_dma = block
+      end
+
+      def irq? = @irq
+
+      # From the moment the REC asks for the bus until it hands it back.
+      def dma? = @requested || @running
+
+      # Whether the REC ran a transfer on the last cycle clocked, which it
+      # goes on doing until the cycle it lets go of the bus.
+      def holds_bus? = @running
+
+      def reset!
+        @status = @chips
+        @command = NO_FF00_TRIGGER
+        @c64 = @c64_start = 0
+        @expansion = @expansion_start = 0
+        @bank = @bank_start = 0
+        @length = @length_start = 0xffff
+        @interrupt_mask = 0x1f
+        @address_control = 0x3f
+        @armed = @requested = @running = @ba_was_low = false
+        interrupt(false)
+      end
+
+      def peek(addr)
+        return @vic.phi1_data if @running
+
+        register = addr & 0x1f
+        value = register_value(register)
+        read_status if register == STATUS
+        value
+      end
+
+      def poke(addr, value)
+        return if @running
+
+        register = addr & 0x1f
+        case register
+        when COMMAND then write_command(value)
+        when C64_LOW, C64_HIGH then @c64 = @c64_start = with_byte(@c64_start, value, register == C64_HIGH)
+        when EXPANSION_LOW, EXPANSION_HIGH
+          @expansion = @expansion_start = with_byte(@expansion_start, value, register == EXPANSION_HIGH)
+        when EXPANSION_BANK then @bank = @bank_start = value & @bank_bits
+        when LENGTH_LOW, LENGTH_HIGH
+          @length = @length_start = with_byte(@length_start, value, register == LENGTH_HIGH)
+        when INTERRUPT_MASK then write_interrupt_mask(value)
+        when ADDRESS_CONTROL then @address_control = value | 0x3f
+        end
+      end
+
+      # A write to $FF00 starts the transfer the command register armed.
+      def ff00_written
+        return unless @armed
+
+        @armed = false
+        request_bus
+      end
+
+      # Clocks the REC for a cycle, given the VIC's BA line. A requested
+      # transfer starts on the first cycle with BA high as the REC sees it,
+      # even one the CPU writes on. Pinned by REU/rmw-trigger. A fetch
+      # requested on the cycle before BA falls writes its first byte on the
+      # first BA-low cycle as well, and again when it starts. Pinned by
+      # REU/badoublewrite.
+      def dma_cycle!(ba_low)
+        late = ba_low && @vic.reu_ba_late?
+        if @requested
+          return hold_off if ba_low && !late
+
+          start_transfer
+        end
+        @dma.cycle!(ba_low, late, ba_low && @vic.reu_ba_handed_on?)
+        end_transfer unless @dma.holds_bus?
+      end
+
+      # The REU's RAM, at an address as the REC's registers give it.
+      def ram_peek(addr) = @ram.peek(addr)
+
+      def ram_poke(addr, value) = @ram.poke(addr, value)
+
+      private
+
+      def register_value(register)
+        case register
+        when STATUS then @status
+        when COMMAND then @command
+        when C64_LOW then @c64 & 0xff
+        when C64_HIGH then @c64 >> 8
+        when EXPANSION_LOW then @expansion & 0xff
+        when EXPANSION_HIGH then @expansion >> 8
+        when EXPANSION_BANK then @bank | BANK_STUCK
+        when LENGTH_LOW then @length & 0xff
+        when LENGTH_HIGH then @length >> 8
+        when INTERRUPT_MASK then @interrupt_mask
+        when ADDRESS_CONTROL then @address_control
+        else 0xff
+        end
+      end
+
+      def read_status
+        @status &= CHIPS_256K
+        interrupt(false)
+      end
+
+      # Writing either byte of an address or the length sets the value the
+      # transfer starts from, and puts the counter back to it.
+      def with_byte(word, value, high)
+        high ? (word & 0x00ff) | (value << 8) : (word & 0xff00) | value
+      end
+
+      def write_command(value)
+        @command = value
+        return if value.nobits?(EXECUTE)
+
+        @armed = value.nobits?(NO_FF00_TRIGGER)
+        request_bus unless @armed
+      end
+
+      # An interrupt enabled over a block that already ended, or a fault
+      # already found, fires at once.
+      def write_interrupt_mask(value)
+        @interrupt_mask = value | 0x1f
+        interrupt_on(@status)
+      end
+
+      def interrupt_on(events)
+        return unless @interrupt_mask.anybits?(INTERRUPTS_ON)
+        return unless (events.anybits?(END_OF_BLOCK) && @interrupt_mask.anybits?(INTERRUPT_ON_END)) ||
+                      (events.anybits?(FAULT) && @interrupt_mask.anybits?(INTERRUPT_ON_FAULT))
+
+        @status |= INTERRUPT_PENDING
+        interrupt(true)
+      end
+
+      def interrupt(level)
+        return if @irq == level
+
+        @irq = level
+        @on_irq_change&.call(level)
+      end
+
+      def request_bus
+        @requested = true
+        @ba_was_low = @vic.ba_low?
+        @on_dma&.call
+      end
+
+      def hold_off
+        @dma.write_ahead(@command & TRANSFER_TYPE, @c64, @expansion | (@bank << 16)) unless @ba_was_low
+        @ba_was_low = true
+      end
+
+      def start_transfer
+        @requested = false
+        @running = true
+        @dma.start(@command & TRANSFER_TYPE, @c64, @expansion | (@bank << 16), @length, @address_control)
+      end
+
+      # The execute bit drops and the $FF00 trigger turns off. With autoload
+      # the addresses and the length go back to where the transfer started,
+      # and otherwise they stay where it stopped.
+      def end_transfer
+        @running = false
+        @command = (@command & ~EXECUTE & 0xff) | NO_FF00_TRIGGER
+        events = @dma.events
+        @status |= events
+        @command.anybits?(AUTOLOAD) ? reload : keep_counters
+        interrupt_on(events)
+      end
+
+      def reload
+        @c64 = @c64_start
+        @expansion = @expansion_start
+        @bank = @bank_start
+        @length = @length_start
+      end
+
+      def keep_counters
+        @c64 = @dma.c64 if @address_control.nobits?(FIX_C64)
+        @length = @dma.length & 0xffff
+        return if @address_control.anybits?(FIX_EXPANSION)
+
+        address = @dma.expansion & @address_mask
+        @expansion = address & 0xffff
+        @bank = (address >> 16) & 0xff
+      end
+    end
+  end
+end

data/lib/badline/c64/true_drives.rb

@@ -0,0 +1,120 @@
+# frozen_string_literal: true
+
+module Badline
+  class C64
+    # The true drives on the machine's serial bus: a Drives::Model1541, and a
+    # Drives::Model1581 (Drives::Model1581::Slot), each in a field of its own. C64,
+    # Vic20 and C128 each include it.
+    module TrueDrives
+      include Drives::Model1581::Slot
+
+      # The true drive models a snapshot names.
+      DRIVE_MODELS = %w[1541 1571 1581].freeze
+
+      # Plugs in a Drives::Model1541, which then runs alongside the machine on its
+      # own clock and talks to it over the serial bus. The serial traps stop
+      # answering the drive's device number, so the KERNAL's TALK, LISTEN and
+      # byte transfers reach the drive. The LOAD and SAVE traps stay, and
+      # still serve a mounted image.
+      def attach_drive1541(drive)
+        @iec_bus.detach(@drive1541) if @drive1541
+        drive.host_clock_hz = timing.clock_hz
+        @drive1541 = drive
+        drive.connect(@iec_bus)
+        @serial_trap&.device = serial_trap_device
+        drive1541_attached
+      end
+
+      # The true drive on the serial bus: the Drives::Model1581 ahead of the
+      # Drives::Model1541, or nil.
+      def true_drive = @drive1581 || @drive1541
+
+      # Plugs a Drives::Model1541 in as device 8, in place of a 1581 there, and
+      # returns it.
+      def plug_true_drive
+        detach_drive1581 if drive1581_on_device8?
+        Drives::Model1541.new.tap { |drive| attach_drive1541(drive) }
+      end
+
+      # The true drives as keyed snapshot modules, each named from its device
+      # number: BL-D8, BL-D8-CPU and so on for device 8.
+      def save_drive_modules(sections)
+        drive1541 = @drive1541
+        drive1541&.save_modules(sections, "BL-D#{drive1541.device}")
+        drive1581 = @drive1581
+        drive1581&.save_modules(sections, "BL-D#{drive1581.device}")
+        save_drive1571_modules(sections)
+        sections
+      end
+
+      # The true drives a snapshot's modules hold, built afresh unless the
+      # same model is on the bus as the same device. A drive the snapshot
+      # doesn't have comes off the bus.
+      def load_drive_modules(modules)
+        models = []
+        8.upto(11) do |device|
+          input = modules.optional("BL-D#{device}")
+          next unless input
+
+          model = input.choice("model", DRIVE_MODELS, "1541")
+          load_drive_model(modules, input, device, model)
+          models << model
+        end
+        detach_drive1541 unless models.include?("1541")
+        detach_drive1581 unless models.include?("1581")
+        detach_drive1571 unless models.include?("1571")
+      end
+
+      # Unplugs the Drives::Model1541, leaving the serial bus with nothing on it.
+      def detach_drive1541
+        return unless @drive1541
+
+        @iec_bus.detach(@drive1541)
+        @drive1541 = nil
+        @serial_trap&.device = serial_trap_device
+      end
+
+      private
+
+      # The device number the serial traps answer: device 8, unless a true
+      # drive is on the bus as device 8.
+      def serial_trap_device
+        device = KernalTrap::Routine::DEVICE
+        @drive1541&.device == device || drive1581_on_device8? ? nil : device
+      end
+
+      # What the machine does as a 1541 goes on its bus. The VIC-20 waits
+      # for its DOS to boot before typing.
+      def drive1541_attached = nil
+
+      def load_drive_model(modules, input, device, model)
+        case model
+        when "1581" then load_drive1581_modules(modules, input, device)
+        when "1571" then load_drive1571_modules(modules, input, device)
+        else load_drive1541_modules(modules, input, device)
+        end
+      end
+
+      def load_drive1541_modules(modules, input, device)
+        detach_drive1541 if @drive1541 && @drive1541.device != device
+        attach_drive1541(Drives::Model1541.new(device:)) unless @drive1541
+        @drive1541.load_modules(modules, input, "BL-D#{device}")
+      end
+
+      def load_drive1581_modules(modules, input, device)
+        detach_drive1581 if @drive1581 && @drive1581.device != device
+        attach_drive1581(Drives::Model1581.new(device:)) unless @drive1581
+        @drive1581.load_modules(modules, input, "BL-D#{device}")
+      end
+
+      # The C128D's 1571, which only the C128 has (C128::Drives).
+      def save_drive1571_modules(sections) = sections
+
+      def load_drive1571_modules(_modules, input, _device)
+        input.adjust("a 1571 doesn't plug into this machine, left out")
+      end
+
+      def detach_drive1571 = nil
+    end
+  end
+end

data/lib/badline/{computer.rb → c64.rb}

@@ -1,20 +1,21 @@
 # frozen_string_literal: true
 
-require "badline/computer/common"
-require "badline/computer/true_drives"
-require "badline/computer/attachments"
-require "badline/computer/kernal_traps"
-require "badline/computer/saved_state"
+require "badline/c64/common"
+require "badline/c64/true_drives"
+require "badline/c64/attachments"
+require "badline/c64/kernal_traps"
+require "badline/c64/keyed_state"
+require "badline/c64/keyed_modules"
 
 module Badline
-  class Computer
+  class C64
     include IntegerHelper
-    include KeyboardBuffer
+    include Machine::KeyboardBuffer
     include Machine::Clocking
+    include Machine::Settling
     include Common
     include Attachments
     include KernalTraps
-    include SavedState
 
     attr_reader :address_bus, :cpu, :cycles, :drive1541
 
@@ -32,6 +33,11 @@ module Badline
 
     def ram = address_bus.ram
 
+    # Reads and writes memory as the CPU sees it, through the bus.
+    def peek(addr) = address_bus.peek(addr)
+
+    def poke(addr, value) = address_bus.poke(addr, value)
+
     def keyboard = address_bus.keyboard
 
     def joystick1 = address_bus.joystick1
@@ -45,18 +51,18 @@ module Badline
     def install_debug_register(&) = address_bus.install_debug_register(&)
 
     # The machine options (sid_model:, cia_model:, vic_model:, region: and
-    # ram_expansion:) configure the AddressBus. The region sets the clock,
+    # ram_expansion:) configure the C64::Bus. The region sets the clock,
     # the VIC's raster and sprite timing, and the mains frequency the CIAs'
     # TOD clocks count. The KERNAL tells PAL from NTSC by the raster, so
     # every region boots the same ROMs. reu plugs an REU of that many K
     # into the expansion port, where it drives the IRQ line and takes the
     # bus for its transfers. kernal:, datasette: and board: fit the bus
-    # afterwards (AddressBus::Fittings): the KERNAL ROM, the cassette port,
+    # afterwards (C64::Bus::Fittings): the KERNAL ROM, the cassette port,
     # which is empty on the SX-64, and the board and case.
     def initialize(debug: false, reu: nil, **machine)
-      @address_bus = AddressBus.new(**machine.except(*AddressBus::Fittings::NAMES))
-      @address_bus.fit(**machine.slice(*AddressBus::Fittings::NAMES))
-      @cpu = CPU.new(@address_bus, debug:)
+      @address_bus = Bus.new(**machine.except(*Bus::Fittings::NAMES))
+      @address_bus.fit(**machine.slice(*Bus::Fittings::NAMES))
+      @cpu = Chips::CPU.new(@address_bus, debug:)
       @vic = @address_bus.vic
       @vic.open_bus = -> { @address_bus.ram.peek(@cpu.program_counter) }
       @cia1 = @address_bus.cia1
@@ -73,7 +79,7 @@ module Badline
       @freeze_writes = 0
       @init_handlers = []
       @pending_keys = nil
-      @drive = nil
+      @dos = nil
       @serial_trap = nil
       @save_trap = nil
       @drive1541 = nil
@@ -145,7 +151,7 @@ module Badline
       address_bus.cartridge&.reset
       @reu&.reset!
       @dma = false
-      @drive&.reset!
+      @dos&.reset!
       @drive1541&.reset!
       @drive1581&.reset!
       @freezing = false
@@ -183,6 +189,9 @@ module Badline
     # The KERNAL the traps stand in for (KernalTraps#mount).
     def trap_layout = KernalTrap::C64_LAYOUT
 
+    # The KERNAL's keyboard buffer, which #type_text feeds.
+    def keyboard_buffer = Machine::KeyboardBuffer::C64_LAYOUT
+
     def trap_bus = address_bus
 
     def plug_reu(size_kb)

data/lib/badline/chips/cia/fast_forward.rb

@@ -0,0 +1,62 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CIA
+      # Running a CIA a stretch of cycles at once, for Drives::Engine::Idle.
+      module FastForward
+        # quiet_cycles for a CIA whose counters will never set a flag.
+        QUIET = 1 << 40
+
+        # Whether fast_forward can run the CIA: timer B stopped with nothing
+        # in its pipeline, no interrupt or acknowledge on its way, CNT where it
+        # was, the TOD clock stopped, and timer A either stopped, or free
+        # running (Timer#free_running?) with its interrupt masked and the
+        # serial port an idle input. Drives::Engine::Idle sleeps the 1571's CIA through
+        # such cycles, which its DOS leaves timer A running in.
+        def quiet?
+          return false unless @tb.idle? && @icr.quiet && @tod.quiet? && cnt_steady?
+
+          @ta.idle? ? @serial.idle : timer_a_free_running?
+        end
+
+        # How many cycles the CIA can run with nothing but its counters
+        # moving: as quiet? allows, but with timer B free running too, up to
+        # the cycle before it underflows. The 1581's DOS leaves timer B
+        # interrupting every 10 ms.
+        def quiet_cycles
+          return 0 unless @icr.quiet && @tod.quiet? && cnt_steady? && timer_a_quiet?
+          return QUIET if @tb.idle?
+          return 0 unless @tb.free_running? && @control_b.value.nobits?(0x60)
+
+          @tb.counter - 1
+        end
+
+        # Runs +cycles+ cycles at once while quiet? or for quiet_cycles, as
+        # cycle! would: timer A's underflows flag in the ICR, and reach the
+        # serial port's underflow line.
+        def fast_forward(cycles)
+          @tod.fast_forward(cycles)
+          @tb.fast_forward(cycles) unless @tb.idle?
+          return if @ta.idle?
+
+          @icr.flag(:timer_a) if @ta.fast_forward(cycles).positive?
+          @serial.follow_underflow(@ta.underflowed)
+        end
+
+        private
+
+        def timer_a_quiet? = @ta.idle? ? @serial.idle : timer_a_free_running?
+
+        # Timer A free running with its interrupt masked, and the serial port
+        # an idle input it only clocks.
+        def timer_a_free_running?
+          @ta.free_running? && !@control_a.serial_mode? && @icr.mask.value.nobits?(0x01) && @serial.drained?
+        end
+
+        # Whether CNT holds the level the last cycle sampled.
+        def cnt_steady? = @serial.cnt == @cnt_high && !@cnt_rise
+      end
+    end
+  end
+end

data/lib/badline/chips/cia/interrupt_register.rb

@@ -0,0 +1,128 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class CIA
+      # The interrupt control register: the source flags, their mask and the
+      # IR bit that drives the interrupt line, with the 6526's acknowledge
+      # timing.
+      class InterruptRegister
+        attr_reader :status, :mask, :quiet
+
+        # The 6526A is the faster of the two: see the rules below.
+        def initialize(model = :mos6526)
+          @fast = model == :mos6526a
+          @mask = InterruptFlags.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, 0])
+          @status = InterruptFlags.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, :interrupt])
+          @pending = 0
+          @read = @read_last_cycle = @read_two_cycles_ago = nil
+          @timer_b_bug = false
+          @quiet = true
+        end
+
+        # The CIA skips this while quiet: no read is recent enough to matter
+        # and no assert is due.
+        def cycle!
+          @read_two_cycles_ago = @read_last_cycle
+          @read_last_cycle = @read
+          @read = nil
+          if @pending.positive?
+            @pending -= 1
+            status.interrupt = true if @pending.zero?
+          end
+          @quiet = @pending.zero? && @read_last_cycle.nil? && @read_two_cycles_ago.nil?
+        end
+
+        def interrupted? = status.value >= 0x80
+
+        # Raises IR on this cycle.
+        def assert_now
+          status.interrupt = true
+          @pending = 0
+        end
+
+        # Schedules IR to rise after delay cycles, keeping an earlier one.
+        def assert!(delay = 1)
+          @pending = @pending.positive? ? [@pending, delay].min : delay
+          @quiet = false
+        end
+
+        # Latch a source, pulling the interrupt line if it is armed. The 6526
+        # raises IR a cycle after the flag. The 6526A raises it on the flag's
+        # own cycle, unless the ICR was read on the cycle before.
+        def flag(source)
+          bit = source_bit(source)
+          @status.value |= bit
+          return unless mask.value.anybits?(bit)
+
+          @fast && @read_last_cycle.nil? ? assert_now : assert!
+        end
+
+        # The 6526 timer B bug: an underflow on the cycle after a read still
+        # raises the flag, but the next read drops it unseen. The 6526A has
+        # no such bug.
+        def timer_b_underflow!
+          @timer_b_bug = !@fast && !@read_last_cycle.nil?
+          flag(:timer_b)
+        end
+
+        # A read releases the interrupt line at once, and cancels an assert
+        # due on the next cycle, but its acknowledge lands a cycle late. On
+        # the 6526 that holds only IR: the next cycle still reads IR set if it
+        # was set, or about to be. The 6526A reads an IR about to rise as set
+        # at once, and holds every bit it read: the next cycle reads them all
+        # again, along with anything flagged since.
+        def read
+          status.timer_b = false if @timer_b_bug
+          @timer_b_bug = false
+          value = status.value
+          value |= 0x80 if @fast && @pending == 1
+          @read = @pending == 1 ? value | 0x80 : value
+          @quiet = false
+          value |= held(@read_last_cycle) if @read_last_cycle
+          status.value = 0x0
+          @pending = 0
+          value
+        end
+
+        # Bit 7 picks between setting and clearing the mask bits given.
+        def write(value)
+          if value.nobits?(0x80)
+            @mask.value &= ~(value & 0x1f)
+          else
+            @mask.value |= (value & 0x1f)
+          end
+          if mask.value.anybits?(status.value & 0x1f)
+            assert!(arm_delay) unless interrupted?
+          elsif @pending == 1 && @read_two_cycles_ago
+            # On the 6526, masking the pending source cancels the assert due
+            # on the next cycle only while a read two cycles back is
+            # acknowledging.
+            @pending = 0
+          end
+        end
+
+        private
+
+        # Arming a pending source raises IR two cycles later on the 6526,
+        # and one cycle later on the 6526A.
+        def arm_delay = @fast ? 1 : 2
+
+        # What a read on the cycle before still holds: IR on the 6526, and
+        # every bit it read on the 6526A.
+        def held(last) = @fast ? last : last & 0x80
+
+        def source_bit(source)
+          case source
+          when :timer_a then 0x01
+          when :timer_b then 0x02
+          when :alarm then 0x04
+          when :serial then 0x08
+          when :flag then 0x10
+          else raise ArgumentError, "unknown interrupt source #{source}"
+          end
+        end
+      end
+    end
+  end
+end