therubyracer 0.8.1.pre2 → 0.8.1

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Files changed (877) hide show
  1. data/Changelog.md +2 -1
  2. data/README.md +6 -3
  3. data/ext/v8/upstream/3.1.8/.gitignore +31 -0
  4. data/ext/v8/upstream/3.1.8/AUTHORS +40 -0
  5. data/ext/v8/upstream/3.1.8/ChangeLog +2566 -0
  6. data/ext/v8/upstream/3.1.8/LICENSE +52 -0
  7. data/ext/v8/upstream/3.1.8/LICENSE.strongtalk +29 -0
  8. data/ext/v8/upstream/3.1.8/LICENSE.v8 +26 -0
  9. data/ext/v8/upstream/3.1.8/LICENSE.valgrind +45 -0
  10. data/ext/v8/upstream/3.1.8/SConstruct +1192 -0
  11. data/ext/v8/upstream/3.1.8/build/README.txt +25 -0
  12. data/ext/v8/upstream/3.1.8/build/all.gyp +18 -0
  13. data/ext/v8/upstream/3.1.8/build/armu.gypi +32 -0
  14. data/ext/v8/upstream/3.1.8/build/common.gypi +82 -0
  15. data/ext/v8/upstream/3.1.8/build/gyp_v8 +145 -0
  16. data/ext/v8/upstream/3.1.8/include/v8-debug.h +384 -0
  17. data/ext/v8/upstream/3.1.8/include/v8-preparser.h +116 -0
  18. data/ext/v8/upstream/3.1.8/include/v8-profiler.h +426 -0
  19. data/ext/v8/upstream/3.1.8/include/v8-testing.h +99 -0
  20. data/ext/v8/upstream/3.1.8/include/v8.h +3846 -0
  21. data/ext/v8/upstream/3.1.8/include/v8stdint.h +53 -0
  22. data/ext/v8/upstream/3.1.8/preparser/preparser-process.cc +206 -0
  23. data/ext/v8/upstream/3.1.8/src/SConscript +356 -0
  24. data/ext/v8/upstream/3.1.8/src/accessors.cc +907 -0
  25. data/ext/v8/upstream/3.1.8/src/accessors.h +121 -0
  26. data/ext/v8/upstream/3.1.8/src/allocation.cc +204 -0
  27. data/ext/v8/upstream/3.1.8/src/allocation.h +176 -0
  28. data/ext/v8/upstream/3.1.8/src/api.cc +5191 -0
  29. data/ext/v8/upstream/3.1.8/src/api.h +508 -0
  30. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/apinatives.js +0 -0
  31. data/ext/v8/upstream/3.1.8/src/apiutils.h +80 -0
  32. data/ext/v8/upstream/3.1.8/src/arguments.h +105 -0
  33. data/ext/v8/upstream/3.1.8/src/arm/assembler-arm-inl.h +352 -0
  34. data/ext/v8/upstream/3.1.8/src/arm/assembler-arm.cc +2756 -0
  35. data/ext/v8/upstream/3.1.8/src/arm/assembler-arm.h +1294 -0
  36. data/ext/v8/upstream/3.1.8/src/arm/builtins-arm.cc +1628 -0
  37. data/ext/v8/upstream/3.1.8/src/arm/code-stubs-arm.cc +6783 -0
  38. data/ext/v8/upstream/3.1.8/src/arm/code-stubs-arm.h +657 -0
  39. data/ext/v8/upstream/3.1.8/src/arm/codegen-arm-inl.h +48 -0
  40. data/ext/v8/upstream/3.1.8/src/arm/codegen-arm.cc +7403 -0
  41. data/ext/v8/upstream/3.1.8/src/arm/codegen-arm.h +595 -0
  42. data/ext/v8/upstream/3.1.8/src/arm/constants-arm.cc +152 -0
  43. data/ext/v8/upstream/3.1.8/src/arm/constants-arm.h +769 -0
  44. data/ext/v8/upstream/3.1.8/src/arm/cpu-arm.cc +147 -0
  45. data/ext/v8/upstream/3.1.8/src/arm/debug-arm.cc +315 -0
  46. data/ext/v8/upstream/3.1.8/src/arm/deoptimizer-arm.cc +700 -0
  47. data/ext/v8/upstream/3.1.8/src/arm/disasm-arm.cc +1439 -0
  48. data/ext/v8/upstream/3.1.8/src/arm/frames-arm.cc +45 -0
  49. data/ext/v8/upstream/3.1.8/src/arm/frames-arm.h +168 -0
  50. data/ext/v8/upstream/3.1.8/src/arm/full-codegen-arm.cc +4230 -0
  51. data/ext/v8/upstream/3.1.8/src/arm/ic-arm.cc +1799 -0
  52. data/ext/v8/upstream/3.1.8/src/arm/jump-target-arm.cc +174 -0
  53. data/ext/v8/upstream/3.1.8/src/arm/lithium-arm.cc +2041 -0
  54. data/ext/v8/upstream/3.1.8/src/arm/lithium-arm.h +2046 -0
  55. data/ext/v8/upstream/3.1.8/src/arm/lithium-codegen-arm.cc +3822 -0
  56. data/ext/v8/upstream/3.1.8/src/arm/lithium-codegen-arm.h +312 -0
  57. data/ext/v8/upstream/3.1.8/src/arm/lithium-gap-resolver-arm.cc +303 -0
  58. data/ext/v8/upstream/3.1.8/src/arm/lithium-gap-resolver-arm.h +84 -0
  59. data/ext/v8/upstream/3.1.8/src/arm/macro-assembler-arm.cc +2701 -0
  60. data/ext/v8/upstream/3.1.8/src/arm/macro-assembler-arm.h +1015 -0
  61. data/ext/v8/upstream/3.1.8/src/arm/regexp-macro-assembler-arm.cc +1280 -0
  62. data/ext/v8/upstream/3.1.8/src/arm/regexp-macro-assembler-arm.h +252 -0
  63. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/register-allocator-arm-inl.h +0 -0
  64. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/register-allocator-arm.cc +0 -0
  65. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/register-allocator-arm.h +0 -0
  66. data/ext/v8/upstream/3.1.8/src/arm/simulator-arm.cc +3165 -0
  67. data/ext/v8/upstream/3.1.8/src/arm/simulator-arm.h +402 -0
  68. data/ext/v8/upstream/3.1.8/src/arm/stub-cache-arm.cc +4077 -0
  69. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/virtual-frame-arm-inl.h +0 -0
  70. data/ext/v8/upstream/3.1.8/src/arm/virtual-frame-arm.cc +843 -0
  71. data/ext/v8/upstream/3.1.8/src/arm/virtual-frame-arm.h +520 -0
  72. data/ext/v8/upstream/3.1.8/src/array.js +1231 -0
  73. data/ext/v8/upstream/3.1.8/src/assembler.cc +973 -0
  74. data/ext/v8/upstream/3.1.8/src/assembler.h +787 -0
  75. data/ext/v8/upstream/3.1.8/src/ast-inl.h +107 -0
  76. data/ext/v8/upstream/3.1.8/src/ast.cc +1067 -0
  77. data/ext/v8/upstream/3.1.8/src/ast.h +2177 -0
  78. data/ext/v8/upstream/3.1.8/src/atomicops.h +165 -0
  79. data/ext/v8/upstream/3.1.8/src/atomicops_internals_arm_gcc.h +145 -0
  80. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_gcc.cc +126 -0
  81. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_gcc.h +287 -0
  82. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_macosx.h +301 -0
  83. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_msvc.h +203 -0
  84. data/ext/v8/upstream/3.1.8/src/bignum-dtoa.cc +655 -0
  85. data/ext/v8/upstream/3.1.8/src/bignum-dtoa.h +81 -0
  86. data/ext/v8/upstream/3.1.8/src/bignum.cc +768 -0
  87. data/ext/v8/upstream/3.1.8/src/bignum.h +140 -0
  88. data/ext/v8/upstream/3.1.8/src/bootstrapper.cc +1888 -0
  89. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/bootstrapper.h +0 -0
  90. data/ext/v8/upstream/3.1.8/src/builtins.cc +1586 -0
  91. data/ext/v8/upstream/3.1.8/src/builtins.h +339 -0
  92. data/ext/v8/upstream/3.1.8/src/bytecodes-irregexp.h +105 -0
  93. data/ext/v8/upstream/3.1.8/src/cached-powers.cc +177 -0
  94. data/ext/v8/upstream/3.1.8/src/cached-powers.h +65 -0
  95. data/ext/v8/upstream/3.1.8/src/char-predicates-inl.h +94 -0
  96. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/char-predicates.h +0 -0
  97. data/ext/v8/upstream/3.1.8/src/checks.cc +110 -0
  98. data/ext/v8/upstream/3.1.8/src/checks.h +292 -0
  99. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/circular-queue-inl.h +0 -0
  100. data/ext/v8/upstream/3.1.8/src/circular-queue.cc +122 -0
  101. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/circular-queue.h +0 -0
  102. data/ext/v8/upstream/3.1.8/src/code-stubs.cc +230 -0
  103. data/ext/v8/upstream/3.1.8/src/code-stubs.h +950 -0
  104. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/code.h +0 -0
  105. data/ext/v8/upstream/3.1.8/src/codegen-inl.h +64 -0
  106. data/ext/v8/upstream/3.1.8/src/codegen.cc +495 -0
  107. data/ext/v8/upstream/3.1.8/src/codegen.h +245 -0
  108. data/ext/v8/upstream/3.1.8/src/compilation-cache.cc +654 -0
  109. data/ext/v8/upstream/3.1.8/src/compilation-cache.h +112 -0
  110. data/ext/v8/upstream/3.1.8/src/compiler.cc +806 -0
  111. data/ext/v8/upstream/3.1.8/src/compiler.h +290 -0
  112. data/ext/v8/upstream/3.1.8/src/contexts.cc +320 -0
  113. data/ext/v8/upstream/3.1.8/src/contexts.h +376 -0
  114. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/conversions-inl.h +0 -0
  115. data/ext/v8/upstream/3.1.8/src/conversions.cc +1069 -0
  116. data/ext/v8/upstream/3.1.8/src/conversions.h +122 -0
  117. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/counters.cc +0 -0
  118. data/ext/v8/upstream/3.1.8/src/counters.h +242 -0
  119. data/ext/v8/upstream/3.1.8/src/cpu-profiler-inl.h +100 -0
  120. data/ext/v8/upstream/3.1.8/src/cpu-profiler.cc +554 -0
  121. data/ext/v8/upstream/3.1.8/src/cpu-profiler.h +291 -0
  122. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/cpu.h +0 -0
  123. data/ext/v8/upstream/3.1.8/src/d8-debug.cc +367 -0
  124. data/ext/v8/upstream/3.1.8/src/d8-debug.h +157 -0
  125. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/d8-posix.cc +0 -0
  126. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/d8-readline.cc +0 -0
  127. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/d8-windows.cc +0 -0
  128. data/ext/v8/upstream/3.1.8/src/d8.cc +792 -0
  129. data/ext/v8/upstream/3.1.8/src/d8.gyp +85 -0
  130. data/ext/v8/upstream/3.1.8/src/d8.h +231 -0
  131. data/ext/v8/upstream/3.1.8/src/d8.js +2798 -0
  132. data/ext/v8/upstream/3.1.8/src/data-flow.cc +545 -0
  133. data/ext/v8/upstream/3.1.8/src/data-flow.h +379 -0
  134. data/ext/v8/upstream/3.1.8/src/date.js +1103 -0
  135. data/ext/v8/upstream/3.1.8/src/dateparser-inl.h +125 -0
  136. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/dateparser.cc +0 -0
  137. data/ext/v8/upstream/3.1.8/src/dateparser.h +263 -0
  138. data/ext/v8/upstream/3.1.8/src/debug-agent.cc +446 -0
  139. data/ext/v8/upstream/3.1.8/src/debug-agent.h +131 -0
  140. data/ext/v8/upstream/3.1.8/src/debug-debugger.js +2569 -0
  141. data/ext/v8/upstream/3.1.8/src/debug.cc +3085 -0
  142. data/ext/v8/upstream/3.1.8/src/debug.h +1025 -0
  143. data/ext/v8/upstream/3.1.8/src/deoptimizer.cc +1185 -0
  144. data/ext/v8/upstream/3.1.8/src/deoptimizer.h +529 -0
  145. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/disasm.h +0 -0
  146. data/ext/v8/upstream/3.1.8/src/disassembler.cc +338 -0
  147. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/disassembler.h +0 -0
  148. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/diy-fp.cc +0 -0
  149. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/diy-fp.h +0 -0
  150. data/ext/v8/upstream/3.1.8/src/double.h +238 -0
  151. data/ext/v8/upstream/3.1.8/src/dtoa.cc +103 -0
  152. data/ext/v8/upstream/3.1.8/src/dtoa.h +85 -0
  153. data/ext/v8/upstream/3.1.8/src/execution.cc +735 -0
  154. data/ext/v8/upstream/3.1.8/src/execution.h +322 -0
  155. data/ext/v8/upstream/3.1.8/src/extensions/experimental/experimental.gyp +53 -0
  156. data/ext/v8/upstream/3.1.8/src/extensions/experimental/i18n-extension.cc +264 -0
  157. data/ext/v8/upstream/3.1.8/src/extensions/experimental/i18n-extension.h +64 -0
  158. data/ext/v8/upstream/3.1.8/src/extensions/externalize-string-extension.cc +141 -0
  159. data/ext/v8/upstream/3.1.8/src/extensions/externalize-string-extension.h +50 -0
  160. data/ext/v8/upstream/3.1.8/src/extensions/gc-extension.cc +58 -0
  161. data/ext/v8/upstream/3.1.8/src/extensions/gc-extension.h +49 -0
  162. data/ext/v8/upstream/3.1.8/src/factory.cc +1087 -0
  163. data/ext/v8/upstream/3.1.8/src/factory.h +432 -0
  164. data/ext/v8/upstream/3.1.8/src/fast-dtoa.cc +736 -0
  165. data/ext/v8/upstream/3.1.8/src/fast-dtoa.h +83 -0
  166. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/fixed-dtoa.cc +0 -0
  167. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/fixed-dtoa.h +0 -0
  168. data/ext/v8/upstream/3.1.8/src/flag-definitions.h +552 -0
  169. data/ext/v8/upstream/3.1.8/src/flags.cc +551 -0
  170. data/ext/v8/upstream/3.1.8/src/flags.h +79 -0
  171. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/frame-element.cc +0 -0
  172. data/ext/v8/upstream/3.1.8/src/frame-element.h +277 -0
  173. data/ext/v8/upstream/3.1.8/src/frames-inl.h +210 -0
  174. data/ext/v8/upstream/3.1.8/src/frames.cc +1232 -0
  175. data/ext/v8/upstream/3.1.8/src/frames.h +826 -0
  176. data/ext/v8/upstream/3.1.8/src/full-codegen.cc +1382 -0
  177. data/ext/v8/upstream/3.1.8/src/full-codegen.h +751 -0
  178. data/ext/v8/upstream/3.1.8/src/func-name-inferrer.cc +90 -0
  179. data/ext/v8/upstream/3.1.8/src/func-name-inferrer.h +111 -0
  180. data/ext/v8/upstream/3.1.8/src/gdb-jit.cc +1547 -0
  181. data/ext/v8/upstream/3.1.8/src/gdb-jit.h +138 -0
  182. data/ext/v8/upstream/3.1.8/src/global-handles.cc +534 -0
  183. data/ext/v8/upstream/3.1.8/src/global-handles.h +181 -0
  184. data/ext/v8/upstream/3.1.8/src/globals.h +325 -0
  185. data/ext/v8/upstream/3.1.8/src/handles-inl.h +80 -0
  186. data/ext/v8/upstream/3.1.8/src/handles.cc +910 -0
  187. data/ext/v8/upstream/3.1.8/src/handles.h +424 -0
  188. data/ext/v8/upstream/3.1.8/src/hashmap.cc +230 -0
  189. data/ext/v8/upstream/3.1.8/src/hashmap.h +121 -0
  190. data/ext/v8/upstream/3.1.8/src/heap-inl.h +587 -0
  191. data/ext/v8/upstream/3.1.8/src/heap-profiler.cc +1128 -0
  192. data/ext/v8/upstream/3.1.8/src/heap-profiler.h +381 -0
  193. data/ext/v8/upstream/3.1.8/src/heap.cc +5610 -0
  194. data/ext/v8/upstream/3.1.8/src/heap.h +2218 -0
  195. data/ext/v8/upstream/3.1.8/src/hydrogen-instructions.cc +1490 -0
  196. data/ext/v8/upstream/3.1.8/src/hydrogen-instructions.h +3493 -0
  197. data/ext/v8/upstream/3.1.8/src/hydrogen.cc +6056 -0
  198. data/ext/v8/upstream/3.1.8/src/hydrogen.h +1091 -0
  199. data/ext/v8/upstream/3.1.8/src/ia32/assembler-ia32-inl.h +429 -0
  200. data/ext/v8/upstream/3.1.8/src/ia32/assembler-ia32.cc +2800 -0
  201. data/ext/v8/upstream/3.1.8/src/ia32/assembler-ia32.h +1093 -0
  202. data/ext/v8/upstream/3.1.8/src/ia32/builtins-ia32.cc +1590 -0
  203. data/ext/v8/upstream/3.1.8/src/ia32/code-stubs-ia32.cc +6624 -0
  204. data/ext/v8/upstream/3.1.8/src/ia32/code-stubs-ia32.h +536 -0
  205. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/codegen-ia32-inl.h +0 -0
  206. data/ext/v8/upstream/3.1.8/src/ia32/codegen-ia32.cc +10354 -0
  207. data/ext/v8/upstream/3.1.8/src/ia32/codegen-ia32.h +798 -0
  208. data/ext/v8/upstream/3.1.8/src/ia32/cpu-ia32.cc +87 -0
  209. data/ext/v8/upstream/3.1.8/src/ia32/debug-ia32.cc +309 -0
  210. data/ext/v8/upstream/3.1.8/src/ia32/deoptimizer-ia32.cc +664 -0
  211. data/ext/v8/upstream/3.1.8/src/ia32/disasm-ia32.cc +1597 -0
  212. data/ext/v8/upstream/3.1.8/src/ia32/frames-ia32.cc +45 -0
  213. data/ext/v8/upstream/3.1.8/src/ia32/frames-ia32.h +140 -0
  214. data/ext/v8/upstream/3.1.8/src/ia32/full-codegen-ia32.cc +4278 -0
  215. data/ext/v8/upstream/3.1.8/src/ia32/ic-ia32.cc +1786 -0
  216. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/jump-target-ia32.cc +0 -0
  217. data/ext/v8/upstream/3.1.8/src/ia32/lithium-codegen-ia32.cc +3880 -0
  218. data/ext/v8/upstream/3.1.8/src/ia32/lithium-codegen-ia32.h +309 -0
  219. data/ext/v8/upstream/3.1.8/src/ia32/lithium-gap-resolver-ia32.cc +460 -0
  220. data/ext/v8/upstream/3.1.8/src/ia32/lithium-gap-resolver-ia32.h +110 -0
  221. data/ext/v8/upstream/3.1.8/src/ia32/lithium-ia32.cc +2095 -0
  222. data/ext/v8/upstream/3.1.8/src/ia32/lithium-ia32.h +2127 -0
  223. data/ext/v8/upstream/3.1.8/src/ia32/macro-assembler-ia32.cc +2031 -0
  224. data/ext/v8/upstream/3.1.8/src/ia32/macro-assembler-ia32.h +798 -0
  225. data/ext/v8/upstream/3.1.8/src/ia32/regexp-macro-assembler-ia32.cc +1253 -0
  226. data/ext/v8/upstream/3.1.8/src/ia32/regexp-macro-assembler-ia32.h +215 -0
  227. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/register-allocator-ia32-inl.h +0 -0
  228. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/register-allocator-ia32.cc +0 -0
  229. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/register-allocator-ia32.h +0 -0
  230. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/simulator-ia32.cc +0 -0
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  232. data/ext/v8/upstream/3.1.8/src/ia32/stub-cache-ia32.cc +3732 -0
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  689. data/ext/v8/upstream/2.3.3/src/ia32/ic-ia32.cc +0 -1966
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@@ -0,0 +1,1439 @@
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+ // Copyright 2010 the V8 project authors. All rights reserved.
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+ // Redistribution and use in source and binary forms, with or without
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+ // modification, are permitted provided that the following conditions are
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+ // met:
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+ //
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+ // * Redistributions of source code must retain the above copyright
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+ // notice, this list of conditions and the following disclaimer.
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+ // * Redistributions in binary form must reproduce the above
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+ // copyright notice, this list of conditions and the following
10
+ // disclaimer in the documentation and/or other materials provided
11
+ // with the distribution.
12
+ // * Neither the name of Google Inc. nor the names of its
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+ // contributors may be used to endorse or promote products derived
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+ // from this software without specific prior written permission.
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+ //
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+ // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
+ // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
+ // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+
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+ // A Disassembler object is used to disassemble a block of code instruction by
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+ // instruction. The default implementation of the NameConverter object can be
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+ // overriden to modify register names or to do symbol lookup on addresses.
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+ //
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+ // The example below will disassemble a block of code and print it to stdout.
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+ //
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+ // NameConverter converter;
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+ // Disassembler d(converter);
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+ // for (byte* pc = begin; pc < end;) {
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+ // v8::internal::EmbeddedVector<char, 256> buffer;
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+ // byte* prev_pc = pc;
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+ // pc += d.InstructionDecode(buffer, pc);
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+ // printf("%p %08x %s\n",
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+ // prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
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+ // }
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+ //
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+ // The Disassembler class also has a convenience method to disassemble a block
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+ // of code into a FILE*, meaning that the above functionality could also be
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+ // achieved by just calling Disassembler::Disassemble(stdout, begin, end);
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+
48
+
49
+ #include <assert.h>
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+ #include <stdio.h>
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+ #include <stdarg.h>
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+ #include <string.h>
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+ #ifndef WIN32
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+ #include <stdint.h>
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+ #endif
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+
57
+ #include "v8.h"
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+
59
+ #if defined(V8_TARGET_ARCH_ARM)
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+
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+ #include "constants-arm.h"
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+ #include "disasm.h"
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+ #include "macro-assembler.h"
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+ #include "platform.h"
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+
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+
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+ namespace v8 {
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+ namespace internal {
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+
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+
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+ //------------------------------------------------------------------------------
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+
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+ // Decoder decodes and disassembles instructions into an output buffer.
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+ // It uses the converter to convert register names and call destinations into
75
+ // more informative description.
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+ class Decoder {
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+ public:
78
+ Decoder(const disasm::NameConverter& converter,
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+ Vector<char> out_buffer)
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+ : converter_(converter),
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+ out_buffer_(out_buffer),
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+ out_buffer_pos_(0) {
83
+ out_buffer_[out_buffer_pos_] = '\0';
84
+ }
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+
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+ ~Decoder() {}
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+
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+ // Writes one disassembled instruction into 'buffer' (0-terminated).
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+ // Returns the length of the disassembled machine instruction in bytes.
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+ int InstructionDecode(byte* instruction);
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+
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+ private:
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+ // Bottleneck functions to print into the out_buffer.
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+ void PrintChar(const char ch);
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+ void Print(const char* str);
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+
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+ // Printing of common values.
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+ void PrintRegister(int reg);
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+ void PrintSRegister(int reg);
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+ void PrintDRegister(int reg);
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+ int FormatVFPRegister(Instruction* instr, const char* format);
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+ void PrintMovwMovt(Instruction* instr);
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+ int FormatVFPinstruction(Instruction* instr, const char* format);
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+ void PrintCondition(Instruction* instr);
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+ void PrintShiftRm(Instruction* instr);
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+ void PrintShiftImm(Instruction* instr);
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+ void PrintShiftSat(Instruction* instr);
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+ void PrintPU(Instruction* instr);
109
+ void PrintSoftwareInterrupt(SoftwareInterruptCodes svc);
110
+
111
+ // Handle formatting of instructions and their options.
112
+ int FormatRegister(Instruction* instr, const char* option);
113
+ int FormatOption(Instruction* instr, const char* option);
114
+ void Format(Instruction* instr, const char* format);
115
+ void Unknown(Instruction* instr);
116
+
117
+ // Each of these functions decodes one particular instruction type, a 3-bit
118
+ // field in the instruction encoding.
119
+ // Types 0 and 1 are combined as they are largely the same except for the way
120
+ // they interpret the shifter operand.
121
+ void DecodeType01(Instruction* instr);
122
+ void DecodeType2(Instruction* instr);
123
+ void DecodeType3(Instruction* instr);
124
+ void DecodeType4(Instruction* instr);
125
+ void DecodeType5(Instruction* instr);
126
+ void DecodeType6(Instruction* instr);
127
+ // Type 7 includes special Debugger instructions.
128
+ int DecodeType7(Instruction* instr);
129
+ // For VFP support.
130
+ void DecodeTypeVFP(Instruction* instr);
131
+ void DecodeType6CoprocessorIns(Instruction* instr);
132
+
133
+ void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instruction* instr);
134
+ void DecodeVCMP(Instruction* instr);
135
+ void DecodeVCVTBetweenDoubleAndSingle(Instruction* instr);
136
+ void DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr);
137
+
138
+ const disasm::NameConverter& converter_;
139
+ Vector<char> out_buffer_;
140
+ int out_buffer_pos_;
141
+
142
+ DISALLOW_COPY_AND_ASSIGN(Decoder);
143
+ };
144
+
145
+
146
+ // Support for assertions in the Decoder formatting functions.
147
+ #define STRING_STARTS_WITH(string, compare_string) \
148
+ (strncmp(string, compare_string, strlen(compare_string)) == 0)
149
+
150
+
151
+ // Append the ch to the output buffer.
152
+ void Decoder::PrintChar(const char ch) {
153
+ out_buffer_[out_buffer_pos_++] = ch;
154
+ }
155
+
156
+
157
+ // Append the str to the output buffer.
158
+ void Decoder::Print(const char* str) {
159
+ char cur = *str++;
160
+ while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
161
+ PrintChar(cur);
162
+ cur = *str++;
163
+ }
164
+ out_buffer_[out_buffer_pos_] = 0;
165
+ }
166
+
167
+
168
+ // These condition names are defined in a way to match the native disassembler
169
+ // formatting. See for example the command "objdump -d <binary file>".
170
+ static const char* cond_names[kNumberOfConditions] = {
171
+ "eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
172
+ "hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
173
+ };
174
+
175
+
176
+ // Print the condition guarding the instruction.
177
+ void Decoder::PrintCondition(Instruction* instr) {
178
+ Print(cond_names[instr->ConditionValue()]);
179
+ }
180
+
181
+
182
+ // Print the register name according to the active name converter.
183
+ void Decoder::PrintRegister(int reg) {
184
+ Print(converter_.NameOfCPURegister(reg));
185
+ }
186
+
187
+ // Print the VFP S register name according to the active name converter.
188
+ void Decoder::PrintSRegister(int reg) {
189
+ Print(VFPRegisters::Name(reg, false));
190
+ }
191
+
192
+ // Print the VFP D register name according to the active name converter.
193
+ void Decoder::PrintDRegister(int reg) {
194
+ Print(VFPRegisters::Name(reg, true));
195
+ }
196
+
197
+
198
+ // These shift names are defined in a way to match the native disassembler
199
+ // formatting. See for example the command "objdump -d <binary file>".
200
+ static const char* shift_names[kNumberOfShifts] = {
201
+ "lsl", "lsr", "asr", "ror"
202
+ };
203
+
204
+
205
+ // Print the register shift operands for the instruction. Generally used for
206
+ // data processing instructions.
207
+ void Decoder::PrintShiftRm(Instruction* instr) {
208
+ ShiftOp shift = instr->ShiftField();
209
+ int shift_index = instr->ShiftValue();
210
+ int shift_amount = instr->ShiftAmountValue();
211
+ int rm = instr->RmValue();
212
+
213
+ PrintRegister(rm);
214
+
215
+ if ((instr->RegShiftValue() == 0) && (shift == LSL) && (shift_amount == 0)) {
216
+ // Special case for using rm only.
217
+ return;
218
+ }
219
+ if (instr->RegShiftValue() == 0) {
220
+ // by immediate
221
+ if ((shift == ROR) && (shift_amount == 0)) {
222
+ Print(", RRX");
223
+ return;
224
+ } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
225
+ shift_amount = 32;
226
+ }
227
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
228
+ ", %s #%d",
229
+ shift_names[shift_index],
230
+ shift_amount);
231
+ } else {
232
+ // by register
233
+ int rs = instr->RsValue();
234
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
235
+ ", %s ", shift_names[shift_index]);
236
+ PrintRegister(rs);
237
+ }
238
+ }
239
+
240
+
241
+ // Print the immediate operand for the instruction. Generally used for data
242
+ // processing instructions.
243
+ void Decoder::PrintShiftImm(Instruction* instr) {
244
+ int rotate = instr->RotateValue() * 2;
245
+ int immed8 = instr->Immed8Value();
246
+ int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
247
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
248
+ "#%d", imm);
249
+ }
250
+
251
+
252
+ // Print the optional shift and immediate used by saturating instructions.
253
+ void Decoder::PrintShiftSat(Instruction* instr) {
254
+ int shift = instr->Bits(11, 7);
255
+ if (shift > 0) {
256
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
257
+ ", %s #%d",
258
+ shift_names[instr->Bit(6) * 2],
259
+ instr->Bits(11, 7));
260
+ }
261
+ }
262
+
263
+
264
+ // Print PU formatting to reduce complexity of FormatOption.
265
+ void Decoder::PrintPU(Instruction* instr) {
266
+ switch (instr->PUField()) {
267
+ case da_x: {
268
+ Print("da");
269
+ break;
270
+ }
271
+ case ia_x: {
272
+ Print("ia");
273
+ break;
274
+ }
275
+ case db_x: {
276
+ Print("db");
277
+ break;
278
+ }
279
+ case ib_x: {
280
+ Print("ib");
281
+ break;
282
+ }
283
+ default: {
284
+ UNREACHABLE();
285
+ break;
286
+ }
287
+ }
288
+ }
289
+
290
+
291
+ // Print SoftwareInterrupt codes. Factoring this out reduces the complexity of
292
+ // the FormatOption method.
293
+ void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) {
294
+ switch (svc) {
295
+ case kCallRtRedirected:
296
+ Print("call rt redirected");
297
+ return;
298
+ case kBreakpoint:
299
+ Print("breakpoint");
300
+ return;
301
+ default:
302
+ if (svc >= kStopCode) {
303
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
304
+ "%d - 0x%x",
305
+ svc & kStopCodeMask,
306
+ svc & kStopCodeMask);
307
+ } else {
308
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
309
+ "%d",
310
+ svc);
311
+ }
312
+ return;
313
+ }
314
+ }
315
+
316
+
317
+ // Handle all register based formatting in this function to reduce the
318
+ // complexity of FormatOption.
319
+ int Decoder::FormatRegister(Instruction* instr, const char* format) {
320
+ ASSERT(format[0] == 'r');
321
+ if (format[1] == 'n') { // 'rn: Rn register
322
+ int reg = instr->RnValue();
323
+ PrintRegister(reg);
324
+ return 2;
325
+ } else if (format[1] == 'd') { // 'rd: Rd register
326
+ int reg = instr->RdValue();
327
+ PrintRegister(reg);
328
+ return 2;
329
+ } else if (format[1] == 's') { // 'rs: Rs register
330
+ int reg = instr->RsValue();
331
+ PrintRegister(reg);
332
+ return 2;
333
+ } else if (format[1] == 'm') { // 'rm: Rm register
334
+ int reg = instr->RmValue();
335
+ PrintRegister(reg);
336
+ return 2;
337
+ } else if (format[1] == 't') { // 'rt: Rt register
338
+ int reg = instr->RtValue();
339
+ PrintRegister(reg);
340
+ return 2;
341
+ } else if (format[1] == 'l') {
342
+ // 'rlist: register list for load and store multiple instructions
343
+ ASSERT(STRING_STARTS_WITH(format, "rlist"));
344
+ int rlist = instr->RlistValue();
345
+ int reg = 0;
346
+ Print("{");
347
+ // Print register list in ascending order, by scanning the bit mask.
348
+ while (rlist != 0) {
349
+ if ((rlist & 1) != 0) {
350
+ PrintRegister(reg);
351
+ if ((rlist >> 1) != 0) {
352
+ Print(", ");
353
+ }
354
+ }
355
+ reg++;
356
+ rlist >>= 1;
357
+ }
358
+ Print("}");
359
+ return 5;
360
+ }
361
+ UNREACHABLE();
362
+ return -1;
363
+ }
364
+
365
+
366
+ // Handle all VFP register based formatting in this function to reduce the
367
+ // complexity of FormatOption.
368
+ int Decoder::FormatVFPRegister(Instruction* instr, const char* format) {
369
+ ASSERT((format[0] == 'S') || (format[0] == 'D'));
370
+
371
+ if (format[1] == 'n') {
372
+ int reg = instr->VnValue();
373
+ if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->NValue()));
374
+ if (format[0] == 'D') PrintDRegister(reg);
375
+ return 2;
376
+ } else if (format[1] == 'm') {
377
+ int reg = instr->VmValue();
378
+ if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->MValue()));
379
+ if (format[0] == 'D') PrintDRegister(reg);
380
+ return 2;
381
+ } else if (format[1] == 'd') {
382
+ int reg = instr->VdValue();
383
+ if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->DValue()));
384
+ if (format[0] == 'D') PrintDRegister(reg);
385
+ return 2;
386
+ }
387
+
388
+ UNREACHABLE();
389
+ return -1;
390
+ }
391
+
392
+
393
+ int Decoder::FormatVFPinstruction(Instruction* instr, const char* format) {
394
+ Print(format);
395
+ return 0;
396
+ }
397
+
398
+
399
+ // Print the movw or movt instruction.
400
+ void Decoder::PrintMovwMovt(Instruction* instr) {
401
+ int imm = instr->ImmedMovwMovtValue();
402
+ int rd = instr->RdValue();
403
+ PrintRegister(rd);
404
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
405
+ ", #%d", imm);
406
+ }
407
+
408
+
409
+ // FormatOption takes a formatting string and interprets it based on
410
+ // the current instructions. The format string points to the first
411
+ // character of the option string (the option escape has already been
412
+ // consumed by the caller.) FormatOption returns the number of
413
+ // characters that were consumed from the formatting string.
414
+ int Decoder::FormatOption(Instruction* instr, const char* format) {
415
+ switch (format[0]) {
416
+ case 'a': { // 'a: accumulate multiplies
417
+ if (instr->Bit(21) == 0) {
418
+ Print("ul");
419
+ } else {
420
+ Print("la");
421
+ }
422
+ return 1;
423
+ }
424
+ case 'b': { // 'b: byte loads or stores
425
+ if (instr->HasB()) {
426
+ Print("b");
427
+ }
428
+ return 1;
429
+ }
430
+ case 'c': { // 'cond: conditional execution
431
+ ASSERT(STRING_STARTS_WITH(format, "cond"));
432
+ PrintCondition(instr);
433
+ return 4;
434
+ }
435
+ case 'd': { // 'd: vmov double immediate.
436
+ double d = instr->DoubleImmedVmov();
437
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
438
+ "#%g", d);
439
+ return 1;
440
+ }
441
+ case 'f': { // 'f: bitfield instructions - v7 and above.
442
+ uint32_t lsbit = instr->Bits(11, 7);
443
+ uint32_t width = instr->Bits(20, 16) + 1;
444
+ if (instr->Bit(21) == 0) {
445
+ // BFC/BFI:
446
+ // Bits 20-16 represent most-significant bit. Covert to width.
447
+ width -= lsbit;
448
+ ASSERT(width > 0);
449
+ }
450
+ ASSERT((width + lsbit) <= 32);
451
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
452
+ "#%d, #%d", lsbit, width);
453
+ return 1;
454
+ }
455
+ case 'h': { // 'h: halfword operation for extra loads and stores
456
+ if (instr->HasH()) {
457
+ Print("h");
458
+ } else {
459
+ Print("b");
460
+ }
461
+ return 1;
462
+ }
463
+ case 'i': { // 'i: immediate value from adjacent bits.
464
+ // Expects tokens in the form imm%02d@%02d, ie. imm05@07, imm10@16
465
+ int width = (format[3] - '0') * 10 + (format[4] - '0');
466
+ int lsb = (format[6] - '0') * 10 + (format[7] - '0');
467
+
468
+ ASSERT((width >= 1) && (width <= 32));
469
+ ASSERT((lsb >= 0) && (lsb <= 31));
470
+ ASSERT((width + lsb) <= 32);
471
+
472
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
473
+ "%d",
474
+ instr->Bits(width + lsb - 1, lsb));
475
+ return 8;
476
+ }
477
+ case 'l': { // 'l: branch and link
478
+ if (instr->HasLink()) {
479
+ Print("l");
480
+ }
481
+ return 1;
482
+ }
483
+ case 'm': {
484
+ if (format[1] == 'w') {
485
+ // 'mw: movt/movw instructions.
486
+ PrintMovwMovt(instr);
487
+ return 2;
488
+ }
489
+ if (format[1] == 'e') { // 'memop: load/store instructions.
490
+ ASSERT(STRING_STARTS_WITH(format, "memop"));
491
+ if (instr->HasL()) {
492
+ Print("ldr");
493
+ } else if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0)) {
494
+ if (instr->Bits(7, 4) == 0xf) {
495
+ Print("strd");
496
+ } else {
497
+ Print("ldrd");
498
+ }
499
+ } else {
500
+ Print("str");
501
+ }
502
+ return 5;
503
+ }
504
+ // 'msg: for simulator break instructions
505
+ ASSERT(STRING_STARTS_WITH(format, "msg"));
506
+ byte* str =
507
+ reinterpret_cast<byte*>(instr->InstructionBits() & 0x0fffffff);
508
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
509
+ "%s", converter_.NameInCode(str));
510
+ return 3;
511
+ }
512
+ case 'o': {
513
+ if ((format[3] == '1') && (format[4] == '2')) {
514
+ // 'off12: 12-bit offset for load and store instructions
515
+ ASSERT(STRING_STARTS_WITH(format, "off12"));
516
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
517
+ "%d", instr->Offset12Value());
518
+ return 5;
519
+ } else if (format[3] == '0') {
520
+ // 'off0to3and8to19 16-bit immediate encoded in bits 19-8 and 3-0.
521
+ ASSERT(STRING_STARTS_WITH(format, "off0to3and8to19"));
522
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
523
+ "%d",
524
+ (instr->Bits(19, 8) << 4) +
525
+ instr->Bits(3, 0));
526
+ return 15;
527
+ }
528
+ // 'off8: 8-bit offset for extra load and store instructions
529
+ ASSERT(STRING_STARTS_WITH(format, "off8"));
530
+ int offs8 = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
531
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
532
+ "%d", offs8);
533
+ return 4;
534
+ }
535
+ case 'p': { // 'pu: P and U bits for load and store instructions
536
+ ASSERT(STRING_STARTS_WITH(format, "pu"));
537
+ PrintPU(instr);
538
+ return 2;
539
+ }
540
+ case 'r': {
541
+ return FormatRegister(instr, format);
542
+ }
543
+ case 's': {
544
+ if (format[1] == 'h') { // 'shift_op or 'shift_rm or 'shift_sat.
545
+ if (format[6] == 'o') { // 'shift_op
546
+ ASSERT(STRING_STARTS_WITH(format, "shift_op"));
547
+ if (instr->TypeValue() == 0) {
548
+ PrintShiftRm(instr);
549
+ } else {
550
+ ASSERT(instr->TypeValue() == 1);
551
+ PrintShiftImm(instr);
552
+ }
553
+ return 8;
554
+ } else if (format[6] == 's') { // 'shift_sat.
555
+ ASSERT(STRING_STARTS_WITH(format, "shift_sat"));
556
+ PrintShiftSat(instr);
557
+ return 9;
558
+ } else { // 'shift_rm
559
+ ASSERT(STRING_STARTS_WITH(format, "shift_rm"));
560
+ PrintShiftRm(instr);
561
+ return 8;
562
+ }
563
+ } else if (format[1] == 'v') { // 'svc
564
+ ASSERT(STRING_STARTS_WITH(format, "svc"));
565
+ PrintSoftwareInterrupt(instr->SvcValue());
566
+ return 3;
567
+ } else if (format[1] == 'i') { // 'sign: signed extra loads and stores
568
+ ASSERT(STRING_STARTS_WITH(format, "sign"));
569
+ if (instr->HasSign()) {
570
+ Print("s");
571
+ }
572
+ return 4;
573
+ }
574
+ // 's: S field of data processing instructions
575
+ if (instr->HasS()) {
576
+ Print("s");
577
+ }
578
+ return 1;
579
+ }
580
+ case 't': { // 'target: target of branch instructions
581
+ ASSERT(STRING_STARTS_WITH(format, "target"));
582
+ int off = (instr->SImmed24Value() << 2) + 8;
583
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
584
+ "%+d -> %s",
585
+ off,
586
+ converter_.NameOfAddress(
587
+ reinterpret_cast<byte*>(instr) + off));
588
+ return 6;
589
+ }
590
+ case 'u': { // 'u: signed or unsigned multiplies
591
+ // The manual gets the meaning of bit 22 backwards in the multiply
592
+ // instruction overview on page A3.16.2. The instructions that
593
+ // exist in u and s variants are the following:
594
+ // smull A4.1.87
595
+ // umull A4.1.129
596
+ // umlal A4.1.128
597
+ // smlal A4.1.76
598
+ // For these 0 means u and 1 means s. As can be seen on their individual
599
+ // pages. The other 18 mul instructions have the bit set or unset in
600
+ // arbitrary ways that are unrelated to the signedness of the instruction.
601
+ // None of these 18 instructions exist in both a 'u' and an 's' variant.
602
+
603
+ if (instr->Bit(22) == 0) {
604
+ Print("u");
605
+ } else {
606
+ Print("s");
607
+ }
608
+ return 1;
609
+ }
610
+ case 'v': {
611
+ return FormatVFPinstruction(instr, format);
612
+ }
613
+ case 'S':
614
+ case 'D': {
615
+ return FormatVFPRegister(instr, format);
616
+ }
617
+ case 'w': { // 'w: W field of load and store instructions
618
+ if (instr->HasW()) {
619
+ Print("!");
620
+ }
621
+ return 1;
622
+ }
623
+ default: {
624
+ UNREACHABLE();
625
+ break;
626
+ }
627
+ }
628
+ UNREACHABLE();
629
+ return -1;
630
+ }
631
+
632
+
633
+ // Format takes a formatting string for a whole instruction and prints it into
634
+ // the output buffer. All escaped options are handed to FormatOption to be
635
+ // parsed further.
636
+ void Decoder::Format(Instruction* instr, const char* format) {
637
+ char cur = *format++;
638
+ while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
639
+ if (cur == '\'') { // Single quote is used as the formatting escape.
640
+ format += FormatOption(instr, format);
641
+ } else {
642
+ out_buffer_[out_buffer_pos_++] = cur;
643
+ }
644
+ cur = *format++;
645
+ }
646
+ out_buffer_[out_buffer_pos_] = '\0';
647
+ }
648
+
649
+
650
+ // For currently unimplemented decodings the disassembler calls Unknown(instr)
651
+ // which will just print "unknown" of the instruction bits.
652
+ void Decoder::Unknown(Instruction* instr) {
653
+ Format(instr, "unknown");
654
+ }
655
+
656
+
657
+ void Decoder::DecodeType01(Instruction* instr) {
658
+ int type = instr->TypeValue();
659
+ if ((type == 0) && instr->IsSpecialType0()) {
660
+ // multiply instruction or extra loads and stores
661
+ if (instr->Bits(7, 4) == 9) {
662
+ if (instr->Bit(24) == 0) {
663
+ // multiply instructions
664
+ if (instr->Bit(23) == 0) {
665
+ if (instr->Bit(21) == 0) {
666
+ // The MUL instruction description (A 4.1.33) refers to Rd as being
667
+ // the destination for the operation, but it confusingly uses the
668
+ // Rn field to encode it.
669
+ Format(instr, "mul'cond's 'rn, 'rm, 'rs");
670
+ } else {
671
+ // The MLA instruction description (A 4.1.28) refers to the order
672
+ // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
673
+ // Rn field to encode the Rd register and the Rd field to encode
674
+ // the Rn register.
675
+ Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
676
+ }
677
+ } else {
678
+ // The signed/long multiply instructions use the terms RdHi and RdLo
679
+ // when referring to the target registers. They are mapped to the Rn
680
+ // and Rd fields as follows:
681
+ // RdLo == Rd field
682
+ // RdHi == Rn field
683
+ // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
684
+ Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
685
+ }
686
+ } else {
687
+ Unknown(instr); // not used by V8
688
+ }
689
+ } else if ((instr->Bit(20) == 0) && ((instr->Bits(7, 4) & 0xd) == 0xd)) {
690
+ // ldrd, strd
691
+ switch (instr->PUField()) {
692
+ case da_x: {
693
+ if (instr->Bit(22) == 0) {
694
+ Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
695
+ } else {
696
+ Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
697
+ }
698
+ break;
699
+ }
700
+ case ia_x: {
701
+ if (instr->Bit(22) == 0) {
702
+ Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
703
+ } else {
704
+ Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
705
+ }
706
+ break;
707
+ }
708
+ case db_x: {
709
+ if (instr->Bit(22) == 0) {
710
+ Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
711
+ } else {
712
+ Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
713
+ }
714
+ break;
715
+ }
716
+ case ib_x: {
717
+ if (instr->Bit(22) == 0) {
718
+ Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
719
+ } else {
720
+ Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w");
721
+ }
722
+ break;
723
+ }
724
+ default: {
725
+ // The PU field is a 2-bit field.
726
+ UNREACHABLE();
727
+ break;
728
+ }
729
+ }
730
+ } else {
731
+ // extra load/store instructions
732
+ switch (instr->PUField()) {
733
+ case da_x: {
734
+ if (instr->Bit(22) == 0) {
735
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
736
+ } else {
737
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
738
+ }
739
+ break;
740
+ }
741
+ case ia_x: {
742
+ if (instr->Bit(22) == 0) {
743
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
744
+ } else {
745
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
746
+ }
747
+ break;
748
+ }
749
+ case db_x: {
750
+ if (instr->Bit(22) == 0) {
751
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
752
+ } else {
753
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
754
+ }
755
+ break;
756
+ }
757
+ case ib_x: {
758
+ if (instr->Bit(22) == 0) {
759
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
760
+ } else {
761
+ Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
762
+ }
763
+ break;
764
+ }
765
+ default: {
766
+ // The PU field is a 2-bit field.
767
+ UNREACHABLE();
768
+ break;
769
+ }
770
+ }
771
+ return;
772
+ }
773
+ } else if ((type == 0) && instr->IsMiscType0()) {
774
+ if (instr->Bits(22, 21) == 1) {
775
+ switch (instr->BitField(7, 4)) {
776
+ case BX:
777
+ Format(instr, "bx'cond 'rm");
778
+ break;
779
+ case BLX:
780
+ Format(instr, "blx'cond 'rm");
781
+ break;
782
+ case BKPT:
783
+ Format(instr, "bkpt 'off0to3and8to19");
784
+ break;
785
+ default:
786
+ Unknown(instr); // not used by V8
787
+ break;
788
+ }
789
+ } else if (instr->Bits(22, 21) == 3) {
790
+ switch (instr->BitField(7, 4)) {
791
+ case CLZ:
792
+ Format(instr, "clz'cond 'rd, 'rm");
793
+ break;
794
+ default:
795
+ Unknown(instr); // not used by V8
796
+ break;
797
+ }
798
+ } else {
799
+ Unknown(instr); // not used by V8
800
+ }
801
+ } else {
802
+ switch (instr->OpcodeField()) {
803
+ case AND: {
804
+ Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
805
+ break;
806
+ }
807
+ case EOR: {
808
+ Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
809
+ break;
810
+ }
811
+ case SUB: {
812
+ Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
813
+ break;
814
+ }
815
+ case RSB: {
816
+ Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
817
+ break;
818
+ }
819
+ case ADD: {
820
+ Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
821
+ break;
822
+ }
823
+ case ADC: {
824
+ Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
825
+ break;
826
+ }
827
+ case SBC: {
828
+ Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
829
+ break;
830
+ }
831
+ case RSC: {
832
+ Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
833
+ break;
834
+ }
835
+ case TST: {
836
+ if (instr->HasS()) {
837
+ Format(instr, "tst'cond 'rn, 'shift_op");
838
+ } else {
839
+ Format(instr, "movw'cond 'mw");
840
+ }
841
+ break;
842
+ }
843
+ case TEQ: {
844
+ if (instr->HasS()) {
845
+ Format(instr, "teq'cond 'rn, 'shift_op");
846
+ } else {
847
+ // Other instructions matching this pattern are handled in the
848
+ // miscellaneous instructions part above.
849
+ UNREACHABLE();
850
+ }
851
+ break;
852
+ }
853
+ case CMP: {
854
+ if (instr->HasS()) {
855
+ Format(instr, "cmp'cond 'rn, 'shift_op");
856
+ } else {
857
+ Format(instr, "movt'cond 'mw");
858
+ }
859
+ break;
860
+ }
861
+ case CMN: {
862
+ if (instr->HasS()) {
863
+ Format(instr, "cmn'cond 'rn, 'shift_op");
864
+ } else {
865
+ // Other instructions matching this pattern are handled in the
866
+ // miscellaneous instructions part above.
867
+ UNREACHABLE();
868
+ }
869
+ break;
870
+ }
871
+ case ORR: {
872
+ Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
873
+ break;
874
+ }
875
+ case MOV: {
876
+ Format(instr, "mov'cond's 'rd, 'shift_op");
877
+ break;
878
+ }
879
+ case BIC: {
880
+ Format(instr, "bic'cond's 'rd, 'rn, 'shift_op");
881
+ break;
882
+ }
883
+ case MVN: {
884
+ Format(instr, "mvn'cond's 'rd, 'shift_op");
885
+ break;
886
+ }
887
+ default: {
888
+ // The Opcode field is a 4-bit field.
889
+ UNREACHABLE();
890
+ break;
891
+ }
892
+ }
893
+ }
894
+ }
895
+
896
+
897
+ void Decoder::DecodeType2(Instruction* instr) {
898
+ switch (instr->PUField()) {
899
+ case da_x: {
900
+ if (instr->HasW()) {
901
+ Unknown(instr); // not used in V8
902
+ }
903
+ Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
904
+ break;
905
+ }
906
+ case ia_x: {
907
+ if (instr->HasW()) {
908
+ Unknown(instr); // not used in V8
909
+ }
910
+ Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
911
+ break;
912
+ }
913
+ case db_x: {
914
+ Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
915
+ break;
916
+ }
917
+ case ib_x: {
918
+ Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
919
+ break;
920
+ }
921
+ default: {
922
+ // The PU field is a 2-bit field.
923
+ UNREACHABLE();
924
+ break;
925
+ }
926
+ }
927
+ }
928
+
929
+
930
+ void Decoder::DecodeType3(Instruction* instr) {
931
+ switch (instr->PUField()) {
932
+ case da_x: {
933
+ ASSERT(!instr->HasW());
934
+ Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
935
+ break;
936
+ }
937
+ case ia_x: {
938
+ if (instr->HasW()) {
939
+ ASSERT(instr->Bits(5, 4) == 0x1);
940
+ if (instr->Bit(22) == 0x1) {
941
+ Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat");
942
+ } else {
943
+ UNREACHABLE(); // SSAT.
944
+ }
945
+ } else {
946
+ Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
947
+ }
948
+ break;
949
+ }
950
+ case db_x: {
951
+ Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
952
+ break;
953
+ }
954
+ case ib_x: {
955
+ if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
956
+ uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
957
+ uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
958
+ uint32_t msbit = widthminus1 + lsbit;
959
+ if (msbit <= 31) {
960
+ if (instr->Bit(22)) {
961
+ Format(instr, "ubfx'cond 'rd, 'rm, 'f");
962
+ } else {
963
+ Format(instr, "sbfx'cond 'rd, 'rm, 'f");
964
+ }
965
+ } else {
966
+ UNREACHABLE();
967
+ }
968
+ } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
969
+ uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
970
+ uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
971
+ if (msbit >= lsbit) {
972
+ if (instr->RmValue() == 15) {
973
+ Format(instr, "bfc'cond 'rd, 'f");
974
+ } else {
975
+ Format(instr, "bfi'cond 'rd, 'rm, 'f");
976
+ }
977
+ } else {
978
+ UNREACHABLE();
979
+ }
980
+ } else {
981
+ Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
982
+ }
983
+ break;
984
+ }
985
+ default: {
986
+ // The PU field is a 2-bit field.
987
+ UNREACHABLE();
988
+ break;
989
+ }
990
+ }
991
+ }
992
+
993
+
994
+ void Decoder::DecodeType4(Instruction* instr) {
995
+ ASSERT(instr->Bit(22) == 0); // Privileged mode currently not supported.
996
+ if (instr->HasL()) {
997
+ Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
998
+ } else {
999
+ Format(instr, "stm'cond'pu 'rn'w, 'rlist");
1000
+ }
1001
+ }
1002
+
1003
+
1004
+ void Decoder::DecodeType5(Instruction* instr) {
1005
+ Format(instr, "b'l'cond 'target");
1006
+ }
1007
+
1008
+
1009
+ void Decoder::DecodeType6(Instruction* instr) {
1010
+ DecodeType6CoprocessorIns(instr);
1011
+ }
1012
+
1013
+
1014
+ int Decoder::DecodeType7(Instruction* instr) {
1015
+ if (instr->Bit(24) == 1) {
1016
+ if (instr->SvcValue() >= kStopCode) {
1017
+ Format(instr, "stop'cond 'svc");
1018
+ // Also print the stop message. Its address is encoded
1019
+ // in the following 4 bytes.
1020
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
1021
+ "\n %p %08x stop message: %s",
1022
+ reinterpret_cast<int32_t*>(instr
1023
+ + Instruction::kInstrSize),
1024
+ *reinterpret_cast<char**>(instr
1025
+ + Instruction::kInstrSize),
1026
+ *reinterpret_cast<char**>(instr
1027
+ + Instruction::kInstrSize));
1028
+ // We have decoded 2 * Instruction::kInstrSize bytes.
1029
+ return 2 * Instruction::kInstrSize;
1030
+ } else {
1031
+ Format(instr, "svc'cond 'svc");
1032
+ }
1033
+ } else {
1034
+ DecodeTypeVFP(instr);
1035
+ }
1036
+ return Instruction::kInstrSize;
1037
+ }
1038
+
1039
+
1040
+ // void Decoder::DecodeTypeVFP(Instruction* instr)
1041
+ // vmov: Sn = Rt
1042
+ // vmov: Rt = Sn
1043
+ // vcvt: Dd = Sm
1044
+ // vcvt: Sd = Dm
1045
+ // Dd = vadd(Dn, Dm)
1046
+ // Dd = vsub(Dn, Dm)
1047
+ // Dd = vmul(Dn, Dm)
1048
+ // Dd = vdiv(Dn, Dm)
1049
+ // vcmp(Dd, Dm)
1050
+ // vmrs
1051
+ // vmsr
1052
+ // Dd = vsqrt(Dm)
1053
+ void Decoder::DecodeTypeVFP(Instruction* instr) {
1054
+ ASSERT((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
1055
+ ASSERT(instr->Bits(11, 9) == 0x5);
1056
+
1057
+ if (instr->Bit(4) == 0) {
1058
+ if (instr->Opc1Value() == 0x7) {
1059
+ // Other data processing instructions
1060
+ if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
1061
+ // vmov register to register.
1062
+ if (instr->SzValue() == 0x1) {
1063
+ Format(instr, "vmov.f64'cond 'Dd, 'Dm");
1064
+ } else {
1065
+ Format(instr, "vmov.f32'cond 'Sd, 'Sm");
1066
+ }
1067
+ } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) {
1068
+ // vabs
1069
+ Format(instr, "vabs'cond 'Dd, 'Dm");
1070
+ } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
1071
+ DecodeVCVTBetweenDoubleAndSingle(instr);
1072
+ } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
1073
+ DecodeVCVTBetweenFloatingPointAndInteger(instr);
1074
+ } else if (((instr->Opc2Value() >> 1) == 0x6) &&
1075
+ (instr->Opc3Value() & 0x1)) {
1076
+ DecodeVCVTBetweenFloatingPointAndInteger(instr);
1077
+ } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
1078
+ (instr->Opc3Value() & 0x1)) {
1079
+ DecodeVCMP(instr);
1080
+ } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
1081
+ Format(instr, "vsqrt.f64'cond 'Dd, 'Dm");
1082
+ } else if (instr->Opc3Value() == 0x0) {
1083
+ if (instr->SzValue() == 0x1) {
1084
+ Format(instr, "vmov.f64'cond 'Dd, 'd");
1085
+ } else {
1086
+ Unknown(instr); // Not used by V8.
1087
+ }
1088
+ } else {
1089
+ Unknown(instr); // Not used by V8.
1090
+ }
1091
+ } else if (instr->Opc1Value() == 0x3) {
1092
+ if (instr->SzValue() == 0x1) {
1093
+ if (instr->Opc3Value() & 0x1) {
1094
+ Format(instr, "vsub.f64'cond 'Dd, 'Dn, 'Dm");
1095
+ } else {
1096
+ Format(instr, "vadd.f64'cond 'Dd, 'Dn, 'Dm");
1097
+ }
1098
+ } else {
1099
+ Unknown(instr); // Not used by V8.
1100
+ }
1101
+ } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
1102
+ if (instr->SzValue() == 0x1) {
1103
+ Format(instr, "vmul.f64'cond 'Dd, 'Dn, 'Dm");
1104
+ } else {
1105
+ Unknown(instr); // Not used by V8.
1106
+ }
1107
+ } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
1108
+ if (instr->SzValue() == 0x1) {
1109
+ Format(instr, "vdiv.f64'cond 'Dd, 'Dn, 'Dm");
1110
+ } else {
1111
+ Unknown(instr); // Not used by V8.
1112
+ }
1113
+ } else {
1114
+ Unknown(instr); // Not used by V8.
1115
+ }
1116
+ } else {
1117
+ if ((instr->VCValue() == 0x0) &&
1118
+ (instr->VAValue() == 0x0)) {
1119
+ DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
1120
+ } else if ((instr->VCValue() == 0x0) &&
1121
+ (instr->VAValue() == 0x7) &&
1122
+ (instr->Bits(19, 16) == 0x1)) {
1123
+ if (instr->VLValue() == 0) {
1124
+ if (instr->Bits(15, 12) == 0xF) {
1125
+ Format(instr, "vmsr'cond FPSCR, APSR");
1126
+ } else {
1127
+ Format(instr, "vmsr'cond FPSCR, 'rt");
1128
+ }
1129
+ } else {
1130
+ if (instr->Bits(15, 12) == 0xF) {
1131
+ Format(instr, "vmrs'cond APSR, FPSCR");
1132
+ } else {
1133
+ Format(instr, "vmrs'cond 'rt, FPSCR");
1134
+ }
1135
+ }
1136
+ }
1137
+ }
1138
+ }
1139
+
1140
+
1141
+ void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(
1142
+ Instruction* instr) {
1143
+ ASSERT((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
1144
+ (instr->VAValue() == 0x0));
1145
+
1146
+ bool to_arm_register = (instr->VLValue() == 0x1);
1147
+
1148
+ if (to_arm_register) {
1149
+ Format(instr, "vmov'cond 'rt, 'Sn");
1150
+ } else {
1151
+ Format(instr, "vmov'cond 'Sn, 'rt");
1152
+ }
1153
+ }
1154
+
1155
+
1156
+ void Decoder::DecodeVCMP(Instruction* instr) {
1157
+ ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
1158
+ ASSERT(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
1159
+ (instr->Opc3Value() & 0x1));
1160
+
1161
+ // Comparison.
1162
+ bool dp_operation = (instr->SzValue() == 1);
1163
+ bool raise_exception_for_qnan = (instr->Bit(7) == 0x1);
1164
+
1165
+ if (dp_operation && !raise_exception_for_qnan) {
1166
+ if (instr->Opc2Value() == 0x4) {
1167
+ Format(instr, "vcmp.f64'cond 'Dd, 'Dm");
1168
+ } else if (instr->Opc2Value() == 0x5) {
1169
+ Format(instr, "vcmp.f64'cond 'Dd, #0.0");
1170
+ } else {
1171
+ Unknown(instr); // invalid
1172
+ }
1173
+ } else {
1174
+ Unknown(instr); // Not used by V8.
1175
+ }
1176
+ }
1177
+
1178
+
1179
+ void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
1180
+ ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
1181
+ ASSERT((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
1182
+
1183
+ bool double_to_single = (instr->SzValue() == 1);
1184
+
1185
+ if (double_to_single) {
1186
+ Format(instr, "vcvt.f32.f64'cond 'Sd, 'Dm");
1187
+ } else {
1188
+ Format(instr, "vcvt.f64.f32'cond 'Dd, 'Sm");
1189
+ }
1190
+ }
1191
+
1192
+
1193
+ void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
1194
+ ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
1195
+ ASSERT(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
1196
+ (((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
1197
+
1198
+ bool to_integer = (instr->Bit(18) == 1);
1199
+ bool dp_operation = (instr->SzValue() == 1);
1200
+ if (to_integer) {
1201
+ bool unsigned_integer = (instr->Bit(16) == 0);
1202
+
1203
+ if (dp_operation) {
1204
+ if (unsigned_integer) {
1205
+ Format(instr, "vcvt.u32.f64'cond 'Sd, 'Dm");
1206
+ } else {
1207
+ Format(instr, "vcvt.s32.f64'cond 'Sd, 'Dm");
1208
+ }
1209
+ } else {
1210
+ if (unsigned_integer) {
1211
+ Format(instr, "vcvt.u32.f32'cond 'Sd, 'Sm");
1212
+ } else {
1213
+ Format(instr, "vcvt.s32.f32'cond 'Sd, 'Sm");
1214
+ }
1215
+ }
1216
+ } else {
1217
+ bool unsigned_integer = (instr->Bit(7) == 0);
1218
+
1219
+ if (dp_operation) {
1220
+ if (unsigned_integer) {
1221
+ Format(instr, "vcvt.f64.u32'cond 'Dd, 'Sm");
1222
+ } else {
1223
+ Format(instr, "vcvt.f64.s32'cond 'Dd, 'Sm");
1224
+ }
1225
+ } else {
1226
+ if (unsigned_integer) {
1227
+ Format(instr, "vcvt.f32.u32'cond 'Sd, 'Sm");
1228
+ } else {
1229
+ Format(instr, "vcvt.f32.s32'cond 'Sd, 'Sm");
1230
+ }
1231
+ }
1232
+ }
1233
+ }
1234
+
1235
+
1236
+ // Decode Type 6 coprocessor instructions.
1237
+ // Dm = vmov(Rt, Rt2)
1238
+ // <Rt, Rt2> = vmov(Dm)
1239
+ // Ddst = MEM(Rbase + 4*offset).
1240
+ // MEM(Rbase + 4*offset) = Dsrc.
1241
+ void Decoder::DecodeType6CoprocessorIns(Instruction* instr) {
1242
+ ASSERT(instr->TypeValue() == 6);
1243
+
1244
+ if (instr->CoprocessorValue() == 0xA) {
1245
+ switch (instr->OpcodeValue()) {
1246
+ case 0x8:
1247
+ case 0xA:
1248
+ if (instr->HasL()) {
1249
+ Format(instr, "vldr'cond 'Sd, ['rn - 4*'imm08@00]");
1250
+ } else {
1251
+ Format(instr, "vstr'cond 'Sd, ['rn - 4*'imm08@00]");
1252
+ }
1253
+ break;
1254
+ case 0xC:
1255
+ case 0xE:
1256
+ if (instr->HasL()) {
1257
+ Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]");
1258
+ } else {
1259
+ Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]");
1260
+ }
1261
+ break;
1262
+ default:
1263
+ Unknown(instr); // Not used by V8.
1264
+ break;
1265
+ }
1266
+ } else if (instr->CoprocessorValue() == 0xB) {
1267
+ switch (instr->OpcodeValue()) {
1268
+ case 0x2:
1269
+ // Load and store double to two GP registers
1270
+ if (instr->Bits(7, 4) != 0x1) {
1271
+ Unknown(instr); // Not used by V8.
1272
+ } else if (instr->HasL()) {
1273
+ Format(instr, "vmov'cond 'rt, 'rn, 'Dm");
1274
+ } else {
1275
+ Format(instr, "vmov'cond 'Dm, 'rt, 'rn");
1276
+ }
1277
+ break;
1278
+ case 0x8:
1279
+ if (instr->HasL()) {
1280
+ Format(instr, "vldr'cond 'Dd, ['rn - 4*'imm08@00]");
1281
+ } else {
1282
+ Format(instr, "vstr'cond 'Dd, ['rn - 4*'imm08@00]");
1283
+ }
1284
+ break;
1285
+ case 0xC:
1286
+ if (instr->HasL()) {
1287
+ Format(instr, "vldr'cond 'Dd, ['rn + 4*'imm08@00]");
1288
+ } else {
1289
+ Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]");
1290
+ }
1291
+ break;
1292
+ default:
1293
+ Unknown(instr); // Not used by V8.
1294
+ break;
1295
+ }
1296
+ } else {
1297
+ UNIMPLEMENTED(); // Not used by V8.
1298
+ }
1299
+ }
1300
+
1301
+
1302
+ // Disassemble the instruction at *instr_ptr into the output buffer.
1303
+ int Decoder::InstructionDecode(byte* instr_ptr) {
1304
+ Instruction* instr = Instruction::At(instr_ptr);
1305
+ // Print raw instruction bytes.
1306
+ out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
1307
+ "%08x ",
1308
+ instr->InstructionBits());
1309
+ if (instr->ConditionField() == kSpecialCondition) {
1310
+ UNIMPLEMENTED();
1311
+ return Instruction::kInstrSize;
1312
+ }
1313
+ switch (instr->TypeValue()) {
1314
+ case 0:
1315
+ case 1: {
1316
+ DecodeType01(instr);
1317
+ break;
1318
+ }
1319
+ case 2: {
1320
+ DecodeType2(instr);
1321
+ break;
1322
+ }
1323
+ case 3: {
1324
+ DecodeType3(instr);
1325
+ break;
1326
+ }
1327
+ case 4: {
1328
+ DecodeType4(instr);
1329
+ break;
1330
+ }
1331
+ case 5: {
1332
+ DecodeType5(instr);
1333
+ break;
1334
+ }
1335
+ case 6: {
1336
+ DecodeType6(instr);
1337
+ break;
1338
+ }
1339
+ case 7: {
1340
+ return DecodeType7(instr);
1341
+ }
1342
+ default: {
1343
+ // The type field is 3-bits in the ARM encoding.
1344
+ UNREACHABLE();
1345
+ break;
1346
+ }
1347
+ }
1348
+ return Instruction::kInstrSize;
1349
+ }
1350
+
1351
+
1352
+ } } // namespace v8::internal
1353
+
1354
+
1355
+
1356
+ //------------------------------------------------------------------------------
1357
+
1358
+ namespace disasm {
1359
+
1360
+
1361
+ const char* NameConverter::NameOfAddress(byte* addr) const {
1362
+ static v8::internal::EmbeddedVector<char, 32> tmp_buffer;
1363
+ v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr);
1364
+ return tmp_buffer.start();
1365
+ }
1366
+
1367
+
1368
+ const char* NameConverter::NameOfConstant(byte* addr) const {
1369
+ return NameOfAddress(addr);
1370
+ }
1371
+
1372
+
1373
+ const char* NameConverter::NameOfCPURegister(int reg) const {
1374
+ return v8::internal::Registers::Name(reg);
1375
+ }
1376
+
1377
+
1378
+ const char* NameConverter::NameOfByteCPURegister(int reg) const {
1379
+ UNREACHABLE(); // ARM does not have the concept of a byte register
1380
+ return "nobytereg";
1381
+ }
1382
+
1383
+
1384
+ const char* NameConverter::NameOfXMMRegister(int reg) const {
1385
+ UNREACHABLE(); // ARM does not have any XMM registers
1386
+ return "noxmmreg";
1387
+ }
1388
+
1389
+
1390
+ const char* NameConverter::NameInCode(byte* addr) const {
1391
+ // The default name converter is called for unknown code. So we will not try
1392
+ // to access any memory.
1393
+ return "";
1394
+ }
1395
+
1396
+
1397
+ //------------------------------------------------------------------------------
1398
+
1399
+ Disassembler::Disassembler(const NameConverter& converter)
1400
+ : converter_(converter) {}
1401
+
1402
+
1403
+ Disassembler::~Disassembler() {}
1404
+
1405
+
1406
+ int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
1407
+ byte* instruction) {
1408
+ v8::internal::Decoder d(converter_, buffer);
1409
+ return d.InstructionDecode(instruction);
1410
+ }
1411
+
1412
+
1413
+ int Disassembler::ConstantPoolSizeAt(byte* instruction) {
1414
+ int instruction_bits = *(reinterpret_cast<int*>(instruction));
1415
+ if ((instruction_bits & 0xfff00000) == 0x03000000) {
1416
+ return instruction_bits & 0x0000ffff;
1417
+ } else {
1418
+ return -1;
1419
+ }
1420
+ }
1421
+
1422
+
1423
+ void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
1424
+ NameConverter converter;
1425
+ Disassembler d(converter);
1426
+ for (byte* pc = begin; pc < end;) {
1427
+ v8::internal::EmbeddedVector<char, 128> buffer;
1428
+ buffer[0] = '\0';
1429
+ byte* prev_pc = pc;
1430
+ pc += d.InstructionDecode(buffer, pc);
1431
+ fprintf(f, "%p %08x %s\n",
1432
+ prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1433
+ }
1434
+ }
1435
+
1436
+
1437
+ } // namespace disasm
1438
+
1439
+ #endif // V8_TARGET_ARCH_ARM