therubyracer 0.8.1.pre2 → 0.8.1

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Files changed (877) hide show
  1. data/Changelog.md +2 -1
  2. data/README.md +6 -3
  3. data/ext/v8/upstream/3.1.8/.gitignore +31 -0
  4. data/ext/v8/upstream/3.1.8/AUTHORS +40 -0
  5. data/ext/v8/upstream/3.1.8/ChangeLog +2566 -0
  6. data/ext/v8/upstream/3.1.8/LICENSE +52 -0
  7. data/ext/v8/upstream/3.1.8/LICENSE.strongtalk +29 -0
  8. data/ext/v8/upstream/3.1.8/LICENSE.v8 +26 -0
  9. data/ext/v8/upstream/3.1.8/LICENSE.valgrind +45 -0
  10. data/ext/v8/upstream/3.1.8/SConstruct +1192 -0
  11. data/ext/v8/upstream/3.1.8/build/README.txt +25 -0
  12. data/ext/v8/upstream/3.1.8/build/all.gyp +18 -0
  13. data/ext/v8/upstream/3.1.8/build/armu.gypi +32 -0
  14. data/ext/v8/upstream/3.1.8/build/common.gypi +82 -0
  15. data/ext/v8/upstream/3.1.8/build/gyp_v8 +145 -0
  16. data/ext/v8/upstream/3.1.8/include/v8-debug.h +384 -0
  17. data/ext/v8/upstream/3.1.8/include/v8-preparser.h +116 -0
  18. data/ext/v8/upstream/3.1.8/include/v8-profiler.h +426 -0
  19. data/ext/v8/upstream/3.1.8/include/v8-testing.h +99 -0
  20. data/ext/v8/upstream/3.1.8/include/v8.h +3846 -0
  21. data/ext/v8/upstream/3.1.8/include/v8stdint.h +53 -0
  22. data/ext/v8/upstream/3.1.8/preparser/preparser-process.cc +206 -0
  23. data/ext/v8/upstream/3.1.8/src/SConscript +356 -0
  24. data/ext/v8/upstream/3.1.8/src/accessors.cc +907 -0
  25. data/ext/v8/upstream/3.1.8/src/accessors.h +121 -0
  26. data/ext/v8/upstream/3.1.8/src/allocation.cc +204 -0
  27. data/ext/v8/upstream/3.1.8/src/allocation.h +176 -0
  28. data/ext/v8/upstream/3.1.8/src/api.cc +5191 -0
  29. data/ext/v8/upstream/3.1.8/src/api.h +508 -0
  30. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/apinatives.js +0 -0
  31. data/ext/v8/upstream/3.1.8/src/apiutils.h +80 -0
  32. data/ext/v8/upstream/3.1.8/src/arguments.h +105 -0
  33. data/ext/v8/upstream/3.1.8/src/arm/assembler-arm-inl.h +352 -0
  34. data/ext/v8/upstream/3.1.8/src/arm/assembler-arm.cc +2756 -0
  35. data/ext/v8/upstream/3.1.8/src/arm/assembler-arm.h +1294 -0
  36. data/ext/v8/upstream/3.1.8/src/arm/builtins-arm.cc +1628 -0
  37. data/ext/v8/upstream/3.1.8/src/arm/code-stubs-arm.cc +6783 -0
  38. data/ext/v8/upstream/3.1.8/src/arm/code-stubs-arm.h +657 -0
  39. data/ext/v8/upstream/3.1.8/src/arm/codegen-arm-inl.h +48 -0
  40. data/ext/v8/upstream/3.1.8/src/arm/codegen-arm.cc +7403 -0
  41. data/ext/v8/upstream/3.1.8/src/arm/codegen-arm.h +595 -0
  42. data/ext/v8/upstream/3.1.8/src/arm/constants-arm.cc +152 -0
  43. data/ext/v8/upstream/3.1.8/src/arm/constants-arm.h +769 -0
  44. data/ext/v8/upstream/3.1.8/src/arm/cpu-arm.cc +147 -0
  45. data/ext/v8/upstream/3.1.8/src/arm/debug-arm.cc +315 -0
  46. data/ext/v8/upstream/3.1.8/src/arm/deoptimizer-arm.cc +700 -0
  47. data/ext/v8/upstream/3.1.8/src/arm/disasm-arm.cc +1439 -0
  48. data/ext/v8/upstream/3.1.8/src/arm/frames-arm.cc +45 -0
  49. data/ext/v8/upstream/3.1.8/src/arm/frames-arm.h +168 -0
  50. data/ext/v8/upstream/3.1.8/src/arm/full-codegen-arm.cc +4230 -0
  51. data/ext/v8/upstream/3.1.8/src/arm/ic-arm.cc +1799 -0
  52. data/ext/v8/upstream/3.1.8/src/arm/jump-target-arm.cc +174 -0
  53. data/ext/v8/upstream/3.1.8/src/arm/lithium-arm.cc +2041 -0
  54. data/ext/v8/upstream/3.1.8/src/arm/lithium-arm.h +2046 -0
  55. data/ext/v8/upstream/3.1.8/src/arm/lithium-codegen-arm.cc +3822 -0
  56. data/ext/v8/upstream/3.1.8/src/arm/lithium-codegen-arm.h +312 -0
  57. data/ext/v8/upstream/3.1.8/src/arm/lithium-gap-resolver-arm.cc +303 -0
  58. data/ext/v8/upstream/3.1.8/src/arm/lithium-gap-resolver-arm.h +84 -0
  59. data/ext/v8/upstream/3.1.8/src/arm/macro-assembler-arm.cc +2701 -0
  60. data/ext/v8/upstream/3.1.8/src/arm/macro-assembler-arm.h +1015 -0
  61. data/ext/v8/upstream/3.1.8/src/arm/regexp-macro-assembler-arm.cc +1280 -0
  62. data/ext/v8/upstream/3.1.8/src/arm/regexp-macro-assembler-arm.h +252 -0
  63. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/register-allocator-arm-inl.h +0 -0
  64. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/register-allocator-arm.cc +0 -0
  65. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/register-allocator-arm.h +0 -0
  66. data/ext/v8/upstream/3.1.8/src/arm/simulator-arm.cc +3165 -0
  67. data/ext/v8/upstream/3.1.8/src/arm/simulator-arm.h +402 -0
  68. data/ext/v8/upstream/3.1.8/src/arm/stub-cache-arm.cc +4077 -0
  69. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/arm/virtual-frame-arm-inl.h +0 -0
  70. data/ext/v8/upstream/3.1.8/src/arm/virtual-frame-arm.cc +843 -0
  71. data/ext/v8/upstream/3.1.8/src/arm/virtual-frame-arm.h +520 -0
  72. data/ext/v8/upstream/3.1.8/src/array.js +1231 -0
  73. data/ext/v8/upstream/3.1.8/src/assembler.cc +973 -0
  74. data/ext/v8/upstream/3.1.8/src/assembler.h +787 -0
  75. data/ext/v8/upstream/3.1.8/src/ast-inl.h +107 -0
  76. data/ext/v8/upstream/3.1.8/src/ast.cc +1067 -0
  77. data/ext/v8/upstream/3.1.8/src/ast.h +2177 -0
  78. data/ext/v8/upstream/3.1.8/src/atomicops.h +165 -0
  79. data/ext/v8/upstream/3.1.8/src/atomicops_internals_arm_gcc.h +145 -0
  80. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_gcc.cc +126 -0
  81. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_gcc.h +287 -0
  82. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_macosx.h +301 -0
  83. data/ext/v8/upstream/3.1.8/src/atomicops_internals_x86_msvc.h +203 -0
  84. data/ext/v8/upstream/3.1.8/src/bignum-dtoa.cc +655 -0
  85. data/ext/v8/upstream/3.1.8/src/bignum-dtoa.h +81 -0
  86. data/ext/v8/upstream/3.1.8/src/bignum.cc +768 -0
  87. data/ext/v8/upstream/3.1.8/src/bignum.h +140 -0
  88. data/ext/v8/upstream/3.1.8/src/bootstrapper.cc +1888 -0
  89. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/bootstrapper.h +0 -0
  90. data/ext/v8/upstream/3.1.8/src/builtins.cc +1586 -0
  91. data/ext/v8/upstream/3.1.8/src/builtins.h +339 -0
  92. data/ext/v8/upstream/3.1.8/src/bytecodes-irregexp.h +105 -0
  93. data/ext/v8/upstream/3.1.8/src/cached-powers.cc +177 -0
  94. data/ext/v8/upstream/3.1.8/src/cached-powers.h +65 -0
  95. data/ext/v8/upstream/3.1.8/src/char-predicates-inl.h +94 -0
  96. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/char-predicates.h +0 -0
  97. data/ext/v8/upstream/3.1.8/src/checks.cc +110 -0
  98. data/ext/v8/upstream/3.1.8/src/checks.h +292 -0
  99. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/circular-queue-inl.h +0 -0
  100. data/ext/v8/upstream/3.1.8/src/circular-queue.cc +122 -0
  101. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/circular-queue.h +0 -0
  102. data/ext/v8/upstream/3.1.8/src/code-stubs.cc +230 -0
  103. data/ext/v8/upstream/3.1.8/src/code-stubs.h +950 -0
  104. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/code.h +0 -0
  105. data/ext/v8/upstream/3.1.8/src/codegen-inl.h +64 -0
  106. data/ext/v8/upstream/3.1.8/src/codegen.cc +495 -0
  107. data/ext/v8/upstream/3.1.8/src/codegen.h +245 -0
  108. data/ext/v8/upstream/3.1.8/src/compilation-cache.cc +654 -0
  109. data/ext/v8/upstream/3.1.8/src/compilation-cache.h +112 -0
  110. data/ext/v8/upstream/3.1.8/src/compiler.cc +806 -0
  111. data/ext/v8/upstream/3.1.8/src/compiler.h +290 -0
  112. data/ext/v8/upstream/3.1.8/src/contexts.cc +320 -0
  113. data/ext/v8/upstream/3.1.8/src/contexts.h +376 -0
  114. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/conversions-inl.h +0 -0
  115. data/ext/v8/upstream/3.1.8/src/conversions.cc +1069 -0
  116. data/ext/v8/upstream/3.1.8/src/conversions.h +122 -0
  117. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/counters.cc +0 -0
  118. data/ext/v8/upstream/3.1.8/src/counters.h +242 -0
  119. data/ext/v8/upstream/3.1.8/src/cpu-profiler-inl.h +100 -0
  120. data/ext/v8/upstream/3.1.8/src/cpu-profiler.cc +554 -0
  121. data/ext/v8/upstream/3.1.8/src/cpu-profiler.h +291 -0
  122. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/cpu.h +0 -0
  123. data/ext/v8/upstream/3.1.8/src/d8-debug.cc +367 -0
  124. data/ext/v8/upstream/3.1.8/src/d8-debug.h +157 -0
  125. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/d8-posix.cc +0 -0
  126. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/d8-readline.cc +0 -0
  127. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/d8-windows.cc +0 -0
  128. data/ext/v8/upstream/3.1.8/src/d8.cc +792 -0
  129. data/ext/v8/upstream/3.1.8/src/d8.gyp +85 -0
  130. data/ext/v8/upstream/3.1.8/src/d8.h +231 -0
  131. data/ext/v8/upstream/3.1.8/src/d8.js +2798 -0
  132. data/ext/v8/upstream/3.1.8/src/data-flow.cc +545 -0
  133. data/ext/v8/upstream/3.1.8/src/data-flow.h +379 -0
  134. data/ext/v8/upstream/3.1.8/src/date.js +1103 -0
  135. data/ext/v8/upstream/3.1.8/src/dateparser-inl.h +125 -0
  136. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/dateparser.cc +0 -0
  137. data/ext/v8/upstream/3.1.8/src/dateparser.h +263 -0
  138. data/ext/v8/upstream/3.1.8/src/debug-agent.cc +446 -0
  139. data/ext/v8/upstream/3.1.8/src/debug-agent.h +131 -0
  140. data/ext/v8/upstream/3.1.8/src/debug-debugger.js +2569 -0
  141. data/ext/v8/upstream/3.1.8/src/debug.cc +3085 -0
  142. data/ext/v8/upstream/3.1.8/src/debug.h +1025 -0
  143. data/ext/v8/upstream/3.1.8/src/deoptimizer.cc +1185 -0
  144. data/ext/v8/upstream/3.1.8/src/deoptimizer.h +529 -0
  145. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/disasm.h +0 -0
  146. data/ext/v8/upstream/3.1.8/src/disassembler.cc +338 -0
  147. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/disassembler.h +0 -0
  148. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/diy-fp.cc +0 -0
  149. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/diy-fp.h +0 -0
  150. data/ext/v8/upstream/3.1.8/src/double.h +238 -0
  151. data/ext/v8/upstream/3.1.8/src/dtoa.cc +103 -0
  152. data/ext/v8/upstream/3.1.8/src/dtoa.h +85 -0
  153. data/ext/v8/upstream/3.1.8/src/execution.cc +735 -0
  154. data/ext/v8/upstream/3.1.8/src/execution.h +322 -0
  155. data/ext/v8/upstream/3.1.8/src/extensions/experimental/experimental.gyp +53 -0
  156. data/ext/v8/upstream/3.1.8/src/extensions/experimental/i18n-extension.cc +264 -0
  157. data/ext/v8/upstream/3.1.8/src/extensions/experimental/i18n-extension.h +64 -0
  158. data/ext/v8/upstream/3.1.8/src/extensions/externalize-string-extension.cc +141 -0
  159. data/ext/v8/upstream/3.1.8/src/extensions/externalize-string-extension.h +50 -0
  160. data/ext/v8/upstream/3.1.8/src/extensions/gc-extension.cc +58 -0
  161. data/ext/v8/upstream/3.1.8/src/extensions/gc-extension.h +49 -0
  162. data/ext/v8/upstream/3.1.8/src/factory.cc +1087 -0
  163. data/ext/v8/upstream/3.1.8/src/factory.h +432 -0
  164. data/ext/v8/upstream/3.1.8/src/fast-dtoa.cc +736 -0
  165. data/ext/v8/upstream/3.1.8/src/fast-dtoa.h +83 -0
  166. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/fixed-dtoa.cc +0 -0
  167. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/fixed-dtoa.h +0 -0
  168. data/ext/v8/upstream/3.1.8/src/flag-definitions.h +552 -0
  169. data/ext/v8/upstream/3.1.8/src/flags.cc +551 -0
  170. data/ext/v8/upstream/3.1.8/src/flags.h +79 -0
  171. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/frame-element.cc +0 -0
  172. data/ext/v8/upstream/3.1.8/src/frame-element.h +277 -0
  173. data/ext/v8/upstream/3.1.8/src/frames-inl.h +210 -0
  174. data/ext/v8/upstream/3.1.8/src/frames.cc +1232 -0
  175. data/ext/v8/upstream/3.1.8/src/frames.h +826 -0
  176. data/ext/v8/upstream/3.1.8/src/full-codegen.cc +1382 -0
  177. data/ext/v8/upstream/3.1.8/src/full-codegen.h +751 -0
  178. data/ext/v8/upstream/3.1.8/src/func-name-inferrer.cc +90 -0
  179. data/ext/v8/upstream/3.1.8/src/func-name-inferrer.h +111 -0
  180. data/ext/v8/upstream/3.1.8/src/gdb-jit.cc +1547 -0
  181. data/ext/v8/upstream/3.1.8/src/gdb-jit.h +138 -0
  182. data/ext/v8/upstream/3.1.8/src/global-handles.cc +534 -0
  183. data/ext/v8/upstream/3.1.8/src/global-handles.h +181 -0
  184. data/ext/v8/upstream/3.1.8/src/globals.h +325 -0
  185. data/ext/v8/upstream/3.1.8/src/handles-inl.h +80 -0
  186. data/ext/v8/upstream/3.1.8/src/handles.cc +910 -0
  187. data/ext/v8/upstream/3.1.8/src/handles.h +424 -0
  188. data/ext/v8/upstream/3.1.8/src/hashmap.cc +230 -0
  189. data/ext/v8/upstream/3.1.8/src/hashmap.h +121 -0
  190. data/ext/v8/upstream/3.1.8/src/heap-inl.h +587 -0
  191. data/ext/v8/upstream/3.1.8/src/heap-profiler.cc +1128 -0
  192. data/ext/v8/upstream/3.1.8/src/heap-profiler.h +381 -0
  193. data/ext/v8/upstream/3.1.8/src/heap.cc +5610 -0
  194. data/ext/v8/upstream/3.1.8/src/heap.h +2218 -0
  195. data/ext/v8/upstream/3.1.8/src/hydrogen-instructions.cc +1490 -0
  196. data/ext/v8/upstream/3.1.8/src/hydrogen-instructions.h +3493 -0
  197. data/ext/v8/upstream/3.1.8/src/hydrogen.cc +6056 -0
  198. data/ext/v8/upstream/3.1.8/src/hydrogen.h +1091 -0
  199. data/ext/v8/upstream/3.1.8/src/ia32/assembler-ia32-inl.h +429 -0
  200. data/ext/v8/upstream/3.1.8/src/ia32/assembler-ia32.cc +2800 -0
  201. data/ext/v8/upstream/3.1.8/src/ia32/assembler-ia32.h +1093 -0
  202. data/ext/v8/upstream/3.1.8/src/ia32/builtins-ia32.cc +1590 -0
  203. data/ext/v8/upstream/3.1.8/src/ia32/code-stubs-ia32.cc +6624 -0
  204. data/ext/v8/upstream/3.1.8/src/ia32/code-stubs-ia32.h +536 -0
  205. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/codegen-ia32-inl.h +0 -0
  206. data/ext/v8/upstream/3.1.8/src/ia32/codegen-ia32.cc +10354 -0
  207. data/ext/v8/upstream/3.1.8/src/ia32/codegen-ia32.h +798 -0
  208. data/ext/v8/upstream/3.1.8/src/ia32/cpu-ia32.cc +87 -0
  209. data/ext/v8/upstream/3.1.8/src/ia32/debug-ia32.cc +309 -0
  210. data/ext/v8/upstream/3.1.8/src/ia32/deoptimizer-ia32.cc +664 -0
  211. data/ext/v8/upstream/3.1.8/src/ia32/disasm-ia32.cc +1597 -0
  212. data/ext/v8/upstream/3.1.8/src/ia32/frames-ia32.cc +45 -0
  213. data/ext/v8/upstream/3.1.8/src/ia32/frames-ia32.h +140 -0
  214. data/ext/v8/upstream/3.1.8/src/ia32/full-codegen-ia32.cc +4278 -0
  215. data/ext/v8/upstream/3.1.8/src/ia32/ic-ia32.cc +1786 -0
  216. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/jump-target-ia32.cc +0 -0
  217. data/ext/v8/upstream/3.1.8/src/ia32/lithium-codegen-ia32.cc +3880 -0
  218. data/ext/v8/upstream/3.1.8/src/ia32/lithium-codegen-ia32.h +309 -0
  219. data/ext/v8/upstream/3.1.8/src/ia32/lithium-gap-resolver-ia32.cc +460 -0
  220. data/ext/v8/upstream/3.1.8/src/ia32/lithium-gap-resolver-ia32.h +110 -0
  221. data/ext/v8/upstream/3.1.8/src/ia32/lithium-ia32.cc +2095 -0
  222. data/ext/v8/upstream/3.1.8/src/ia32/lithium-ia32.h +2127 -0
  223. data/ext/v8/upstream/3.1.8/src/ia32/macro-assembler-ia32.cc +2031 -0
  224. data/ext/v8/upstream/3.1.8/src/ia32/macro-assembler-ia32.h +798 -0
  225. data/ext/v8/upstream/3.1.8/src/ia32/regexp-macro-assembler-ia32.cc +1253 -0
  226. data/ext/v8/upstream/3.1.8/src/ia32/regexp-macro-assembler-ia32.h +215 -0
  227. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/register-allocator-ia32-inl.h +0 -0
  228. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/register-allocator-ia32.cc +0 -0
  229. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/register-allocator-ia32.h +0 -0
  230. data/ext/v8/upstream/{2.3.3 → 3.1.8}/src/ia32/simulator-ia32.cc +0 -0
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  232. data/ext/v8/upstream/3.1.8/src/ia32/stub-cache-ia32.cc +3732 -0
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  689. data/ext/v8/upstream/2.3.3/src/ia32/ic-ia32.cc +0 -1966
  690. data/ext/v8/upstream/2.3.3/src/ia32/macro-assembler-ia32.cc +0 -1610
  691. data/ext/v8/upstream/2.3.3/src/ia32/macro-assembler-ia32.h +0 -610
  692. data/ext/v8/upstream/2.3.3/src/ia32/regexp-macro-assembler-ia32.cc +0 -1247
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  694. data/ext/v8/upstream/2.3.3/src/ia32/simulator-ia32.h +0 -62
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  697. data/ext/v8/upstream/2.3.3/src/ia32/virtual-frame-ia32.h +0 -627
  698. data/ext/v8/upstream/2.3.3/src/ic-inl.h +0 -120
  699. data/ext/v8/upstream/2.3.3/src/ic.cc +0 -1827
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  736. data/ext/v8/upstream/2.3.3/src/mirror-debugger.js +0 -2380
  737. data/ext/v8/upstream/2.3.3/src/objects-debug.cc +0 -1366
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@@ -0,0 +1,1597 @@
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+ // Copyright 2007-2008 the V8 project authors. All rights reserved.
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+ // Redistribution and use in source and binary forms, with or without
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+ // modification, are permitted provided that the following conditions are
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+ // met:
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+ //
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+ // * Redistributions of source code must retain the above copyright
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+ // notice, this list of conditions and the following disclaimer.
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+ // * Redistributions in binary form must reproduce the above
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+ // copyright notice, this list of conditions and the following
10
+ // disclaimer in the documentation and/or other materials provided
11
+ // with the distribution.
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+ // * Neither the name of Google Inc. nor the names of its
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+ // contributors may be used to endorse or promote products derived
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+ // from this software without specific prior written permission.
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+ //
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+ // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
+ // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
+ // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+
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+ #include <assert.h>
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+ #include <stdio.h>
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+ #include <stdarg.h>
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+
32
+ #include "v8.h"
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+
34
+ #if defined(V8_TARGET_ARCH_IA32)
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+
36
+ #include "disasm.h"
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+
38
+ namespace disasm {
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+
40
+ enum OperandOrder {
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+ UNSET_OP_ORDER = 0,
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+ REG_OPER_OP_ORDER,
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+ OPER_REG_OP_ORDER
44
+ };
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+
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+
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+ //------------------------------------------------------------------
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+ // Tables
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+ //------------------------------------------------------------------
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+ struct ByteMnemonic {
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+ int b; // -1 terminates, otherwise must be in range (0..255)
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+ const char* mnem;
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+ OperandOrder op_order_;
54
+ };
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+
56
+
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+ static ByteMnemonic two_operands_instr[] = {
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+ {0x03, "add", REG_OPER_OP_ORDER},
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+ {0x09, "or", OPER_REG_OP_ORDER},
60
+ {0x0B, "or", REG_OPER_OP_ORDER},
61
+ {0x1B, "sbb", REG_OPER_OP_ORDER},
62
+ {0x21, "and", OPER_REG_OP_ORDER},
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+ {0x23, "and", REG_OPER_OP_ORDER},
64
+ {0x29, "sub", OPER_REG_OP_ORDER},
65
+ {0x2A, "subb", REG_OPER_OP_ORDER},
66
+ {0x2B, "sub", REG_OPER_OP_ORDER},
67
+ {0x31, "xor", OPER_REG_OP_ORDER},
68
+ {0x33, "xor", REG_OPER_OP_ORDER},
69
+ {0x38, "cmpb", OPER_REG_OP_ORDER},
70
+ {0x3A, "cmpb", REG_OPER_OP_ORDER},
71
+ {0x3B, "cmp", REG_OPER_OP_ORDER},
72
+ {0x84, "test_b", REG_OPER_OP_ORDER},
73
+ {0x85, "test", REG_OPER_OP_ORDER},
74
+ {0x87, "xchg", REG_OPER_OP_ORDER},
75
+ {0x8A, "mov_b", REG_OPER_OP_ORDER},
76
+ {0x8B, "mov", REG_OPER_OP_ORDER},
77
+ {0x8D, "lea", REG_OPER_OP_ORDER},
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+ {-1, "", UNSET_OP_ORDER}
79
+ };
80
+
81
+
82
+ static ByteMnemonic zero_operands_instr[] = {
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+ {0xC3, "ret", UNSET_OP_ORDER},
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+ {0xC9, "leave", UNSET_OP_ORDER},
85
+ {0x90, "nop", UNSET_OP_ORDER},
86
+ {0xF4, "hlt", UNSET_OP_ORDER},
87
+ {0xCC, "int3", UNSET_OP_ORDER},
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+ {0x60, "pushad", UNSET_OP_ORDER},
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+ {0x61, "popad", UNSET_OP_ORDER},
90
+ {0x9C, "pushfd", UNSET_OP_ORDER},
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+ {0x9D, "popfd", UNSET_OP_ORDER},
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+ {0x9E, "sahf", UNSET_OP_ORDER},
93
+ {0x99, "cdq", UNSET_OP_ORDER},
94
+ {0x9B, "fwait", UNSET_OP_ORDER},
95
+ {0xFC, "cld", UNSET_OP_ORDER},
96
+ {0xAB, "stos", UNSET_OP_ORDER},
97
+ {-1, "", UNSET_OP_ORDER}
98
+ };
99
+
100
+
101
+ static ByteMnemonic call_jump_instr[] = {
102
+ {0xE8, "call", UNSET_OP_ORDER},
103
+ {0xE9, "jmp", UNSET_OP_ORDER},
104
+ {-1, "", UNSET_OP_ORDER}
105
+ };
106
+
107
+
108
+ static ByteMnemonic short_immediate_instr[] = {
109
+ {0x05, "add", UNSET_OP_ORDER},
110
+ {0x0D, "or", UNSET_OP_ORDER},
111
+ {0x15, "adc", UNSET_OP_ORDER},
112
+ {0x25, "and", UNSET_OP_ORDER},
113
+ {0x2D, "sub", UNSET_OP_ORDER},
114
+ {0x35, "xor", UNSET_OP_ORDER},
115
+ {0x3D, "cmp", UNSET_OP_ORDER},
116
+ {-1, "", UNSET_OP_ORDER}
117
+ };
118
+
119
+
120
+ static const char* jump_conditional_mnem[] = {
121
+ /*0*/ "jo", "jno", "jc", "jnc",
122
+ /*4*/ "jz", "jnz", "jna", "ja",
123
+ /*8*/ "js", "jns", "jpe", "jpo",
124
+ /*12*/ "jl", "jnl", "jng", "jg"
125
+ };
126
+
127
+
128
+ static const char* set_conditional_mnem[] = {
129
+ /*0*/ "seto", "setno", "setc", "setnc",
130
+ /*4*/ "setz", "setnz", "setna", "seta",
131
+ /*8*/ "sets", "setns", "setpe", "setpo",
132
+ /*12*/ "setl", "setnl", "setng", "setg"
133
+ };
134
+
135
+
136
+ static const char* conditional_move_mnem[] = {
137
+ /*0*/ "cmovo", "cmovno", "cmovc", "cmovnc",
138
+ /*4*/ "cmovz", "cmovnz", "cmovna", "cmova",
139
+ /*8*/ "cmovs", "cmovns", "cmovpe", "cmovpo",
140
+ /*12*/ "cmovl", "cmovnl", "cmovng", "cmovg"
141
+ };
142
+
143
+
144
+ enum InstructionType {
145
+ NO_INSTR,
146
+ ZERO_OPERANDS_INSTR,
147
+ TWO_OPERANDS_INSTR,
148
+ JUMP_CONDITIONAL_SHORT_INSTR,
149
+ REGISTER_INSTR,
150
+ MOVE_REG_INSTR,
151
+ CALL_JUMP_INSTR,
152
+ SHORT_IMMEDIATE_INSTR
153
+ };
154
+
155
+
156
+ struct InstructionDesc {
157
+ const char* mnem;
158
+ InstructionType type;
159
+ OperandOrder op_order_;
160
+ };
161
+
162
+
163
+ class InstructionTable {
164
+ public:
165
+ InstructionTable();
166
+ const InstructionDesc& Get(byte x) const { return instructions_[x]; }
167
+
168
+ private:
169
+ InstructionDesc instructions_[256];
170
+ void Clear();
171
+ void Init();
172
+ void CopyTable(ByteMnemonic bm[], InstructionType type);
173
+ void SetTableRange(InstructionType type,
174
+ byte start,
175
+ byte end,
176
+ const char* mnem);
177
+ void AddJumpConditionalShort();
178
+ };
179
+
180
+
181
+ InstructionTable::InstructionTable() {
182
+ Clear();
183
+ Init();
184
+ }
185
+
186
+
187
+ void InstructionTable::Clear() {
188
+ for (int i = 0; i < 256; i++) {
189
+ instructions_[i].mnem = "";
190
+ instructions_[i].type = NO_INSTR;
191
+ instructions_[i].op_order_ = UNSET_OP_ORDER;
192
+ }
193
+ }
194
+
195
+
196
+ void InstructionTable::Init() {
197
+ CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
198
+ CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
199
+ CopyTable(call_jump_instr, CALL_JUMP_INSTR);
200
+ CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
201
+ AddJumpConditionalShort();
202
+ SetTableRange(REGISTER_INSTR, 0x40, 0x47, "inc");
203
+ SetTableRange(REGISTER_INSTR, 0x48, 0x4F, "dec");
204
+ SetTableRange(REGISTER_INSTR, 0x50, 0x57, "push");
205
+ SetTableRange(REGISTER_INSTR, 0x58, 0x5F, "pop");
206
+ SetTableRange(REGISTER_INSTR, 0x91, 0x97, "xchg eax,"); // 0x90 is nop.
207
+ SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, "mov");
208
+ }
209
+
210
+
211
+ void InstructionTable::CopyTable(ByteMnemonic bm[], InstructionType type) {
212
+ for (int i = 0; bm[i].b >= 0; i++) {
213
+ InstructionDesc* id = &instructions_[bm[i].b];
214
+ id->mnem = bm[i].mnem;
215
+ id->op_order_ = bm[i].op_order_;
216
+ ASSERT_EQ(NO_INSTR, id->type); // Information not already entered.
217
+ id->type = type;
218
+ }
219
+ }
220
+
221
+
222
+ void InstructionTable::SetTableRange(InstructionType type,
223
+ byte start,
224
+ byte end,
225
+ const char* mnem) {
226
+ for (byte b = start; b <= end; b++) {
227
+ InstructionDesc* id = &instructions_[b];
228
+ ASSERT_EQ(NO_INSTR, id->type); // Information not already entered.
229
+ id->mnem = mnem;
230
+ id->type = type;
231
+ }
232
+ }
233
+
234
+
235
+ void InstructionTable::AddJumpConditionalShort() {
236
+ for (byte b = 0x70; b <= 0x7F; b++) {
237
+ InstructionDesc* id = &instructions_[b];
238
+ ASSERT_EQ(NO_INSTR, id->type); // Information not already entered.
239
+ id->mnem = jump_conditional_mnem[b & 0x0F];
240
+ id->type = JUMP_CONDITIONAL_SHORT_INSTR;
241
+ }
242
+ }
243
+
244
+
245
+ static InstructionTable instruction_table;
246
+
247
+
248
+ // The IA32 disassembler implementation.
249
+ class DisassemblerIA32 {
250
+ public:
251
+ DisassemblerIA32(const NameConverter& converter,
252
+ bool abort_on_unimplemented = true)
253
+ : converter_(converter),
254
+ tmp_buffer_pos_(0),
255
+ abort_on_unimplemented_(abort_on_unimplemented) {
256
+ tmp_buffer_[0] = '\0';
257
+ }
258
+
259
+ virtual ~DisassemblerIA32() {}
260
+
261
+ // Writes one disassembled instruction into 'buffer' (0-terminated).
262
+ // Returns the length of the disassembled machine instruction in bytes.
263
+ int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
264
+
265
+ private:
266
+ const NameConverter& converter_;
267
+ v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
268
+ unsigned int tmp_buffer_pos_;
269
+ bool abort_on_unimplemented_;
270
+
271
+
272
+ enum {
273
+ eax = 0,
274
+ ecx = 1,
275
+ edx = 2,
276
+ ebx = 3,
277
+ esp = 4,
278
+ ebp = 5,
279
+ esi = 6,
280
+ edi = 7
281
+ };
282
+
283
+
284
+ enum ShiftOpcodeExtension {
285
+ kROL = 0,
286
+ kROR = 1,
287
+ kRCL = 2,
288
+ kRCR = 3,
289
+ kSHL = 4,
290
+ KSHR = 5,
291
+ kSAR = 7
292
+ };
293
+
294
+
295
+ const char* NameOfCPURegister(int reg) const {
296
+ return converter_.NameOfCPURegister(reg);
297
+ }
298
+
299
+
300
+ const char* NameOfByteCPURegister(int reg) const {
301
+ return converter_.NameOfByteCPURegister(reg);
302
+ }
303
+
304
+
305
+ const char* NameOfXMMRegister(int reg) const {
306
+ return converter_.NameOfXMMRegister(reg);
307
+ }
308
+
309
+
310
+ const char* NameOfAddress(byte* addr) const {
311
+ return converter_.NameOfAddress(addr);
312
+ }
313
+
314
+
315
+ // Disassembler helper functions.
316
+ static void get_modrm(byte data, int* mod, int* regop, int* rm) {
317
+ *mod = (data >> 6) & 3;
318
+ *regop = (data & 0x38) >> 3;
319
+ *rm = data & 7;
320
+ }
321
+
322
+
323
+ static void get_sib(byte data, int* scale, int* index, int* base) {
324
+ *scale = (data >> 6) & 3;
325
+ *index = (data >> 3) & 7;
326
+ *base = data & 7;
327
+ }
328
+
329
+ typedef const char* (DisassemblerIA32::*RegisterNameMapping)(int reg) const;
330
+
331
+ int PrintRightOperandHelper(byte* modrmp, RegisterNameMapping register_name);
332
+ int PrintRightOperand(byte* modrmp);
333
+ int PrintRightByteOperand(byte* modrmp);
334
+ int PrintOperands(const char* mnem, OperandOrder op_order, byte* data);
335
+ int PrintImmediateOp(byte* data);
336
+ int F7Instruction(byte* data);
337
+ int D1D3C1Instruction(byte* data);
338
+ int JumpShort(byte* data);
339
+ int JumpConditional(byte* data, const char* comment);
340
+ int JumpConditionalShort(byte* data, const char* comment);
341
+ int SetCC(byte* data);
342
+ int CMov(byte* data);
343
+ int FPUInstruction(byte* data);
344
+ int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
345
+ int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
346
+ void AppendToBuffer(const char* format, ...);
347
+
348
+
349
+ void UnimplementedInstruction() {
350
+ if (abort_on_unimplemented_) {
351
+ UNIMPLEMENTED();
352
+ } else {
353
+ AppendToBuffer("'Unimplemented Instruction'");
354
+ }
355
+ }
356
+ };
357
+
358
+
359
+ void DisassemblerIA32::AppendToBuffer(const char* format, ...) {
360
+ v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
361
+ va_list args;
362
+ va_start(args, format);
363
+ int result = v8::internal::OS::VSNPrintF(buf, format, args);
364
+ va_end(args);
365
+ tmp_buffer_pos_ += result;
366
+ }
367
+
368
+ int DisassemblerIA32::PrintRightOperandHelper(
369
+ byte* modrmp,
370
+ RegisterNameMapping register_name) {
371
+ int mod, regop, rm;
372
+ get_modrm(*modrmp, &mod, &regop, &rm);
373
+ switch (mod) {
374
+ case 0:
375
+ if (rm == ebp) {
376
+ int32_t disp = *reinterpret_cast<int32_t*>(modrmp+1);
377
+ AppendToBuffer("[0x%x]", disp);
378
+ return 5;
379
+ } else if (rm == esp) {
380
+ byte sib = *(modrmp + 1);
381
+ int scale, index, base;
382
+ get_sib(sib, &scale, &index, &base);
383
+ if (index == esp && base == esp && scale == 0 /*times_1*/) {
384
+ AppendToBuffer("[%s]", (this->*register_name)(rm));
385
+ return 2;
386
+ } else if (base == ebp) {
387
+ int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
388
+ AppendToBuffer("[%s*%d+0x%x]",
389
+ (this->*register_name)(index),
390
+ 1 << scale,
391
+ disp);
392
+ return 6;
393
+ } else if (index != esp && base != ebp) {
394
+ // [base+index*scale]
395
+ AppendToBuffer("[%s+%s*%d]",
396
+ (this->*register_name)(base),
397
+ (this->*register_name)(index),
398
+ 1 << scale);
399
+ return 2;
400
+ } else {
401
+ UnimplementedInstruction();
402
+ return 1;
403
+ }
404
+ } else {
405
+ AppendToBuffer("[%s]", (this->*register_name)(rm));
406
+ return 1;
407
+ }
408
+ break;
409
+ case 1: // fall through
410
+ case 2:
411
+ if (rm == esp) {
412
+ byte sib = *(modrmp + 1);
413
+ int scale, index, base;
414
+ get_sib(sib, &scale, &index, &base);
415
+ int disp =
416
+ mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 2) : *(modrmp + 2);
417
+ if (index == base && index == rm /*esp*/ && scale == 0 /*times_1*/) {
418
+ AppendToBuffer("[%s+0x%x]", (this->*register_name)(rm), disp);
419
+ } else {
420
+ AppendToBuffer("[%s+%s*%d+0x%x]",
421
+ (this->*register_name)(base),
422
+ (this->*register_name)(index),
423
+ 1 << scale,
424
+ disp);
425
+ }
426
+ return mod == 2 ? 6 : 3;
427
+ } else {
428
+ // No sib.
429
+ int disp =
430
+ mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 1) : *(modrmp + 1);
431
+ AppendToBuffer("[%s+0x%x]", (this->*register_name)(rm), disp);
432
+ return mod == 2 ? 5 : 2;
433
+ }
434
+ break;
435
+ case 3:
436
+ AppendToBuffer("%s", (this->*register_name)(rm));
437
+ return 1;
438
+ default:
439
+ UnimplementedInstruction();
440
+ return 1;
441
+ }
442
+ UNREACHABLE();
443
+ }
444
+
445
+
446
+ int DisassemblerIA32::PrintRightOperand(byte* modrmp) {
447
+ return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfCPURegister);
448
+ }
449
+
450
+
451
+ int DisassemblerIA32::PrintRightByteOperand(byte* modrmp) {
452
+ return PrintRightOperandHelper(modrmp,
453
+ &DisassemblerIA32::NameOfByteCPURegister);
454
+ }
455
+
456
+
457
+ // Returns number of bytes used including the current *data.
458
+ // Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
459
+ int DisassemblerIA32::PrintOperands(const char* mnem,
460
+ OperandOrder op_order,
461
+ byte* data) {
462
+ byte modrm = *data;
463
+ int mod, regop, rm;
464
+ get_modrm(modrm, &mod, &regop, &rm);
465
+ int advance = 0;
466
+ switch (op_order) {
467
+ case REG_OPER_OP_ORDER: {
468
+ AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
469
+ advance = PrintRightOperand(data);
470
+ break;
471
+ }
472
+ case OPER_REG_OP_ORDER: {
473
+ AppendToBuffer("%s ", mnem);
474
+ advance = PrintRightOperand(data);
475
+ AppendToBuffer(",%s", NameOfCPURegister(regop));
476
+ break;
477
+ }
478
+ default:
479
+ UNREACHABLE();
480
+ break;
481
+ }
482
+ return advance;
483
+ }
484
+
485
+
486
+ // Returns number of bytes used by machine instruction, including *data byte.
487
+ // Writes immediate instructions to 'tmp_buffer_'.
488
+ int DisassemblerIA32::PrintImmediateOp(byte* data) {
489
+ bool sign_extension_bit = (*data & 0x02) != 0;
490
+ byte modrm = *(data+1);
491
+ int mod, regop, rm;
492
+ get_modrm(modrm, &mod, &regop, &rm);
493
+ const char* mnem = "Imm???";
494
+ switch (regop) {
495
+ case 0: mnem = "add"; break;
496
+ case 1: mnem = "or"; break;
497
+ case 2: mnem = "adc"; break;
498
+ case 4: mnem = "and"; break;
499
+ case 5: mnem = "sub"; break;
500
+ case 6: mnem = "xor"; break;
501
+ case 7: mnem = "cmp"; break;
502
+ default: UnimplementedInstruction();
503
+ }
504
+ AppendToBuffer("%s ", mnem);
505
+ int count = PrintRightOperand(data+1);
506
+ if (sign_extension_bit) {
507
+ AppendToBuffer(",0x%x", *(data + 1 + count));
508
+ return 1 + count + 1 /*int8*/;
509
+ } else {
510
+ AppendToBuffer(",0x%x", *reinterpret_cast<int32_t*>(data + 1 + count));
511
+ return 1 + count + 4 /*int32_t*/;
512
+ }
513
+ }
514
+
515
+
516
+ // Returns number of bytes used, including *data.
517
+ int DisassemblerIA32::F7Instruction(byte* data) {
518
+ ASSERT_EQ(0xF7, *data);
519
+ byte modrm = *(data+1);
520
+ int mod, regop, rm;
521
+ get_modrm(modrm, &mod, &regop, &rm);
522
+ if (mod == 3 && regop != 0) {
523
+ const char* mnem = NULL;
524
+ switch (regop) {
525
+ case 2: mnem = "not"; break;
526
+ case 3: mnem = "neg"; break;
527
+ case 4: mnem = "mul"; break;
528
+ case 7: mnem = "idiv"; break;
529
+ default: UnimplementedInstruction();
530
+ }
531
+ AppendToBuffer("%s %s", mnem, NameOfCPURegister(rm));
532
+ return 2;
533
+ } else if (mod == 3 && regop == eax) {
534
+ int32_t imm = *reinterpret_cast<int32_t*>(data+2);
535
+ AppendToBuffer("test %s,0x%x", NameOfCPURegister(rm), imm);
536
+ return 6;
537
+ } else if (regop == eax) {
538
+ AppendToBuffer("test ");
539
+ int count = PrintRightOperand(data+1);
540
+ int32_t imm = *reinterpret_cast<int32_t*>(data+1+count);
541
+ AppendToBuffer(",0x%x", imm);
542
+ return 1+count+4 /*int32_t*/;
543
+ } else {
544
+ UnimplementedInstruction();
545
+ return 2;
546
+ }
547
+ }
548
+
549
+ int DisassemblerIA32::D1D3C1Instruction(byte* data) {
550
+ byte op = *data;
551
+ ASSERT(op == 0xD1 || op == 0xD3 || op == 0xC1);
552
+ byte modrm = *(data+1);
553
+ int mod, regop, rm;
554
+ get_modrm(modrm, &mod, &regop, &rm);
555
+ int imm8 = -1;
556
+ int num_bytes = 2;
557
+ if (mod == 3) {
558
+ const char* mnem = NULL;
559
+ switch (regop) {
560
+ case kROL: mnem = "rol"; break;
561
+ case kROR: mnem = "ror"; break;
562
+ case kRCL: mnem = "rcl"; break;
563
+ case kRCR: mnem = "rcr"; break;
564
+ case kSHL: mnem = "shl"; break;
565
+ case KSHR: mnem = "shr"; break;
566
+ case kSAR: mnem = "sar"; break;
567
+ default: UnimplementedInstruction();
568
+ }
569
+ if (op == 0xD1) {
570
+ imm8 = 1;
571
+ } else if (op == 0xC1) {
572
+ imm8 = *(data+2);
573
+ num_bytes = 3;
574
+ } else if (op == 0xD3) {
575
+ // Shift/rotate by cl.
576
+ }
577
+ ASSERT_NE(NULL, mnem);
578
+ AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm));
579
+ if (imm8 > 0) {
580
+ AppendToBuffer("%d", imm8);
581
+ } else {
582
+ AppendToBuffer("cl");
583
+ }
584
+ } else {
585
+ UnimplementedInstruction();
586
+ }
587
+ return num_bytes;
588
+ }
589
+
590
+
591
+ // Returns number of bytes used, including *data.
592
+ int DisassemblerIA32::JumpShort(byte* data) {
593
+ ASSERT_EQ(0xEB, *data);
594
+ byte b = *(data+1);
595
+ byte* dest = data + static_cast<int8_t>(b) + 2;
596
+ AppendToBuffer("jmp %s", NameOfAddress(dest));
597
+ return 2;
598
+ }
599
+
600
+
601
+ // Returns number of bytes used, including *data.
602
+ int DisassemblerIA32::JumpConditional(byte* data, const char* comment) {
603
+ ASSERT_EQ(0x0F, *data);
604
+ byte cond = *(data+1) & 0x0F;
605
+ byte* dest = data + *reinterpret_cast<int32_t*>(data+2) + 6;
606
+ const char* mnem = jump_conditional_mnem[cond];
607
+ AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
608
+ if (comment != NULL) {
609
+ AppendToBuffer(", %s", comment);
610
+ }
611
+ return 6; // includes 0x0F
612
+ }
613
+
614
+
615
+ // Returns number of bytes used, including *data.
616
+ int DisassemblerIA32::JumpConditionalShort(byte* data, const char* comment) {
617
+ byte cond = *data & 0x0F;
618
+ byte b = *(data+1);
619
+ byte* dest = data + static_cast<int8_t>(b) + 2;
620
+ const char* mnem = jump_conditional_mnem[cond];
621
+ AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
622
+ if (comment != NULL) {
623
+ AppendToBuffer(", %s", comment);
624
+ }
625
+ return 2;
626
+ }
627
+
628
+
629
+ // Returns number of bytes used, including *data.
630
+ int DisassemblerIA32::SetCC(byte* data) {
631
+ ASSERT_EQ(0x0F, *data);
632
+ byte cond = *(data+1) & 0x0F;
633
+ const char* mnem = set_conditional_mnem[cond];
634
+ AppendToBuffer("%s ", mnem);
635
+ PrintRightByteOperand(data+2);
636
+ return 3; // Includes 0x0F.
637
+ }
638
+
639
+
640
+ // Returns number of bytes used, including *data.
641
+ int DisassemblerIA32::CMov(byte* data) {
642
+ ASSERT_EQ(0x0F, *data);
643
+ byte cond = *(data + 1) & 0x0F;
644
+ const char* mnem = conditional_move_mnem[cond];
645
+ int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2);
646
+ return 2 + op_size; // includes 0x0F
647
+ }
648
+
649
+
650
+ // Returns number of bytes used, including *data.
651
+ int DisassemblerIA32::FPUInstruction(byte* data) {
652
+ byte escape_opcode = *data;
653
+ ASSERT_EQ(0xD8, escape_opcode & 0xF8);
654
+ byte modrm_byte = *(data+1);
655
+
656
+ if (modrm_byte >= 0xC0) {
657
+ return RegisterFPUInstruction(escape_opcode, modrm_byte);
658
+ } else {
659
+ return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
660
+ }
661
+ }
662
+
663
+ int DisassemblerIA32::MemoryFPUInstruction(int escape_opcode,
664
+ int modrm_byte,
665
+ byte* modrm_start) {
666
+ const char* mnem = "?";
667
+ int regop = (modrm_byte >> 3) & 0x7; // reg/op field of modrm byte.
668
+ switch (escape_opcode) {
669
+ case 0xD9: switch (regop) {
670
+ case 0: mnem = "fld_s"; break;
671
+ case 3: mnem = "fstp_s"; break;
672
+ case 7: mnem = "fstcw"; break;
673
+ default: UnimplementedInstruction();
674
+ }
675
+ break;
676
+
677
+ case 0xDB: switch (regop) {
678
+ case 0: mnem = "fild_s"; break;
679
+ case 1: mnem = "fisttp_s"; break;
680
+ case 2: mnem = "fist_s"; break;
681
+ case 3: mnem = "fistp_s"; break;
682
+ default: UnimplementedInstruction();
683
+ }
684
+ break;
685
+
686
+ case 0xDD: switch (regop) {
687
+ case 0: mnem = "fld_d"; break;
688
+ case 1: mnem = "fisttp_d"; break;
689
+ case 2: mnem = "fst_d"; break;
690
+ case 3: mnem = "fstp_d"; break;
691
+ default: UnimplementedInstruction();
692
+ }
693
+ break;
694
+
695
+ case 0xDF: switch (regop) {
696
+ case 5: mnem = "fild_d"; break;
697
+ case 7: mnem = "fistp_d"; break;
698
+ default: UnimplementedInstruction();
699
+ }
700
+ break;
701
+
702
+ default: UnimplementedInstruction();
703
+ }
704
+ AppendToBuffer("%s ", mnem);
705
+ int count = PrintRightOperand(modrm_start);
706
+ return count + 1;
707
+ }
708
+
709
+ int DisassemblerIA32::RegisterFPUInstruction(int escape_opcode,
710
+ byte modrm_byte) {
711
+ bool has_register = false; // Is the FPU register encoded in modrm_byte?
712
+ const char* mnem = "?";
713
+
714
+ switch (escape_opcode) {
715
+ case 0xD8:
716
+ UnimplementedInstruction();
717
+ break;
718
+
719
+ case 0xD9:
720
+ switch (modrm_byte & 0xF8) {
721
+ case 0xC0:
722
+ mnem = "fld";
723
+ has_register = true;
724
+ break;
725
+ case 0xC8:
726
+ mnem = "fxch";
727
+ has_register = true;
728
+ break;
729
+ default:
730
+ switch (modrm_byte) {
731
+ case 0xE0: mnem = "fchs"; break;
732
+ case 0xE1: mnem = "fabs"; break;
733
+ case 0xE4: mnem = "ftst"; break;
734
+ case 0xE8: mnem = "fld1"; break;
735
+ case 0xEB: mnem = "fldpi"; break;
736
+ case 0xED: mnem = "fldln2"; break;
737
+ case 0xEE: mnem = "fldz"; break;
738
+ case 0xF1: mnem = "fyl2x"; break;
739
+ case 0xF5: mnem = "fprem1"; break;
740
+ case 0xF7: mnem = "fincstp"; break;
741
+ case 0xF8: mnem = "fprem"; break;
742
+ case 0xFE: mnem = "fsin"; break;
743
+ case 0xFF: mnem = "fcos"; break;
744
+ default: UnimplementedInstruction();
745
+ }
746
+ }
747
+ break;
748
+
749
+ case 0xDA:
750
+ if (modrm_byte == 0xE9) {
751
+ mnem = "fucompp";
752
+ } else {
753
+ UnimplementedInstruction();
754
+ }
755
+ break;
756
+
757
+ case 0xDB:
758
+ if ((modrm_byte & 0xF8) == 0xE8) {
759
+ mnem = "fucomi";
760
+ has_register = true;
761
+ } else if (modrm_byte == 0xE2) {
762
+ mnem = "fclex";
763
+ } else {
764
+ UnimplementedInstruction();
765
+ }
766
+ break;
767
+
768
+ case 0xDC:
769
+ has_register = true;
770
+ switch (modrm_byte & 0xF8) {
771
+ case 0xC0: mnem = "fadd"; break;
772
+ case 0xE8: mnem = "fsub"; break;
773
+ case 0xC8: mnem = "fmul"; break;
774
+ case 0xF8: mnem = "fdiv"; break;
775
+ default: UnimplementedInstruction();
776
+ }
777
+ break;
778
+
779
+ case 0xDD:
780
+ has_register = true;
781
+ switch (modrm_byte & 0xF8) {
782
+ case 0xC0: mnem = "ffree"; break;
783
+ case 0xD8: mnem = "fstp"; break;
784
+ default: UnimplementedInstruction();
785
+ }
786
+ break;
787
+
788
+ case 0xDE:
789
+ if (modrm_byte == 0xD9) {
790
+ mnem = "fcompp";
791
+ } else {
792
+ has_register = true;
793
+ switch (modrm_byte & 0xF8) {
794
+ case 0xC0: mnem = "faddp"; break;
795
+ case 0xE8: mnem = "fsubp"; break;
796
+ case 0xC8: mnem = "fmulp"; break;
797
+ case 0xF8: mnem = "fdivp"; break;
798
+ default: UnimplementedInstruction();
799
+ }
800
+ }
801
+ break;
802
+
803
+ case 0xDF:
804
+ if (modrm_byte == 0xE0) {
805
+ mnem = "fnstsw_ax";
806
+ } else if ((modrm_byte & 0xF8) == 0xE8) {
807
+ mnem = "fucomip";
808
+ has_register = true;
809
+ }
810
+ break;
811
+
812
+ default: UnimplementedInstruction();
813
+ }
814
+
815
+ if (has_register) {
816
+ AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
817
+ } else {
818
+ AppendToBuffer("%s", mnem);
819
+ }
820
+ return 2;
821
+ }
822
+
823
+
824
+ // Mnemonics for instructions 0xF0 byte.
825
+ // Returns NULL if the instruction is not handled here.
826
+ static const char* F0Mnem(byte f0byte) {
827
+ switch (f0byte) {
828
+ case 0x18: return "prefetch";
829
+ case 0xA2: return "cpuid";
830
+ case 0x31: return "rdtsc";
831
+ case 0xBE: return "movsx_b";
832
+ case 0xBF: return "movsx_w";
833
+ case 0xB6: return "movzx_b";
834
+ case 0xB7: return "movzx_w";
835
+ case 0xAF: return "imul";
836
+ case 0xA5: return "shld";
837
+ case 0xAD: return "shrd";
838
+ case 0xAB: return "bts";
839
+ default: return NULL;
840
+ }
841
+ }
842
+
843
+
844
+ // Disassembled instruction '*instr' and writes it into 'out_buffer'.
845
+ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
846
+ byte* instr) {
847
+ tmp_buffer_pos_ = 0; // starting to write as position 0
848
+ byte* data = instr;
849
+ // Check for hints.
850
+ const char* branch_hint = NULL;
851
+ // We use these two prefixes only with branch prediction
852
+ if (*data == 0x3E /*ds*/) {
853
+ branch_hint = "predicted taken";
854
+ data++;
855
+ } else if (*data == 0x2E /*cs*/) {
856
+ branch_hint = "predicted not taken";
857
+ data++;
858
+ }
859
+ bool processed = true; // Will be set to false if the current instruction
860
+ // is not in 'instructions' table.
861
+ const InstructionDesc& idesc = instruction_table.Get(*data);
862
+ switch (idesc.type) {
863
+ case ZERO_OPERANDS_INSTR:
864
+ AppendToBuffer(idesc.mnem);
865
+ data++;
866
+ break;
867
+
868
+ case TWO_OPERANDS_INSTR:
869
+ data++;
870
+ data += PrintOperands(idesc.mnem, idesc.op_order_, data);
871
+ break;
872
+
873
+ case JUMP_CONDITIONAL_SHORT_INSTR:
874
+ data += JumpConditionalShort(data, branch_hint);
875
+ break;
876
+
877
+ case REGISTER_INSTR:
878
+ AppendToBuffer("%s %s", idesc.mnem, NameOfCPURegister(*data & 0x07));
879
+ data++;
880
+ break;
881
+
882
+ case MOVE_REG_INSTR: {
883
+ byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1));
884
+ AppendToBuffer("mov %s,%s",
885
+ NameOfCPURegister(*data & 0x07),
886
+ NameOfAddress(addr));
887
+ data += 5;
888
+ break;
889
+ }
890
+
891
+ case CALL_JUMP_INSTR: {
892
+ byte* addr = data + *reinterpret_cast<int32_t*>(data+1) + 5;
893
+ AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
894
+ data += 5;
895
+ break;
896
+ }
897
+
898
+ case SHORT_IMMEDIATE_INSTR: {
899
+ byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1));
900
+ AppendToBuffer("%s eax, %s", idesc.mnem, NameOfAddress(addr));
901
+ data += 5;
902
+ break;
903
+ }
904
+
905
+ case NO_INSTR:
906
+ processed = false;
907
+ break;
908
+
909
+ default:
910
+ UNIMPLEMENTED(); // This type is not implemented.
911
+ }
912
+ //----------------------------
913
+ if (!processed) {
914
+ switch (*data) {
915
+ case 0xC2:
916
+ AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data+1));
917
+ data += 3;
918
+ break;
919
+
920
+ case 0x69: // fall through
921
+ case 0x6B:
922
+ { int mod, regop, rm;
923
+ get_modrm(*(data+1), &mod, &regop, &rm);
924
+ int32_t imm =
925
+ *data == 0x6B ? *(data+2) : *reinterpret_cast<int32_t*>(data+2);
926
+ AppendToBuffer("imul %s,%s,0x%x",
927
+ NameOfCPURegister(regop),
928
+ NameOfCPURegister(rm),
929
+ imm);
930
+ data += 2 + (*data == 0x6B ? 1 : 4);
931
+ }
932
+ break;
933
+
934
+ case 0xF6:
935
+ { data++;
936
+ int mod, regop, rm;
937
+ get_modrm(*data, &mod, &regop, &rm);
938
+ if (regop == eax) {
939
+ AppendToBuffer("test_b ");
940
+ data += PrintRightOperand(data);
941
+ int32_t imm = *data;
942
+ AppendToBuffer(",0x%x", imm);
943
+ data++;
944
+ } else {
945
+ UnimplementedInstruction();
946
+ }
947
+ }
948
+ break;
949
+
950
+ case 0x81: // fall through
951
+ case 0x83: // 0x81 with sign extension bit set
952
+ data += PrintImmediateOp(data);
953
+ break;
954
+
955
+ case 0x0F:
956
+ { byte f0byte = *(data+1);
957
+ const char* f0mnem = F0Mnem(f0byte);
958
+ if (f0byte == 0x18) {
959
+ int mod, regop, rm;
960
+ get_modrm(*data, &mod, &regop, &rm);
961
+ const char* suffix[] = {"nta", "1", "2", "3"};
962
+ AppendToBuffer("%s%s ", f0mnem, suffix[regop & 0x03]);
963
+ data += PrintRightOperand(data);
964
+ } else if (f0byte == 0xA2 || f0byte == 0x31) {
965
+ AppendToBuffer("%s", f0mnem);
966
+ data += 2;
967
+ } else if (f0byte == 0x28) {
968
+ data += 2;
969
+ int mod, regop, rm;
970
+ get_modrm(*data, &mod, &regop, &rm);
971
+ AppendToBuffer("movaps %s,%s",
972
+ NameOfXMMRegister(regop),
973
+ NameOfXMMRegister(rm));
974
+ data++;
975
+ } else if ((f0byte & 0xF0) == 0x80) {
976
+ data += JumpConditional(data, branch_hint);
977
+ } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 ||
978
+ f0byte == 0xB7 || f0byte == 0xAF) {
979
+ data += 2;
980
+ data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data);
981
+ } else if ((f0byte & 0xF0) == 0x90) {
982
+ data += SetCC(data);
983
+ } else if ((f0byte & 0xF0) == 0x40) {
984
+ data += CMov(data);
985
+ } else {
986
+ data += 2;
987
+ if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
988
+ // shrd, shld, bts
989
+ AppendToBuffer("%s ", f0mnem);
990
+ int mod, regop, rm;
991
+ get_modrm(*data, &mod, &regop, &rm);
992
+ data += PrintRightOperand(data);
993
+ if (f0byte == 0xAB) {
994
+ AppendToBuffer(",%s", NameOfCPURegister(regop));
995
+ } else {
996
+ AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
997
+ }
998
+ } else {
999
+ UnimplementedInstruction();
1000
+ }
1001
+ }
1002
+ }
1003
+ break;
1004
+
1005
+ case 0x8F:
1006
+ { data++;
1007
+ int mod, regop, rm;
1008
+ get_modrm(*data, &mod, &regop, &rm);
1009
+ if (regop == eax) {
1010
+ AppendToBuffer("pop ");
1011
+ data += PrintRightOperand(data);
1012
+ }
1013
+ }
1014
+ break;
1015
+
1016
+ case 0xFF:
1017
+ { data++;
1018
+ int mod, regop, rm;
1019
+ get_modrm(*data, &mod, &regop, &rm);
1020
+ const char* mnem = NULL;
1021
+ switch (regop) {
1022
+ case esi: mnem = "push"; break;
1023
+ case eax: mnem = "inc"; break;
1024
+ case ecx: mnem = "dec"; break;
1025
+ case edx: mnem = "call"; break;
1026
+ case esp: mnem = "jmp"; break;
1027
+ default: mnem = "???";
1028
+ }
1029
+ AppendToBuffer("%s ", mnem);
1030
+ data += PrintRightOperand(data);
1031
+ }
1032
+ break;
1033
+
1034
+ case 0xC7: // imm32, fall through
1035
+ case 0xC6: // imm8
1036
+ { bool is_byte = *data == 0xC6;
1037
+ data++;
1038
+ AppendToBuffer("%s ", is_byte ? "mov_b" : "mov");
1039
+ data += PrintRightOperand(data);
1040
+ int32_t imm = is_byte ? *data : *reinterpret_cast<int32_t*>(data);
1041
+ AppendToBuffer(",0x%x", imm);
1042
+ data += is_byte ? 1 : 4;
1043
+ }
1044
+ break;
1045
+
1046
+ case 0x80:
1047
+ { data++;
1048
+ int mod, regop, rm;
1049
+ get_modrm(*data, &mod, &regop, &rm);
1050
+ const char* mnem = NULL;
1051
+ switch (regop) {
1052
+ case 5: mnem = "subb"; break;
1053
+ case 7: mnem = "cmpb"; break;
1054
+ default: UnimplementedInstruction();
1055
+ }
1056
+ AppendToBuffer("%s ", mnem);
1057
+ data += PrintRightOperand(data);
1058
+ int32_t imm = *data;
1059
+ AppendToBuffer(",0x%x", imm);
1060
+ data++;
1061
+ }
1062
+ break;
1063
+
1064
+ case 0x88: // 8bit, fall through
1065
+ case 0x89: // 32bit
1066
+ { bool is_byte = *data == 0x88;
1067
+ int mod, regop, rm;
1068
+ data++;
1069
+ get_modrm(*data, &mod, &regop, &rm);
1070
+ AppendToBuffer("%s ", is_byte ? "mov_b" : "mov");
1071
+ data += PrintRightOperand(data);
1072
+ AppendToBuffer(",%s", NameOfCPURegister(regop));
1073
+ }
1074
+ break;
1075
+
1076
+ case 0x66: // prefix
1077
+ data++;
1078
+ if (*data == 0x8B) {
1079
+ data++;
1080
+ data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data);
1081
+ } else if (*data == 0x89) {
1082
+ data++;
1083
+ int mod, regop, rm;
1084
+ get_modrm(*data, &mod, &regop, &rm);
1085
+ AppendToBuffer("mov_w ");
1086
+ data += PrintRightOperand(data);
1087
+ AppendToBuffer(",%s", NameOfCPURegister(regop));
1088
+ } else if (*data == 0x0F) {
1089
+ data++;
1090
+ if (*data == 0x38) {
1091
+ data++;
1092
+ if (*data == 0x17) {
1093
+ data++;
1094
+ int mod, regop, rm;
1095
+ get_modrm(*data, &mod, &regop, &rm);
1096
+ AppendToBuffer("ptest %s,%s",
1097
+ NameOfXMMRegister(regop),
1098
+ NameOfXMMRegister(rm));
1099
+ data++;
1100
+ } else if (*data == 0x2A) {
1101
+ // movntdqa
1102
+ data++;
1103
+ int mod, regop, rm;
1104
+ get_modrm(*data, &mod, &regop, &rm);
1105
+ AppendToBuffer("movntdqa %s,", NameOfXMMRegister(regop));
1106
+ data += PrintRightOperand(data);
1107
+ } else {
1108
+ UnimplementedInstruction();
1109
+ }
1110
+ } else if (*data == 0x3A) {
1111
+ data++;
1112
+ if (*data == 0x16) {
1113
+ data++;
1114
+ int mod, regop, rm;
1115
+ get_modrm(*data, &mod, &regop, &rm);
1116
+ int8_t imm8 = static_cast<int8_t>(data[1]);
1117
+ AppendToBuffer("pextrd %s,%s,%d",
1118
+ NameOfCPURegister(regop),
1119
+ NameOfXMMRegister(rm),
1120
+ static_cast<int>(imm8));
1121
+ data += 2;
1122
+ } else if (*data == 0x22) {
1123
+ data++;
1124
+ int mod, regop, rm;
1125
+ get_modrm(*data, &mod, &regop, &rm);
1126
+ int8_t imm8 = static_cast<int8_t>(data[1]);
1127
+ AppendToBuffer("pinsrd %s,%s,%d",
1128
+ NameOfXMMRegister(regop),
1129
+ NameOfCPURegister(rm),
1130
+ static_cast<int>(imm8));
1131
+ data += 2;
1132
+ } else {
1133
+ UnimplementedInstruction();
1134
+ }
1135
+ } else if (*data == 0x2E || *data == 0x2F) {
1136
+ const char* mnem = (*data == 0x2E) ? "ucomisd" : "comisd";
1137
+ data++;
1138
+ int mod, regop, rm;
1139
+ get_modrm(*data, &mod, &regop, &rm);
1140
+ if (mod == 0x3) {
1141
+ AppendToBuffer("%s %s,%s", mnem,
1142
+ NameOfXMMRegister(regop),
1143
+ NameOfXMMRegister(rm));
1144
+ data++;
1145
+ } else {
1146
+ AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
1147
+ data += PrintRightOperand(data);
1148
+ }
1149
+ } else if (*data == 0x50) {
1150
+ data++;
1151
+ int mod, regop, rm;
1152
+ get_modrm(*data, &mod, &regop, &rm);
1153
+ AppendToBuffer("movmskpd %s,%s",
1154
+ NameOfCPURegister(regop),
1155
+ NameOfXMMRegister(rm));
1156
+ data++;
1157
+ } else if (*data == 0x54) {
1158
+ data++;
1159
+ int mod, regop, rm;
1160
+ get_modrm(*data, &mod, &regop, &rm);
1161
+ AppendToBuffer("andpd %s,%s",
1162
+ NameOfXMMRegister(regop),
1163
+ NameOfXMMRegister(rm));
1164
+ data++;
1165
+ } else if (*data == 0x57) {
1166
+ data++;
1167
+ int mod, regop, rm;
1168
+ get_modrm(*data, &mod, &regop, &rm);
1169
+ AppendToBuffer("xorpd %s,%s",
1170
+ NameOfXMMRegister(regop),
1171
+ NameOfXMMRegister(rm));
1172
+ data++;
1173
+ } else if (*data == 0x6E) {
1174
+ data++;
1175
+ int mod, regop, rm;
1176
+ get_modrm(*data, &mod, &regop, &rm);
1177
+ AppendToBuffer("movd %s,", NameOfXMMRegister(regop));
1178
+ data += PrintRightOperand(data);
1179
+ } else if (*data == 0x6F) {
1180
+ data++;
1181
+ int mod, regop, rm;
1182
+ get_modrm(*data, &mod, &regop, &rm);
1183
+ AppendToBuffer("movdqa %s,", NameOfXMMRegister(regop));
1184
+ data += PrintRightOperand(data);
1185
+ } else if (*data == 0x70) {
1186
+ data++;
1187
+ int mod, regop, rm;
1188
+ get_modrm(*data, &mod, &regop, &rm);
1189
+ int8_t imm8 = static_cast<int8_t>(data[1]);
1190
+ AppendToBuffer("pshufd %s,%s,%d",
1191
+ NameOfXMMRegister(regop),
1192
+ NameOfXMMRegister(rm),
1193
+ static_cast<int>(imm8));
1194
+ data += 2;
1195
+ } else if (*data == 0xF3) {
1196
+ data++;
1197
+ int mod, regop, rm;
1198
+ get_modrm(*data, &mod, &regop, &rm);
1199
+ AppendToBuffer("psllq %s,%s",
1200
+ NameOfXMMRegister(regop),
1201
+ NameOfXMMRegister(rm));
1202
+ data++;
1203
+ } else if (*data == 0x73) {
1204
+ data++;
1205
+ int mod, regop, rm;
1206
+ get_modrm(*data, &mod, &regop, &rm);
1207
+ int8_t imm8 = static_cast<int8_t>(data[1]);
1208
+ ASSERT(regop == esi || regop == edx);
1209
+ AppendToBuffer("%s %s,%d",
1210
+ (regop == esi) ? "psllq" : "psrlq",
1211
+ NameOfXMMRegister(rm),
1212
+ static_cast<int>(imm8));
1213
+ data += 2;
1214
+ } else if (*data == 0xD3) {
1215
+ data++;
1216
+ int mod, regop, rm;
1217
+ get_modrm(*data, &mod, &regop, &rm);
1218
+ AppendToBuffer("psrlq %s,%s",
1219
+ NameOfXMMRegister(regop),
1220
+ NameOfXMMRegister(rm));
1221
+ data++;
1222
+ } else if (*data == 0x7F) {
1223
+ AppendToBuffer("movdqa ");
1224
+ data++;
1225
+ int mod, regop, rm;
1226
+ get_modrm(*data, &mod, &regop, &rm);
1227
+ data += PrintRightOperand(data);
1228
+ AppendToBuffer(",%s", NameOfXMMRegister(regop));
1229
+ } else if (*data == 0x7E) {
1230
+ data++;
1231
+ int mod, regop, rm;
1232
+ get_modrm(*data, &mod, &regop, &rm);
1233
+ AppendToBuffer("movd ");
1234
+ data += PrintRightOperand(data);
1235
+ AppendToBuffer(",%s", NameOfXMMRegister(regop));
1236
+ } else if (*data == 0xDB) {
1237
+ data++;
1238
+ int mod, regop, rm;
1239
+ get_modrm(*data, &mod, &regop, &rm);
1240
+ AppendToBuffer("pand %s,%s",
1241
+ NameOfXMMRegister(regop),
1242
+ NameOfXMMRegister(rm));
1243
+ data++;
1244
+ } else if (*data == 0xE7) {
1245
+ AppendToBuffer("movntdq ");
1246
+ data++;
1247
+ int mod, regop, rm;
1248
+ get_modrm(*data, &mod, &regop, &rm);
1249
+ data += PrintRightOperand(data);
1250
+ AppendToBuffer(",%s", NameOfXMMRegister(regop));
1251
+ } else if (*data == 0xEF) {
1252
+ data++;
1253
+ int mod, regop, rm;
1254
+ get_modrm(*data, &mod, &regop, &rm);
1255
+ AppendToBuffer("pxor %s,%s",
1256
+ NameOfXMMRegister(regop),
1257
+ NameOfXMMRegister(rm));
1258
+ data++;
1259
+ } else if (*data == 0xEB) {
1260
+ data++;
1261
+ int mod, regop, rm;
1262
+ get_modrm(*data, &mod, &regop, &rm);
1263
+ AppendToBuffer("por %s,%s",
1264
+ NameOfXMMRegister(regop),
1265
+ NameOfXMMRegister(rm));
1266
+ data++;
1267
+ } else {
1268
+ UnimplementedInstruction();
1269
+ }
1270
+ } else {
1271
+ UnimplementedInstruction();
1272
+ }
1273
+ break;
1274
+
1275
+ case 0xFE:
1276
+ { data++;
1277
+ int mod, regop, rm;
1278
+ get_modrm(*data, &mod, &regop, &rm);
1279
+ if (regop == ecx) {
1280
+ AppendToBuffer("dec_b ");
1281
+ data += PrintRightOperand(data);
1282
+ } else {
1283
+ UnimplementedInstruction();
1284
+ }
1285
+ }
1286
+ break;
1287
+
1288
+ case 0x68:
1289
+ AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data+1));
1290
+ data += 5;
1291
+ break;
1292
+
1293
+ case 0x6A:
1294
+ AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
1295
+ data += 2;
1296
+ break;
1297
+
1298
+ case 0xA8:
1299
+ AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data+1));
1300
+ data += 2;
1301
+ break;
1302
+
1303
+ case 0x2C:
1304
+ AppendToBuffer("subb eax,0x%x", *reinterpret_cast<uint8_t*>(data+1));
1305
+ data += 2;
1306
+ break;
1307
+
1308
+ case 0xA9:
1309
+ AppendToBuffer("test eax,0x%x", *reinterpret_cast<int32_t*>(data+1));
1310
+ data += 5;
1311
+ break;
1312
+
1313
+ case 0xD1: // fall through
1314
+ case 0xD3: // fall through
1315
+ case 0xC1:
1316
+ data += D1D3C1Instruction(data);
1317
+ break;
1318
+
1319
+ case 0xD9: // fall through
1320
+ case 0xDA: // fall through
1321
+ case 0xDB: // fall through
1322
+ case 0xDC: // fall through
1323
+ case 0xDD: // fall through
1324
+ case 0xDE: // fall through
1325
+ case 0xDF:
1326
+ data += FPUInstruction(data);
1327
+ break;
1328
+
1329
+ case 0xEB:
1330
+ data += JumpShort(data);
1331
+ break;
1332
+
1333
+ case 0xF2:
1334
+ if (*(data+1) == 0x0F) {
1335
+ byte b2 = *(data+2);
1336
+ if (b2 == 0x11) {
1337
+ AppendToBuffer("movsd ");
1338
+ data += 3;
1339
+ int mod, regop, rm;
1340
+ get_modrm(*data, &mod, &regop, &rm);
1341
+ data += PrintRightOperand(data);
1342
+ AppendToBuffer(",%s", NameOfXMMRegister(regop));
1343
+ } else if (b2 == 0x10) {
1344
+ data += 3;
1345
+ int mod, regop, rm;
1346
+ get_modrm(*data, &mod, &regop, &rm);
1347
+ AppendToBuffer("movsd %s,", NameOfXMMRegister(regop));
1348
+ data += PrintRightOperand(data);
1349
+ } else {
1350
+ const char* mnem = "?";
1351
+ switch (b2) {
1352
+ case 0x2A: mnem = "cvtsi2sd"; break;
1353
+ case 0x2C: mnem = "cvttsd2si"; break;
1354
+ case 0x51: mnem = "sqrtsd"; break;
1355
+ case 0x58: mnem = "addsd"; break;
1356
+ case 0x59: mnem = "mulsd"; break;
1357
+ case 0x5C: mnem = "subsd"; break;
1358
+ case 0x5E: mnem = "divsd"; break;
1359
+ }
1360
+ data += 3;
1361
+ int mod, regop, rm;
1362
+ get_modrm(*data, &mod, &regop, &rm);
1363
+ if (b2 == 0x2A) {
1364
+ if (mod != 0x3) {
1365
+ AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
1366
+ data += PrintRightOperand(data);
1367
+ } else {
1368
+ AppendToBuffer("%s %s,%s",
1369
+ mnem,
1370
+ NameOfXMMRegister(regop),
1371
+ NameOfCPURegister(rm));
1372
+ data++;
1373
+ }
1374
+ } else if (b2 == 0x2C) {
1375
+ if (mod != 0x3) {
1376
+ AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
1377
+ data += PrintRightOperand(data);
1378
+ } else {
1379
+ AppendToBuffer("%s %s,%s",
1380
+ mnem,
1381
+ NameOfCPURegister(regop),
1382
+ NameOfXMMRegister(rm));
1383
+ data++;
1384
+ }
1385
+ } else if (b2 == 0xC2) {
1386
+ // Intel manual 2A, Table 3-18.
1387
+ const char* const pseudo_op[] = {
1388
+ "cmpeqsd",
1389
+ "cmpltsd",
1390
+ "cmplesd",
1391
+ "cmpunordsd",
1392
+ "cmpneqsd",
1393
+ "cmpnltsd",
1394
+ "cmpnlesd",
1395
+ "cmpordsd"
1396
+ };
1397
+ AppendToBuffer("%s %s,%s",
1398
+ pseudo_op[data[1]],
1399
+ NameOfXMMRegister(regop),
1400
+ NameOfXMMRegister(rm));
1401
+ data += 2;
1402
+ } else {
1403
+ if (mod != 0x3) {
1404
+ AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
1405
+ data += PrintRightOperand(data);
1406
+ } else {
1407
+ AppendToBuffer("%s %s,%s",
1408
+ mnem,
1409
+ NameOfXMMRegister(regop),
1410
+ NameOfXMMRegister(rm));
1411
+ data++;
1412
+ }
1413
+ }
1414
+ }
1415
+ } else {
1416
+ UnimplementedInstruction();
1417
+ }
1418
+ break;
1419
+
1420
+ case 0xF3:
1421
+ if (*(data+1) == 0x0F) {
1422
+ if (*(data+2) == 0x2C) {
1423
+ data += 3;
1424
+ data += PrintOperands("cvttss2si", REG_OPER_OP_ORDER, data);
1425
+ } else if (*(data+2) == 0x5A) {
1426
+ data += 3;
1427
+ int mod, regop, rm;
1428
+ get_modrm(*data, &mod, &regop, &rm);
1429
+ AppendToBuffer("cvtss2sd %s,%s",
1430
+ NameOfXMMRegister(regop),
1431
+ NameOfXMMRegister(rm));
1432
+ data++;
1433
+ } else if (*(data+2) == 0x6F) {
1434
+ data += 3;
1435
+ int mod, regop, rm;
1436
+ get_modrm(*data, &mod, &regop, &rm);
1437
+ AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop));
1438
+ data += PrintRightOperand(data);
1439
+ } else if (*(data+2) == 0x7F) {
1440
+ AppendToBuffer("movdqu ");
1441
+ data += 3;
1442
+ int mod, regop, rm;
1443
+ get_modrm(*data, &mod, &regop, &rm);
1444
+ data += PrintRightOperand(data);
1445
+ AppendToBuffer(",%s", NameOfXMMRegister(regop));
1446
+ } else {
1447
+ UnimplementedInstruction();
1448
+ }
1449
+ } else if (*(data+1) == 0xA5) {
1450
+ data += 2;
1451
+ AppendToBuffer("rep_movs");
1452
+ } else if (*(data+1) == 0xAB) {
1453
+ data += 2;
1454
+ AppendToBuffer("rep_stos");
1455
+ } else {
1456
+ UnimplementedInstruction();
1457
+ }
1458
+ break;
1459
+
1460
+ case 0xF7:
1461
+ data += F7Instruction(data);
1462
+ break;
1463
+
1464
+ default:
1465
+ UnimplementedInstruction();
1466
+ }
1467
+ }
1468
+
1469
+ if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
1470
+ tmp_buffer_[tmp_buffer_pos_] = '\0';
1471
+ }
1472
+
1473
+ int instr_len = data - instr;
1474
+ if (instr_len == 0) {
1475
+ printf("%02x", *data);
1476
+ }
1477
+ ASSERT(instr_len > 0); // Ensure progress.
1478
+
1479
+ int outp = 0;
1480
+ // Instruction bytes.
1481
+ for (byte* bp = instr; bp < data; bp++) {
1482
+ outp += v8::internal::OS::SNPrintF(out_buffer + outp,
1483
+ "%02x",
1484
+ *bp);
1485
+ }
1486
+ for (int i = 6 - instr_len; i >= 0; i--) {
1487
+ outp += v8::internal::OS::SNPrintF(out_buffer + outp,
1488
+ " ");
1489
+ }
1490
+
1491
+ outp += v8::internal::OS::SNPrintF(out_buffer + outp,
1492
+ " %s",
1493
+ tmp_buffer_.start());
1494
+ return instr_len;
1495
+ } // NOLINT (function is too long)
1496
+
1497
+
1498
+ //------------------------------------------------------------------------------
1499
+
1500
+
1501
+ static const char* cpu_regs[8] = {
1502
+ "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"
1503
+ };
1504
+
1505
+
1506
+ static const char* byte_cpu_regs[8] = {
1507
+ "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
1508
+ };
1509
+
1510
+
1511
+ static const char* xmm_regs[8] = {
1512
+ "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"
1513
+ };
1514
+
1515
+
1516
+ const char* NameConverter::NameOfAddress(byte* addr) const {
1517
+ static v8::internal::EmbeddedVector<char, 32> tmp_buffer;
1518
+ v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr);
1519
+ return tmp_buffer.start();
1520
+ }
1521
+
1522
+
1523
+ const char* NameConverter::NameOfConstant(byte* addr) const {
1524
+ return NameOfAddress(addr);
1525
+ }
1526
+
1527
+
1528
+ const char* NameConverter::NameOfCPURegister(int reg) const {
1529
+ if (0 <= reg && reg < 8) return cpu_regs[reg];
1530
+ return "noreg";
1531
+ }
1532
+
1533
+
1534
+ const char* NameConverter::NameOfByteCPURegister(int reg) const {
1535
+ if (0 <= reg && reg < 8) return byte_cpu_regs[reg];
1536
+ return "noreg";
1537
+ }
1538
+
1539
+
1540
+ const char* NameConverter::NameOfXMMRegister(int reg) const {
1541
+ if (0 <= reg && reg < 8) return xmm_regs[reg];
1542
+ return "noxmmreg";
1543
+ }
1544
+
1545
+
1546
+ const char* NameConverter::NameInCode(byte* addr) const {
1547
+ // IA32 does not embed debug strings at the moment.
1548
+ UNREACHABLE();
1549
+ return "";
1550
+ }
1551
+
1552
+
1553
+ //------------------------------------------------------------------------------
1554
+
1555
+ Disassembler::Disassembler(const NameConverter& converter)
1556
+ : converter_(converter) {}
1557
+
1558
+
1559
+ Disassembler::~Disassembler() {}
1560
+
1561
+
1562
+ int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
1563
+ byte* instruction) {
1564
+ DisassemblerIA32 d(converter_, false /*do not crash if unimplemented*/);
1565
+ return d.InstructionDecode(buffer, instruction);
1566
+ }
1567
+
1568
+
1569
+ // The IA-32 assembler does not currently use constant pools.
1570
+ int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; }
1571
+
1572
+
1573
+ /*static*/ void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
1574
+ NameConverter converter;
1575
+ Disassembler d(converter);
1576
+ for (byte* pc = begin; pc < end;) {
1577
+ v8::internal::EmbeddedVector<char, 128> buffer;
1578
+ buffer[0] = '\0';
1579
+ byte* prev_pc = pc;
1580
+ pc += d.InstructionDecode(buffer, pc);
1581
+ fprintf(f, "%p", prev_pc);
1582
+ fprintf(f, " ");
1583
+
1584
+ for (byte* bp = prev_pc; bp < pc; bp++) {
1585
+ fprintf(f, "%02x", *bp);
1586
+ }
1587
+ for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
1588
+ fprintf(f, " ");
1589
+ }
1590
+ fprintf(f, " %s\n", buffer.start());
1591
+ }
1592
+ }
1593
+
1594
+
1595
+ } // namespace disasm
1596
+
1597
+ #endif // V8_TARGET_ARCH_IA32