siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/flows/showflow.py

@@ -0,0 +1,59 @@
+import siliconcompiler
+from siliconcompiler import SiliconCompilerError
+
+
+############################################################################
+# DOCS
+############################################################################
+def make_docs(chip):
+    chip.load_target('freepdk45_demo')
+    return setup(chip, filetype='gds', np=3)
+
+
+###########################################################################
+# Flowgraph Setup
+############################################################################
+def setup(chip, flowname='showflow', filetype=None, screenshot=False, np=1):
+    '''
+    A flow to show the output files generated from other flows.
+
+    Required settings for this flow are below:
+
+    * filetype : Type of file to show
+
+    Optional settings for this flow are below:
+
+    * np : Number of parallel show jobs to launch
+    * screenshot : true/false, indicate if this should be configured as a screenshot
+    '''
+
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    # Get required parameters first
+    if not filetype:
+        raise ValueError('filetype is a required argument')
+
+    if filetype not in chip._showtools:
+        raise SiliconCompilerError(f'Show tool for {filetype} is not defined.')
+
+    show_tool = chip._showtools[filetype]
+
+    stepname = 'show'
+    if screenshot:
+        stepname = 'screenshot'
+
+    if stepname not in show_tool:
+        raise SiliconCompilerError(f'{stepname} for {filetype} is not defined.')
+
+    for idx in range(np):
+        flow.node(flowname, stepname, show_tool[stepname], index=idx)
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/signoffflow.py

@@ -0,0 +1,53 @@
+import siliconcompiler
+
+from siliconcompiler.tools.magic import extspice
+from siliconcompiler.tools.magic import drc
+from siliconcompiler.tools.netgen import lvs
+from siliconcompiler.tools.builtin import nop
+from siliconcompiler.tools.builtin import join
+
+
+def make_docs(chip):
+    chip.set('input', 'netlist', 'verilog', 'test')
+    return setup(chip)
+
+
+def setup(chip):
+    '''A flow for running LVS/DRC signoff on a GDS layout.
+
+    Inputs must be passed to this flow as follows::
+
+        flow.input('<path-to-layout>.gds')
+        flow.input('<path-to-netlist>.vg')
+    '''
+    flowname = 'signoffflow'
+
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    # nop import since we don't need to pull in any sources
+    flow.node(flowname, 'import', nop)
+
+    flow.node(flowname, 'extspice', extspice)
+    flow.node(flowname, 'drc', drc)
+    flow.node(flowname, 'lvs', lvs)
+    flow.node(flowname, 'signoff', join)
+
+    flow.edge(flowname, 'import', 'drc')
+    flow.edge(flowname, 'import', 'extspice')
+    flow.edge(flowname, 'extspice', 'lvs')
+    flow.edge(flowname, 'lvs', 'signoff')
+    flow.edge(flowname, 'drc', 'signoff')
+
+    # Set default goal
+    for step in flow.getkeys('flowgraph', flowname):
+        flow.set('flowgraph', flowname, step, '0', 'goal', 'errors', 0)
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/synflow.py

@@ -0,0 +1,128 @@
+import siliconcompiler
+
+from siliconcompiler.flows._common import setup_multiple_frontends
+from siliconcompiler.flows._common import _make_docs
+
+from siliconcompiler.tools.yosys import syn_asic
+from siliconcompiler.tools.opensta import timing
+
+from siliconcompiler.tools.builtin import minimum
+
+
+############################################################################
+# DOCS
+############################################################################
+def make_docs(chip):
+    n = 3
+    _make_docs(chip)
+    return setup(chip, syn_np=n, timing_np=n)
+
+
+###########################################################################
+# Flowgraph Setup
+############################################################################
+def setup(chip,
+          flowname='synflow',
+          syn_np=1,
+          timing_np=1):
+    '''
+    A configurable ASIC synthesys flow with static timing.
+
+    The 'synflow' includes the stages below. The steps syn have
+    minimization associated with them.
+    To view the flowgraph, see the .png file.
+
+    * **import**: Sources are collected and packaged for compilation
+    * **syn**: Translates RTL to netlist using Yosys
+    * **timing**: Create timing reports of design
+
+    The syn and timing steps supports per process
+    options that can be set up by setting 'syn_np' or 'timing_np'
+    arg to a value > 1, as detailed below:
+
+    * syn_np : Number of parallel synthesis jobs to launch
+    * timing_np : Number of parallel timing jobs to launch
+    '''
+
+    flow = siliconcompiler.Flow(chip, flowname)
+
+    # Linear flow, up until branch to run parallel verification steps.
+    longpipe = ['syn',
+                'synmin',
+                'timing']
+
+    # step --> task
+    tasks = {
+        'syn': syn_asic,
+        'synmin': minimum,
+        'timing': timing
+    }
+
+    np = {
+        "syn": syn_np,
+        "timing": timing_np
+    }
+
+    prevstep = None
+    # Remove built in steps where appropriate
+    flowpipe = []
+    for step in longpipe:
+        task = tasks[step]
+        if task == minimum:
+            if prevstep in np and np[prevstep] > 1:
+                flowpipe.append(step)
+        else:
+            flowpipe.append(step)
+        prevstep = step
+
+    flowtasks = []
+    for step in flowpipe:
+        flowtasks.append((step, tasks[step]))
+
+    # Programmatically build linear portion of flowgraph and fanin/fanout args
+    prevstep = setup_multiple_frontends(chip, flow)
+    for step, task in flowtasks:
+        fanout = 1
+        if step in np:
+            fanout = np[step]
+        # create nodes
+        for index in range(fanout):
+            # nodes
+            flow.node(flowname, step, task, index=index)
+
+            # edges
+            if task == minimum:
+                fanin = 1
+                if prevstep in np:
+                    fanin = np[prevstep]
+                for i in range(fanin):
+                    flow.edge(flowname, prevstep, step, tail_index=i)
+            elif prevstep:
+                flow.edge(flowname, prevstep, step, head_index=index)
+
+            # metrics
+            goal_metrics = ()
+            weight_metrics = ()
+            if task in (syn_asic, ):
+                goal_metrics = ('errors',)
+                weight_metrics = ()
+            elif task in (timing, ):
+                goal_metrics = ('errors', 'setupwns', 'setuptns')
+                weight_metrics = ('cellarea', 'peakpower', 'leakagepower')
+
+            for metric in goal_metrics:
+                flow.set('flowgraph', flowname, step, str(index), 'goal', metric, 0)
+            for metric in weight_metrics:
+                flow.set('flowgraph', flowname, step, str(index), 'weight', metric, 1.0)
+        prevstep = step
+
+    return flow
+
+
+##################################################
+if __name__ == "__main__":
+    chip = siliconcompiler.Chip('design')
+    chip.set('input', 'constraint', 'sdc', 'test')
+    flow = make_docs(chip)
+    chip.use(flow)
+    chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/fpgas/lattice_ice40.py

@@ -0,0 +1,42 @@
+import siliconcompiler
+from siliconcompiler.utils import register_sc_data_source
+
+
+####################################################
+# Setup for ICE40 Family FPGAs
+####################################################
+def setup(chip):
+    '''
+    Lattice ICE40 FPGAs are a family of small parts
+    made by Lattice Semiconductor.  A fully open source
+    RTL to bitstream flow for ICE40 is available using
+    yosys + nextpnr
+    '''
+
+    vendor = 'lattice'
+
+    lut_size = '4'
+
+    all_fpgas = []
+
+    all_part_names = [
+        "ice40up5k-sg48",
+    ]
+
+    register_sc_data_source(chip)
+
+    for part_name in all_part_names:
+        fpga = siliconcompiler.FPGA(chip, part_name, package='siliconcompiler_data')
+
+        fpga.set('fpga', part_name, 'vendor', vendor)
+        fpga.set('fpga', part_name, 'lutsize', lut_size)
+
+        all_fpgas.append(fpga)
+
+    return all_fpgas
+
+
+#########################
+if __name__ == "__main__":
+    for fpga in setup(siliconcompiler.Chip('<fpga>')):
+        fpga.write_manifest(f'{fpga.design}.json')

siliconcompiler/fpgas/vpr_example.py

@@ -0,0 +1,109 @@
+import os
+import siliconcompiler
+from siliconcompiler.utils import register_sc_data_source
+
+
+####################################################
+# Setup for vpr_example Family FPGAs
+####################################################
+def setup(chip):
+    '''
+    The vpr_example FPGA family is a set of
+    open source architectures used as illustrative
+    examples for academic FPGA architectures.  They
+    are based on numerous examples furnished over the
+    the years by the University of Toronto with different
+    distributions of VPR
+
+    For more information about VPR and its architecture models,
+    see Murray et. al, "VTR 8: High Performance CAD and Customizable
+    FPGA Architecture Modelling", ACM Trans. Reconfigurable Technol.
+    Syst., 2020, https://www.eecg.utoronto.ca/~kmurray/vtr/vtr8_trets.pdf
+    '''
+
+    vendor = 'N/A'
+
+    flow_root = os.path.join('examples', 'fpga_flow')
+
+    lut_size = '4'
+
+    all_fpgas = []
+
+    all_part_names = [
+        'example_arch_X005Y005',
+        'example_arch_X008Y008',
+        'example_arch_X014Y014',
+        'example_arch_X030Y030',
+    ]
+
+    register_sc_data_source(chip)
+
+    # Settings common to all parts in family
+    for part_name in all_part_names:
+        fpga = siliconcompiler.FPGA(chip, part_name, package='siliconcompiler_data')
+
+        fpga.set('fpga', part_name, 'vendor', vendor)
+
+        fpga.set('fpga', part_name, 'lutsize', lut_size)
+
+        arch_root = os.path.join(flow_root, 'arch', part_name)
+        fpga.set('fpga', part_name, 'file', 'archfile', os.path.join(arch_root, f'{part_name}.xml'))
+
+        fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'ideal')
+
+        if (part_name == 'example_arch_X005Y005'):
+            arch_root = os.path.join(flow_root, 'arch', part_name)
+            fpga.set('fpga', part_name, 'file', 'graphfile',
+                     os.path.join(arch_root, 'example_arch_X005Y005_rr_graph.xml'))
+            fpga.set('fpga', part_name, 'var', 'channelwidth', '32')
+
+        if (part_name == 'example_arch_X008Y008'):
+            # No RR graph for this architecture to support testing
+            fpga.set('fpga', part_name, 'var', 'channelwidth', '32')
+
+        if ((part_name == 'example_arch_X014Y014') or (part_name == 'example_arch_X030Y030')):
+
+            techlib_root = os.path.join(flow_root, 'techlib')
+
+            if (part_name == 'example_arch_X014Y014'):
+                fpga.set('fpga', part_name, 'file', 'constraints_map',
+                         os.path.join(arch_root, f'{part_name}_constraint_map.json'))
+
+            fpga.set('fpga', part_name, 'var', 'channelwidth', '80')
+            fpga.add('fpga', part_name, 'var', 'feature_set', 'async_set')
+            fpga.add('fpga', part_name, 'var', 'feature_set', 'async_reset')
+            fpga.add('fpga', part_name, 'var', 'feature_set', 'enable')
+            fpga.add('fpga', part_name, 'file', 'yosys_flop_techmap',
+                     os.path.join(techlib_root, 'example_arch_techmap_flops.v'))
+
+            fpga.add('fpga', part_name, 'file', 'yosys_dsp_techmap',
+                     os.path.join(techlib_root, 'example_arch_techmap_dsp.v'))
+
+            fpga.add('fpga', part_name, 'file', 'yosys_extractlib',
+                     os.path.join(techlib_root, 'example_arch_techmap_dsp_extract.v'))
+
+            # The same library used for the extraction pass can also be used to
+            # define macros that can be passed through synthesis, specify that here
+            fpga.add('fpga', part_name, 'file', 'yosys_macrolib',
+                     os.path.join(techlib_root, 'example_arch_techmap_dsp_extract.v'))
+
+            fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MAXWIDTH=18')
+            fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MAXWIDTH=18')
+            fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_A_MINWIDTH=2')
+            fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_B_MINWIDTH=2')
+            fpga.add('fpga', part_name, 'var', 'yosys_dsp_options', 'DSP_NAME=_dsp_block_')
+
+            fpga.add('fpga', part_name, 'file', 'yosys_memory_techmap',
+                     os.path.join(techlib_root, 'example_arch_techmap_bram.v'))
+            fpga.add('fpga', part_name, 'file', 'yosys_memory_libmap',
+                     os.path.join(techlib_root, 'example_arch_bram_memory_map.txt'))
+
+        all_fpgas.append(fpga)
+
+    return all_fpgas
+
+
+#########################
+if __name__ == "__main__":
+    for fpga in setup(siliconcompiler.Chip('<fpga>')):
+        fpga.write_manifest(f'{fpga.design}.json')

siliconcompiler/issue.py

@@ -0,0 +1,300 @@
+import git
+import json
+import os
+import shutil
+import sys
+import tarfile
+import time
+import tempfile
+from datetime import datetime
+from siliconcompiler.utils import get_file_template
+from siliconcompiler.scheduler import _makecmd, _write_task_manifest, _get_machine_info
+from siliconcompiler.tools._common import get_tool_task
+
+
+def generate_testcase(chip,
+                      step,
+                      index,
+                      archive_name=None,
+                      archive_directory=None,
+                      include_pdks=True,
+                      include_specific_pdks=None,
+                      include_libraries=True,
+                      include_specific_libraries=None,
+                      hash_files=False,
+                      verbose_collect=True):
+
+    # Save original schema since it will be modified
+    schema_copy = chip.schema.copy()
+
+    issue_dir = tempfile.TemporaryDirectory(prefix='sc_issue_')
+
+    chip.set('option', 'continue', True)
+    if hash_files:
+        for key in chip.allkeys():
+            if key[0] == 'history':
+                continue
+            if len(key) > 1:
+                if key[-2] == 'option' and key[-1] == 'builddir':
+                    continue
+                if key[-2] == 'option' and key[-1] == 'cachedir':
+                    continue
+            sc_type = chip.get(*key, field='type')
+            if 'file' not in sc_type and 'dir' not in sc_type:
+                continue
+            for _, key_step, key_index in chip.schema._getvals(*key):
+                chip.hash_files(*key,
+                                check=False,
+                                allow_cache=True,
+                                verbose=False,
+                                skip_missing=True,
+                                step=key_step, index=key_index)
+
+    manifest_path = os.path.join(issue_dir.name, 'orig_manifest.json')
+    chip.write_manifest(manifest_path)
+
+    flow = chip.get('option', 'flow')
+    tool, task = get_tool_task(chip, step, index, flow=flow)
+    task_requires = chip.get('tool', tool, 'task', task, 'require',
+                             step=step, index=index)
+
+    def determine_copy(*keypath, in_require):
+        copy = in_require
+
+        if keypath[0] == 'library':
+            # only copy libraries if selected
+            if include_specific_libraries and keypath[1] in include_specific_libraries:
+                copy = True
+            else:
+                copy = include_libraries
+
+            copy = copy and determine_copy(*keypath[2:], in_require=in_require)
+        elif keypath[0] == 'pdk':
+            # only copy pdks if selected
+            if include_specific_pdks and keypath[1] in include_specific_pdks:
+                copy = True
+            else:
+                copy = include_pdks
+        elif keypath[0] == 'history':
+            # Skip history
+            copy = False
+        elif keypath[0] == 'package':
+            # Skip packages
+            copy = False
+        elif keypath[0] == 'tool':
+            # Only grab tool / tasks
+            copy = False
+            if list(keypath[0:4]) == ['tool', tool, 'task', task]:
+                # Get files associated with testcase tool / task
+                copy = True
+                if len(keypath) >= 5:
+                    if keypath[4] in ('output', 'input', 'report'):
+                        # Skip input, output, and report files
+                        copy = False
+        elif keypath[0] == 'option':
+            if keypath[1] == 'builddir':
+                # Avoid build directory
+                copy = False
+            elif keypath[1] == 'cachedir':
+                # Avoid cache directory
+                copy = False
+            elif keypath[1] == 'cfg':
+                # Avoid all of cfg, since we are getting the manifest separately
+                copy = False
+            elif keypath[1] == 'credentials':
+                # Exclude credentials file
+                copy = False
+
+        return copy
+
+    for keypath in chip.allkeys():
+        if 'default' in keypath:
+            continue
+
+        sctype = chip.get(*keypath, field='type')
+        if 'file' not in sctype and 'dir' not in sctype:
+            continue
+
+        chip.set(*keypath,
+                 determine_copy(*keypath,
+                                in_require=','.join(keypath) in task_requires),
+                 field='copy')
+
+    # Collect files
+    work_dir = chip.getworkdir(step=step, index=index)
+
+    builddir = chip.get('option', 'builddir')
+    if os.path.isabs(builddir):
+        # If build is an abs path, grab last directory
+        chip.set('option', 'builddir', os.path.basename(builddir))
+
+    # Temporarily change current directory to appear to be issue_dir
+    original_cwd = chip.cwd
+    chip.cwd = issue_dir.name
+
+    # Get new directories
+    job_dir = chip.getworkdir()
+    new_work_dir = chip.getworkdir(step=step, index=index)
+    collection_dir = chip._getcollectdir()
+
+    # Restore current directory
+    chip.cwd = original_cwd
+
+    # Copy in issue run files
+    shutil.copytree(work_dir, new_work_dir, dirs_exist_ok=True)
+    # Copy in source files
+    chip.collect(directory=collection_dir, verbose=verbose_collect)
+
+    # Set relative path to generate runnable files
+    chip._relative_path = new_work_dir
+    chip.cwd = issue_dir.name
+
+    current_work_dir = os.getcwd()
+    os.chdir(new_work_dir)
+
+    # Rewrite replay.sh
+    prev_quiet = chip.get('option', 'quiet', step=step, index=index)
+    chip.set('option', 'quiet', True, step=step, index=index)
+    from siliconcompiler import SiliconCompilerError
+    try:
+        # Rerun setup
+        chip.set('arg', 'step', step)
+        chip.set('arg', 'index', index)
+        func = getattr(chip._get_task_module(step, index, flow=flow), 'pre_process', None)
+        if func:
+            try:
+                # Rerun pre_process
+                func(chip)
+            except Exception:
+                pass
+    except SiliconCompilerError:
+        pass
+    chip.set('option', 'quiet', prev_quiet, step=step, index=index)
+
+    flow = chip.get('option', 'flow')
+    is_python_tool = hasattr(chip._get_task_module(step, index, flow=flow), 'run')
+
+    if not is_python_tool:
+        _makecmd(chip,
+                 tool, task, step, index,
+                 script_name=f'{chip.getworkdir(step=step, index=index)}/replay.sh',
+                 include_path=False)
+
+    # Rewrite tool manifest
+    chip.set('arg', 'step', step)
+    chip.set('arg', 'index', index)
+    _write_task_manifest(chip, tool, path=new_work_dir)
+
+    # Restore normal path behavior
+    chip._relative_path = None
+
+    # Restore current directory
+    chip.cwd = original_cwd
+    os.chdir(current_work_dir)
+
+    git_data = {}
+    try:
+        # Check git information
+        repo = git.Repo(path=os.path.join(chip.scroot, '..'))
+        commit = repo.head.commit
+        git_data['commit'] = commit.hexsha
+        git_data['date'] = time.strftime('%Y-%m-%d %H:%M:%S',
+                                         time.gmtime(commit.committed_date))
+        git_data['author'] = f'{commit.author.name} <{commit.author.email}>'
+        git_data['msg'] = commit.message
+        # Count number of commits ahead of version
+        version_tag = repo.tag(f'v{chip.scversion}')
+        count = 0
+        for c in commit.iter_parents():
+            count += 1
+            if c == version_tag.commit:
+                break
+        git_data['count'] = count
+    except git.InvalidGitRepositoryError:
+        pass
+    except Exception as e:
+        git_data['failed'] = str(e)
+        pass
+
+    tool, task = get_tool_task(chip, step=step, index=index)
+
+    issue_time = time.time()
+    issue_information = {}
+    issue_information['environment'] = {key: value for key, value in os.environ.items()}
+    issue_information['python'] = {"path": sys.path,
+                                   "version": sys.version}
+    issue_information['date'] = datetime.fromtimestamp(issue_time).strftime('%Y-%m-%d %H:%M:%S')
+    issue_information['machine'] = _get_machine_info()
+    issue_information['run'] = {'step': step,
+                                'index': index,
+                                'libraries_included': include_libraries,
+                                'pdks_included': include_pdks,
+                                'tool': tool,
+                                'toolversion': chip.get('record', 'toolversion',
+                                                        step=step, index=index),
+                                'task': task}
+    issue_information['version'] = {'schema': chip.schemaversion,
+                                    'sc': chip.scversion,
+                                    'git': git_data}
+
+    if not archive_name:
+        design = chip.design
+        job = chip.get('option', 'jobname')
+        file_time = datetime.fromtimestamp(issue_time).strftime('%Y%m%d-%H%M%S')
+        archive_name = f'sc_issue_{design}_{job}_{step}{index}_{file_time}.tar.gz'
+
+    # Make support files
+    issue_path = os.path.join(issue_dir.name, 'issue.json')
+    with open(issue_path, 'w') as fd:
+        json.dump(issue_information, fd, indent=4, sort_keys=True)
+
+    readme_path = os.path.join(issue_dir.name, 'README.txt')
+    with open(readme_path, 'w') as f:
+        f.write(get_file_template('issue/README.txt').render(
+            archive_name=archive_name,
+            has_run=not is_python_tool,
+            **issue_information))
+
+    run_path = None
+    if not is_python_tool:
+        run_path = os.path.join(issue_dir.name, 'run.sh')
+        with open(run_path, 'w') as f:
+            replay_dir = os.path.relpath(chip.getworkdir(step=step, index=index),
+                                         chip.cwd)
+            issue_title = f'{chip.design} for {step}{index} using {tool}/{task}'
+            f.write(get_file_template('issue/run.sh').render(
+                title=issue_title,
+                exec_dir=replay_dir
+            ))
+        os.chmod(run_path, 0o755)
+
+    full_archive_path = archive_name
+    if archive_directory:
+        full_archive_path = os.path.join(archive_directory, archive_name)
+    full_archive_path = os.path.abspath(full_archive_path)
+    # Build archive
+    arch_base_dir = os.path.basename(archive_name).split('.')[0]
+    with tarfile.open(full_archive_path, "w:gz") as tar:
+        # Add individual files
+        add_files = [manifest_path,
+                     issue_path,
+                     readme_path]
+        if not is_python_tool:
+            add_files.append(run_path)
+        for path in add_files:
+            tar.add(os.path.abspath(path),
+                    arcname=os.path.join(arch_base_dir,
+                                         os.path.basename(path)))
+
+        tar.add(job_dir,
+                arcname=os.path.join(arch_base_dir,
+                                     os.path.relpath(job_dir,
+                                                     issue_dir.name)))
+
+    issue_dir.cleanup()
+
+    chip.logger.info(f'Generated testcase for {step}{index} in: '
+                     f'{full_archive_path}')
+
+    # Restore original schema
+    chip.schema = schema_copy