siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/ghdl/convert.py

@@ -0,0 +1,87 @@
+import os
+from siliconcompiler.tools._common import add_require_input, add_frontend_requires, \
+    get_input_files, get_tool_task, has_input_files
+
+
+def setup(chip):
+    '''
+    Imports VHDL and converts it to verilog
+    '''
+
+    # Standard Setup
+    tool = 'ghdl'
+    clobber = False
+
+    if not has_input_files(chip, 'input', 'rtl', 'vhdl'):
+        return "no files in [input,rtl,vhdl]"
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'ghdl')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=4.0.0-dev', clobber=clobber)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', '',
+             step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'output',
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'stdout', 'suffix', 'v',
+             step=step, index=index)
+
+    # Schema requirements
+    add_require_input(chip, 'input', 'rtl', 'vhdl')
+    add_frontend_requires(chip, ['define'])
+
+    design = chip.top()
+
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.v', step=step, index=index)
+
+
+################################
+#  Custom runtime options
+################################
+def runtime_options(chip):
+
+    ''' Custom runtime options, returnst list of command line options.
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    options = []
+
+    # Synthesize inputs and output Verilog netlist
+    options.append('--synth')
+    options.append('--std=08')
+    options.append('--out=verilog')
+    options.append('--no-formal')
+
+    # currently only -fsynopsys and --latches supported
+    valid_extraopts = ['-fsynopsys', '--latches']
+
+    extra_opts = chip.get('tool', 'ghdl', 'task', task, 'var', 'extraopts', step=step, index=index)
+    for opt in extra_opts:
+        if opt in valid_extraopts:
+            options.append(opt)
+        else:
+            chip.error('Unsupported option ' + opt)
+
+    # Add defines
+    for define in chip.get('option', 'define'):
+        options.append(f'-g{define}')
+
+    # Add sources
+    for value in get_input_files(chip, 'input', 'rtl', 'vhdl'):
+        options.append(value)
+
+    # Set top module
+    options.append('-e')
+
+    options.append(chip.top(step=step, index=index))
+
+    return options

siliconcompiler/tools/ghdl/ghdl.py

@@ -0,0 +1,41 @@
+
+'''
+GHDL is an open-source analyzer, compiler, simulator and
+(experimental) synthesizer for VHDL. It allows you to analyse
+and elaborate sources for generating machine code from your design.
+Native program execution is the only way for high speed simulation.
+
+Documentation: https://ghdl.readthedocs.io/en/latest
+
+Sources: https://github.com/ghdl/ghdl
+
+Installation: https://github.com/ghdl/ghdl
+'''
+
+from siliconcompiler.tools.ghdl import convert
+
+
+#####################################################################
+# Make Docs
+#####################################################################
+def make_docs(chip):
+    convert.setup(chip)
+    return chip
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # first line: GHDL 2.0.0-dev (1.0.0.r827.ge49cb7b9) [Dunoon edition]
+
+    # '*-dev' is interpreted by packaging.version as a "developmental release",
+    # which has the correct semantics. e.g. Version('2.0.0') > Version('2.0.0-dev')
+    return stdout.split()[1]
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("ghdl.json")

siliconcompiler/tools/icarus/compile.py

@@ -0,0 +1,87 @@
+import os
+from siliconcompiler.tools._common import \
+    add_require_input, add_frontend_requires, get_input_files, get_frontend_options, \
+    get_tool_task
+
+
+def setup(chip):
+    '''
+    Compile the input verilog into a vvp file that can be simulated.
+    '''
+
+    # If the 'lock' bit is set, don't reconfigure.
+    tool = 'icarus'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Standard Setup
+    chip.set('tool', tool, 'exe', 'iverilog')
+    chip.set('tool', tool, 'vswitch', '-V')
+    chip.set('tool', tool, 'version', '>=10.3', clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'verilog_generation',
+             'Select Verilog language generation for Icarus to use. Legal values are '
+             '"1995", "2001", "2001-noconfig", "2005", "2005-sv", "2009", or "2012". '
+             'See the corresponding "-g" flags in the Icarus manual for more information.',
+             field='help')
+
+    add_require_input(chip, 'input', 'rtl', 'netlist')
+    add_require_input(chip, 'input', 'rtl', 'verilog')
+    add_require_input(chip, 'input', 'rtl', 'systemverilog')
+    add_require_input(chip, 'input', 'cmdfile', 'f')
+    add_frontend_requires(chip, ['ydir', 'vlib', 'idir', 'define', 'libext'])
+
+    design = chip.top()
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.vvp', step=step, index=index)
+
+
+################################
+#  Custom runtime options
+################################
+def runtime_options(chip):
+
+    ''' Custom runtime options, returns list of command line options.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    cmdlist = []
+
+    design = chip.top()
+    cmdlist = ['-o', f'outputs/{design}.vvp']
+    cmdlist += ['-s', chip.top()]
+
+    verilog_gen = chip.get('tool', tool, 'task', task, 'var', 'verilog_generation',
+                           step=step, index=index)
+    if verilog_gen:
+        cmdlist.append(f'-g{verilog_gen[0]}')
+
+    opts = get_frontend_options(chip, ['ydir', 'vlib', 'idir', 'define', 'libext'])
+
+    for libext in opts['libext']:
+        cmdlist.append(f'-Y.{libext}')
+
+    # source files
+    for value in opts['ydir']:
+        cmdlist.append('-y ' + value)
+    for value in opts['vlib']:
+        cmdlist.append('-v ' + value)
+    for value in opts['idir']:
+        cmdlist.append('-I' + value)
+    for value in opts['define']:
+        cmdlist.append('-D' + value)
+    for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
+        cmdlist.append('-f ' + value)
+    for value in get_input_files(chip, 'input', 'rtl', 'netlist'):
+        cmdlist.append(value)
+    for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
+        cmdlist.append(value)
+    for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
+        cmdlist.append(value)
+
+    return cmdlist

siliconcompiler/tools/icarus/icarus.py

@@ -0,0 +1,36 @@
+
+'''
+Icarus is a verilog simulator with full support for Verilog
+IEEE-1364. Icarus can simulate synthesizable as well as
+behavioral Verilog.
+
+Documentation: https://steveicarus.github.io/iverilog/
+
+Sources: https://github.com/steveicarus/iverilog
+
+Installation: https://github.com/steveicarus/iverilog
+'''
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    from siliconcompiler.tools.icarus.compile import setup
+    setup(chip)
+    return chip
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # First line: Icarus Verilog version 10.1 (stable) ()
+    return stdout.split()[3]
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("icarus.json")

siliconcompiler/tools/icepack/bitstream.py

@@ -0,0 +1,20 @@
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Generate a bitstream for the ICE40 FPGA
+    '''
+    tool = 'icepack'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    clobber = False
+    design = chip.top()
+
+    chip.set('tool', tool, 'exe', tool)
+
+    chip.set('tool', tool, 'task', task, 'option', "", step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'input', f'{design}.asc', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.bit', step=step, index=index)

siliconcompiler/tools/icepack/icepack.py

@@ -0,0 +1,43 @@
+
+'''
+Icepack converts an ASCII bitstream file to a .bin file for the
+ICE40 FPGA.
+
+Documentation: https://clifford.at/icestorm
+
+Sources: https://github.com/YosysHQ/icestorm
+
+Installation: https://github.com/YosysHQ/icestorm
+'''
+
+
+#####################################################################
+# Make Docs
+#####################################################################
+def make_docs(chip):
+    from siliconcompiler.tools.icepack.bitstream import setup
+    setup(chip)
+    return chip
+
+
+################################
+#  Custom runtime options
+################################
+def runtime_options(chip):
+    ''' Custom runtime options, returnst list of command line options.
+    '''
+
+    topmodule = chip.top()
+
+    cmdlist = []
+    cmdlist.append("inputs/" + topmodule + ".asc")
+    cmdlist.append("outputs/" + topmodule + ".bit")
+
+    return cmdlist
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("icepack.json")

siliconcompiler/tools/klayout/export.py

@@ -0,0 +1,117 @@
+
+from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools.klayout.screenshot import setup_gui_screenshot
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools._common.asic import get_libraries
+
+
+def setup(chip):
+    '''
+    Generate a GDSII file from an input DEF file
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    tool = 'klayout'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+    clobber = False
+
+    script = 'klayout_export.py'
+    option = ['-z', '-nc', '-rx', '-r']
+    chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=clobber)
+
+    targetlibs = get_libraries(chip, 'logic')
+    stackup = chip.get('option', 'stackup')
+    pdk = chip.get('option', 'pdk')
+
+    # Set stream extension
+    streams = ('gds', 'oas')
+    chip.set('tool', tool, 'task', task, 'var', 'stream', 'gds',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'stream',
+             f'Extension to use for stream generation ({streams})',
+             field='help')
+    default_stream = chip.get('tool', tool, 'task', task, 'var', 'stream',
+                              step=step, index=index)[0]
+    sc_stream_order = [default_stream, *[s for s in streams if s != default_stream]]
+
+    if stackup and targetlibs:
+        macrolibs = get_libraries(chip, 'macro')
+
+        chip.add('tool', tool, 'task', task, 'require', ",".join(['asic', 'logiclib']),
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'require', ",".join(['option', 'stackup']),
+                 step=step, index=index)
+        req_set = False
+        for s in sc_stream_order:
+            if chip.valid('pdk', pdk, 'layermap', 'klayout', 'def', s, stackup):
+                chip.add('tool', tool, 'task', task, 'require',
+                         ",".join(['pdk', pdk, 'layermap', 'klayout', 'def', s, stackup]),
+                         step=step, index=index)
+                req_set = True
+                break
+        if not req_set:
+            # add default require
+            chip.add('tool', tool, 'task', task, 'require',
+                     ",".join(['pdk', pdk, 'layermap', 'klayout', 'def', 'klayout', stackup]),
+                     step=step, index=index)
+
+        for lib in (targetlibs + macrolibs):
+            lib_requires_stream = True
+            if chip.valid('library', lib, 'option', 'var', 'klayout_allow_missing_cell') and \
+               chip.get('library', lib, 'option', 'var', 'klayout_allow_missing_cell'):
+                lib_requires_stream = False
+            req_set = False
+            for s in sc_stream_order:
+                if chip.valid('library', lib, 'output', stackup, s):
+                    chip.add('tool', tool, 'task', task, 'require',
+                             ",".join(['library', lib, 'output', stackup, s]),
+                             step=step, index=index)
+                    req_set = True
+                    break
+            if not req_set and lib_requires_stream:
+                chip.add('tool', tool, 'task', task, 'require',
+                         ",".join(['library', lib, 'output', stackup, default_stream]),
+                         step=step, index=index)
+            chip.add('tool', tool, 'task', task, 'require',
+                     ",".join(['library', lib, 'output', stackup, 'lef']),
+                     step=step, index=index)
+    else:
+        chip.error('Stackup and targetlib parameters required for Klayout.')
+
+    # Input/Output requirements for default flow
+    design = chip.top()
+    if design + '.def' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.def',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,layout,def',
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.{default_stream}',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.lyt',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.lyp',
+             step=step, index=index)
+
+    # Export GDS with timestamps by default.
+    chip.set('tool', tool, 'task', task, 'var', 'timestamps', 'true',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'timestamps',
+             'Export GDSII with timestamps',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'var', 'screenshot', 'true',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'screenshot',
+             'true/false: true will cause KLayout to generate a screenshot of the layout',
+             field='help')
+
+    if chip.get('tool', tool, 'task', task, 'var', 'screenshot',
+                step=step, index=index) == ['true']:
+        setup_gui_screenshot(chip, require_input=False)

siliconcompiler/tools/klayout/klayout.py

@@ -0,0 +1,119 @@
+
+'''
+Klayout is a production grade viewer and editor of GDSII and
+Oasis data with customizable Python and Ruby interfaces.
+
+Documentation: https://www.klayout.de
+
+Sources: https://github.com/KLayout/klayout
+
+Installation: https://www.klayout.de/build.html
+'''
+
+import os
+from pathlib import Path
+import platform
+import shutil
+from siliconcompiler.tools._common import get_tool_task
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    chip.load_target("freepdk45_demo")
+
+
+####################################################################
+# Setup tool
+####################################################################
+def setup(chip, mode="batch"):
+    '''
+    Setup function for Klayout
+    '''
+
+    tool = 'klayout'
+    refdir = 'tools/' + tool
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+    clobber = False
+
+    klayout_exe = 'klayout'
+    if chip.get('option', 'scheduler', 'name', step=step, index=index) != 'docker':
+        if platform.system() == 'Windows':
+            klayout_exe = 'klayout_app.exe'
+            if not shutil.which(klayout_exe):
+                loc_dir = os.path.join(Path.home(), 'AppData', 'Roaming', 'KLayout')
+                global_dir = os.path.join(os.path.splitdrive(Path.home())[0],
+                                          os.path.sep,
+                                          'Program Files (x86)',
+                                          'KLayout')
+                if os.path.isdir(loc_dir):
+                    chip.set('tool', tool, 'path', loc_dir)
+                elif os.path.isdir(global_dir):
+                    chip.set('tool', tool, 'path', global_dir)
+        elif platform.system() == 'Darwin':
+            klayout_exe = 'klayout'
+            if not shutil.which(klayout_exe):
+                klayout_dir = os.path.join(os.path.sep,
+                                           'Applications',
+                                           'klayout.app',
+                                           'Contents',
+                                           'MacOS')
+                # different install directory when installed using Homebrew
+                klayout_brew_dir = os.path.join(os.path.sep,
+                                                'Applications',
+                                                'KLayout',
+                                                'klayout.app',
+                                                'Contents',
+                                                'MacOS')
+                if os.path.isdir(klayout_dir):
+                    chip.set('tool', tool, 'path', klayout_dir)
+                elif os.path.isdir(klayout_brew_dir):
+                    chip.set('tool', tool, 'path', klayout_brew_dir)
+
+    # common to all
+    chip.set('tool', tool, 'exe', klayout_exe)
+    chip.set('tool', tool, 'vswitch', ['-zz', '-v'])
+    chip.set('tool', tool, 'version', '>=0.28.0', clobber=clobber)
+    chip.set('tool', tool, 'format', 'json', clobber=clobber)
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
+             package='siliconcompiler', clobber=clobber)
+
+    if chip.get('option', 'nodisplay'):
+        # Tells QT to use the offscreen platform if nodisplay is used
+        chip.set('tool', tool, 'task', task, 'env', 'QT_QPA_PLATFORM', 'offscreen',
+                 step=step, index=index)
+
+    # Log file parsing
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'(WARNING|warning)',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'ERROR',
+             step=step, index=index, clobber=False)
+
+
+def runtime_options(chip):
+    # Provide KLayout with path to SC package so the driver can import the
+    # schema package directly. Since KL may be using a different Python
+    # environment than the user, it needs to import the limited Schema class
+    # that has no 3rd-party dependencies.
+    # This must be done at runtime to work in a remote context.
+
+    return ['-rd', f'SC_ROOT={chip.scroot}']
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # KLayout 0.26.11
+    return stdout.split()[1]
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("klayout.json")