siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/klayout/screenshot.py

@@ -0,0 +1,98 @@
+from siliconcompiler.tools.klayout import klayout
+from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools.klayout.show import general_gui_setup
+from siliconcompiler.tools.klayout.show import pre_process as show_pre_process
+from siliconcompiler.tools._common import get_tool_task
+
+
+def make_docs(chip):
+    klayout.make_docs(chip)
+    chip.set('tool', 'klayout', 'task', 'screenshot', 'var', 'show_filepath', '<path>')
+
+
+def setup(chip):
+    '''
+    Generate a PNG file from a layout file
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    tool = 'klayout'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+    clobber = False
+
+    setup_gui_screenshot(chip)
+
+    option = ['-nc', '-z', '-rm']
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=clobber)
+
+
+def pre_process(chip):
+    show_pre_process(chip)
+
+
+def setup_gui_screenshot(chip, require_input=True):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    general_gui_setup(chip, task, True, require_input=require_input)
+
+    chip.set('tool', tool, 'task', task, 'var', 'show_horizontal_resolution', '4096',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'show_vertical_resolution', '4096',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'xbins', '1',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'ybins', '1',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'margin', '10',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'linewidth', '0',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'oversampling', '2',
+             step=step, index=index, clobber=False)
+
+    # Help
+    chip.set('tool', tool, 'task', task, 'var', 'show_horizontal_resolution',
+             'Horizontal resolution in pixels',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'show_vertical_resolution',
+             'Vertical resolution in pixels',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'var', 'xbins',
+             'If greater than 1, splits the image into multiple segments along x-axis',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'ybins',
+             'If greater than 1, splits the image into multiple segments along y-axis',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'margin',
+             'Margin around design in microns',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'linewidth',
+             'Width of lines in detailed screenshots',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'oversampling',
+             'Image oversampling used in detailed screenshots',
+             field='help')
+
+    xbins = int(chip.get('tool', tool, 'task', task, 'var', 'xbins',
+                         step=step, index=index)[0])
+    ybins = int(chip.get('tool', tool, 'task', task, 'var', 'ybins',
+                         step=step, index=index)[0])
+
+    if xbins == 1 and ybins == 1:
+        chip.add('tool', tool, 'task', task, 'output', design + '.png',
+                 step=step, index=index)
+    else:
+        for x in range(xbins):
+            for y in range(ybins):
+                chip.add('tool', tool, 'task', task, 'output', f'{design}_X{x}_Y{y}.png',
+                         step=step, index=index)

siliconcompiler/tools/klayout/show.py

@@ -0,0 +1,101 @@
+import os
+import shutil
+
+from siliconcompiler.tools.klayout import klayout
+from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools._common import find_incoming_ext, get_tool_task
+
+
+def make_docs(chip):
+    klayout.make_docs(chip)
+    chip.set('tool', 'klayout', 'task', 'show', 'var', 'show_filepath', '<path>')
+
+
+def general_gui_setup(chip, task, exit, require_input=True):
+    # Generic tool setup.
+    setup_tool(chip)
+
+    tool = 'klayout'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    clobber = False
+
+    script = 'klayout_show.py'
+    chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+    if chip.valid('pdk', pdk, 'var', 'klayout', 'hide_layers', stackup):
+        layers_to_hide = chip.get('pdk', pdk, 'var', 'klayout', 'hide_layers', stackup)
+        chip.add('tool', tool, 'task', task, 'var', 'hide_layers', layers_to_hide,
+                 step=step, index=index)
+
+    if chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+       chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'show_filepath']),
+                 step=step, index=index)
+    elif require_input:
+        incoming_ext = find_incoming_ext(chip, ('gds', 'oas', 'def'), 'def')
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'show_filetype']),
+                 step=step, index=index)
+        chip.set('tool', tool, 'task', task, 'var', 'show_filetype', incoming_ext,
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'input', f'{chip.top()}.{incoming_ext}',
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit', "true" if exit else "false",
+             step=step, index=index, clobber=False)
+
+    # Help
+    chip.set('tool', tool, 'task', task, 'var', 'hide_layers',
+             'List of layers to hide',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'show_filepath',
+             'File to open',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'show_filetype',
+             'File type to look for in the inputs',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit',
+             'true/false: true will cause kLayout to exit when complete',
+             field='help')
+
+
+def setup(chip):
+    '''
+    Show a layout in kLayout
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    general_gui_setup(chip, task, False)
+
+    tool = 'klayout'
+    clobber = False
+
+    option = ['-nc', '-rm']
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=clobber)
+
+
+def pre_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+       chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        show_file = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',
+                             step=step, index=index)[0]
+
+        rel_path = os.path.dirname(show_file)
+        for ext in ('lyt', 'lyp'):
+            ext_file = os.path.join(rel_path, f'{chip.top()}.{ext}')
+            if ext_file and os.path.exists(ext_file):
+                shutil.copy2(ext_file, f"inputs/{chip.top()}.{ext}")

siliconcompiler/tools/magic/drc.py

@@ -0,0 +1,49 @@
+import re
+
+from siliconcompiler.tools.magic.magic import setup as setup_tool
+from siliconcompiler import sc_open
+from siliconcompiler.tools._common import get_tool_task, record_metric
+
+
+def setup(chip):
+    '''
+    Perform DRC checks
+    '''
+
+    # Generic tool setup
+    setup_tool(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.drc.mag', step=step, index=index)
+
+
+################################
+# Post_process (post executable)
+################################
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+
+    Reads error count from output and fills in appropriate entry in metrics
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    design = chip.top()
+
+    report_path = f'reports/{design}.drc'
+    drcs = 0
+    with sc_open(report_path) as f:
+        for line in f:
+            errors = re.search(r'^\[INFO\]: COUNT: (\d+)', line)
+
+            if errors:
+                drcs = errors.group(1)
+    record_metric(chip, step, index, 'drcs', drcs, report_path)
+
+    # TODO: return error code
+    return 0

siliconcompiler/tools/magic/extspice.py

@@ -0,0 +1,19 @@
+from siliconcompiler.tools.magic.magic import setup as setup_tool
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Extract spice netlists from a GDS file for simulation use
+    '''
+
+    # Generic tool setup
+    setup_tool(chip)
+
+    tool = 'magic'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.spice', step=step, index=index)

siliconcompiler/tools/magic/magic.py

@@ -0,0 +1,85 @@
+'''
+Magic is a chip layout viewer, editor, and circuit verifier with
+built in DRC and LVS engines.
+
+Documentation: http://opencircuitdesign.com/magic/userguide.html
+
+Installation: https://github.com/RTimothyEdwards/magic
+
+Sources: https://github.com/RTimothyEdwards/magic
+'''
+
+import os
+from siliconcompiler.tools._common import input_provides, get_tool_task
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    chip.load_target("freepdk45_demo")
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    ''' Setup function for 'magic' tool
+    '''
+
+    tool = 'magic'
+    refdir = 'tools/' + tool
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # magic used for drc and lvs
+    # if step not in ('drc', 'extspice'):
+    #    raise ValueError(f"Magic tool doesn't support step {step}.")
+    script = 'sc_magic.tcl'
+
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=8.3.196', clobber=False)
+    chip.set('tool', tool, 'format', 'tcl')
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'script', script,
+             step=step, index=index, clobber=False)
+
+    # set options
+    options = []
+    options.append('-noc')
+    options.append('-dnull')
+    chip.set('tool', tool, 'task', task, 'option', options, step=step, index=index, clobber=False)
+
+    design = chip.top()
+    if f'{design}.gds' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.gds', step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['input', 'layout', 'gds']),
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'^Error',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'warning',
+             step=step, index=index, clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    return stdout.strip('\n')
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("magic.json")

siliconcompiler/tools/magic/sc_drc.tcl

@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+source ./sc_manifest.tcl
+
+set sc_step    [sc_cfg_get arg step]
+set sc_index   [sc_cfg_get arg index]
+set sc_task    $sc_step
+
+set sc_design    [sc_top]
+set sc_macrolibs [sc_get_asic_libraries macro]
+set sc_stackup   [sc_cfg_get option stackup]
+
+if { [sc_cfg_tool_task_exists var exclude] } {
+    set sc_exclude [sc_cfg_tool_task_get var exclude]
+} else {
+    set sc_exclude [list]
+}
+
+# Ignore specific libraries by reading their LEFs (causes magic to abstract them)
+foreach lib $sc_macrolibs {
+    puts $lib
+    if { [lsearch -exact $sc_exclude $lib] >= 0 } {
+        lef read [sc_cfg_get library $lib output $sc_stackup lef]
+    }
+}
+
+gds noduplicates true
+
+if { [file exists "inputs/$sc_design.gds"] } {
+    set gds_path "inputs/$sc_design.gds"
+} else {
+    set gds_path [sc_cfg_get input layout gds]
+}
+
+gds read $gds_path
+puts $sc_design.gds
+set fout [open reports/$sc_design.drc w]
+set oscale [cif scale out]
+set cell_name $sc_design
+magic::suspendall
+puts stdout "\[INFO\]: Loading ${sc_design}\n"
+flush stdout
+load $sc_design
+select top cell
+drc euclidean on
+drc style drc(full)
+drc check
+set drcresult [drc listall why]
+set count 0
+puts $fout "$sc_design"
+puts $fout "----------------------------------------"
+foreach {errtype coordlist} $drcresult {
+    puts $fout $errtype
+    puts $fout "----------------------------------------"
+    foreach coord $coordlist {
+        set bllx [expr { $oscale * [lindex $coord 0] }]
+        set blly [expr { $oscale * [lindex $coord 1] }]
+        set burx [expr { $oscale * [lindex $coord 2] }]
+        set bury [expr { $oscale * [lindex $coord 3] }]
+        set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+        puts $fout "$coords"
+        incr count
+    }
+    puts $fout "----------------------------------------"
+}
+
+puts $fout "\[INFO\]: COUNT: $count"
+puts $fout "\[INFO\]: Should be divided by 3 or 4"
+
+puts $fout ""
+close $fout
+
+puts stdout "\[INFO\]: COUNT: $count"
+puts stdout "\[INFO\]: Should be divided by 3 or 4"
+puts stdout "\[INFO\]: DRC Checking DONE (outputs/${sc_design}.drc)"
+flush stdout
+
+puts stdout "\[INFO\]: Saving mag view with DRC errors(outputs/${sc_design}.drc.mag)"
+# WARNING: changes the name of the cell; keep as last step
+save outputs/${sc_design}.drc.mag
+puts stdout "\[INFO\]: Saved"
+
+exit 0

siliconcompiler/tools/magic/sc_extspice.tcl

@@ -0,0 +1,54 @@
+source ./sc_manifest.tcl
+
+set sc_step    [sc_cfg_get arg step]
+set sc_index   [sc_cfg_get arg index]
+set sc_task    $sc_step
+
+set sc_design [sc_top]
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_mainlib [lindex $sc_logiclibs 0]
+set sc_stackup [sc_cfg_get option stackup]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_libtype [sc_cfg_get library $sc_mainlib asic libarch]
+set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech magic $sc_stackup $sc_libtype lef]
+set sc_liblef [sc_cfg_get library $sc_mainlib output $sc_stackup lef]
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+if { [sc_cfg_tool_task_exists var exclude] } {
+    set sc_exclude [sc_cfg_tool_task_get var exclude]
+} else {
+    set sc_exclude [list]
+}
+
+lef read $sc_techlef
+lef read $sc_liblef
+
+# Ignore specific libraries by reading their LEFs (causes magic to abstract them)
+foreach lib $sc_macrolibs {
+    puts $lib
+    if { [lsearch -exact $sc_exclude $lib] >= 0 } {
+        lef read [sc_cfg_get library $lib output $sc_stackup lef]
+    }
+}
+
+if { [file exists "inputs/$sc_design.gds"] } {
+    set gds_path "inputs/$sc_design.gds"
+} else {
+    set gds_path [sc_cfg_get input layout gds]
+}
+
+gds noduplicates true
+gds read $gds_path
+
+# Extract layout to Spice netlist
+load $sc_design -dereference
+select top cell
+extract no all
+extract do local
+extract unique
+extract
+ext2spice lvs
+ext2spice ${sc_design}.ext -o outputs/$sc_design.spice
+feedback save extract_${sc_design}.log
+
+exit

siliconcompiler/tools/magic/sc_magic.tcl

@@ -0,0 +1,47 @@
+source ./sc_manifest.tcl
+
+set sc_stackup [sc_cfg_get option stackup]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_runset [sc_cfg_get pdk $sc_pdk drc runset magic $sc_stackup basic]
+
+# Put grid on 0.005 pitch.  This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if { [lindex $scalefac 1] < 2 } {
+    scalegrid 1 2
+}
+
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch { random seed }
+
+# loading technology
+tech load $sc_runset
+
+# set units to lambda grid
+snap lambda
+
+if { $sc_pdk == "skywater130" } {
+    # TODO: should not have process specific stuff here!
+
+    # set sky130 standard power, ground, and substrate names
+    set VDD VPWR
+    set GND VGND
+    set SUB VSUBS
+
+    # switch GDS input style to vendor variant, which ensures pins will be read
+    # correctly
+    cif istyle sky130(vendor)
+}
+
+set mydir      [file dirname [file normalize [info script]]]
+set sc_step    [sc_cfg_get arg step]
+
+if { [catch { source "$mydir/sc_${sc_step}.tcl" } err] } {
+    puts $err
+    exit 1
+}
+
+exit 0

siliconcompiler/tools/montage/montage.py

@@ -0,0 +1,30 @@
+
+'''
+ImageMagick® is a free and open-source software suite for displaying, converting, and editing raster
+image and vector image files.
+It can read and write over 200 image file formats, and can support a wide range of image
+manipulation operations, such as resizing, cropping, and color correction.
+Use the montage program to create a composite image by combining several separate images.
+The images are tiled on the composite image optionally adorned with a border, frame, image name,
+and more
+
+Documentation: https://imagemagick.org/
+
+Sources: https://github.com/ImageMagick/ImageMagick
+
+Installation: https://github.com/ImageMagick/ImageMagick
+'''
+
+
+def setup(chip):
+    exe = 'montage'
+
+    chip.set('tool', 'montage', 'exe', exe)
+    chip.set('tool', 'montage', 'vswitch', '-version')
+    chip.set('tool', 'montage', 'version', '>=6.9.0')
+
+
+def parse_version(stdout):
+    first_line = stdout.splitlines()[0]
+
+    return first_line.split(' ')[2]

siliconcompiler/tools/montage/tile.py

@@ -0,0 +1,66 @@
+from siliconcompiler.tools.montage import montage
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Tiles input images into a single output image.
+
+    Notes:
+    Need to make ensure that /etc/ImageMagick-6/policy.xml
+      <policy domain="resource" name="memory" value="8GiB"/>
+      <policy domain="resource" name="map" value="8GiB"/>
+      <policy domain="resource" name="width" value="32KP"/>
+      <policy domain="resource" name="height" value="32KP"/>
+      <policy domain="resource" name="area" value="1GP"/>
+      <policy domain="resource" name="disk" value="8GiB"/>
+    This ensures there are enough resources available to generate
+    the final image.
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    montage.setup(chip)
+
+    chip.set('tool', tool, 'task', task, 'var', 'xbins', '2',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'ybins', '2',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'xbins',
+             'Number of bins along the x-axis',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'ybins',
+             'Number of bins along the y-axis',
+             field='help')
+
+    xbins = int(chip.get('tool', tool, 'task', task, 'var', 'xbins',
+                         step=step, index=index)[0])
+    ybins = int(chip.get('tool', tool, 'task', task, 'var', 'ybins',
+                         step=step, index=index)[0])
+
+    for x in range(xbins):
+        for y in range(ybins):
+            chip.add('tool', tool, 'task', task, 'input', f'{design}_X{x}_Y{y}.png',
+                     step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.png',
+             step=step, index=index)
+
+    options = []
+
+    for y in range(ybins):
+        for x in range(xbins):
+            options.append(f'inputs/{design}_X{x}_Y{y}.png')
+
+    options.append('-tile')
+    options.append(f'{xbins}x{ybins}')
+    options.append('-geometry')
+    options.append('+0+0')
+    options.append(f'outputs/{design}.png')
+
+    chip.set('tool', tool, 'task', task, 'option', options,
+             step=step, index=index)