siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_procs.tcl

@@ -0,0 +1,423 @@
+#######################
+# Global Placement
+#######################
+
+proc sc_global_placement_density {} {
+  global openroad_gpl_padding
+  global openroad_gpl_place_density
+  global openroad_gpl_uniform_placement_adjustment
+
+  set or_uniform_density [gpl::get_global_placement_uniform_density \
+    -pad_left $openroad_gpl_padding \
+    -pad_right $openroad_gpl_padding]
+
+  # Small adder to ensure requested density is slightly over the uniform density
+  set or_adjust_density_adder 0.001
+
+  set selected_density $openroad_gpl_place_density
+
+  # User specified adjustment
+  if { $openroad_gpl_uniform_placement_adjustment > 0.0 } {
+    set or_uniform_adjusted_density \
+      [expr { $or_uniform_density + ((1.0 - $or_uniform_density) * \
+              $openroad_gpl_uniform_placement_adjustment) + $or_adjust_density_adder }]
+    if { $or_uniform_adjusted_density > 1.00 } {
+      utl::warn FLW 1 "Adjusted density exceeds 1.00 ([format %0.3f $or_uniform_adjusted_density]),\
+        reverting to use ($openroad_gpl_place_density) for global placement"
+      set selected_density $openroad_gpl_place_density
+    } else {
+      utl::info FLW 1 "Using computed density of ([format %0.3f $or_uniform_adjusted_density])\
+        for global placement"
+      set selected_density $or_uniform_adjusted_density
+    }
+  }
+
+  # Final selection
+  set or_uniform_zero_adjusted_density \
+    [expr { min($or_uniform_density + $or_adjust_density_adder, 1.0) }]
+
+  if { $selected_density < $or_uniform_density } {
+    utl::warn FLW 1 "Using computed density of ([format %0.3f $or_uniform_zero_adjusted_density])\
+      for global placement as [format %0.3f $selected_density] < [format %0.3f $or_uniform_density]"
+    set selected_density $or_uniform_zero_adjusted_density
+  }
+
+  return $selected_density
+}
+
+proc sc_global_placement { args } {
+  sta::parse_key_args "sc_global_placement" args \
+    keys {} \
+    flags {-skip_io -disable_routability_driven}
+  sta::check_argc_eq0 "sc_global_placement" $args
+
+  global openroad_gpl_routability_driven
+  global openroad_gpl_timing_driven
+  global openroad_gpl_padding
+
+  set openroad_gpl_args []
+  if { $openroad_gpl_routability_driven == "true" && \
+       ![info exists flags(-disable_routability_driven)] } {
+    lappend openroad_gpl_args "-routability_driven"
+  }
+  if { $openroad_gpl_timing_driven == "true" } {
+    lappend openroad_gpl_args "-timing_driven"
+  }
+
+  if { [info exists flags(-skip_io)] } {
+    lappend openroad_gpl_args "-skip_io"
+  }
+
+  global_placement {*}$openroad_gpl_args \
+    -density [sc_global_placement_density] \
+    -pad_left $openroad_gpl_padding \
+    -pad_right $openroad_gpl_padding
+}
+
+###########################
+# Detailed Placement
+###########################
+
+proc sc_detailed_placement {} {
+  global openroad_dpl_padding
+  global openroad_dpl_padding
+  global openroad_dpl_disallow_one_site
+  global openroad_dpl_max_displacement
+
+  set_placement_padding -global \
+    -left $openroad_dpl_padding \
+    -right $openroad_dpl_padding
+
+  set dpl_args []
+  if { $openroad_dpl_disallow_one_site == "true" } {
+    lappend dpl_args "-disallow_one_site_gaps"
+  }
+
+  detailed_placement -max_displacement $openroad_dpl_max_displacement \
+    {*}$dpl_args
+  check_placement -verbose
+}
+
+###########################
+# Pin Placement
+###########################
+
+proc sc_pin_placement { args } {
+  sta::parse_key_args "sc_pin_placement" args \
+    keys {} \
+    flags {-random}
+  sta::check_argc_eq0 "sc_pin_placement" $args
+
+  global sc_cfg
+  global sc_tool
+  global sc_task
+  global sc_hpinmetal
+  global sc_vpinmetal
+  global openroad_ppl_arguments
+
+  if { [sc_cfg_tool_task_exists var pin_thickness_h] } {
+    set h_mult [lindex [sc_cfg_tool_task_get var pin_thickness_h] 0]
+    set_pin_thick_multiplier -hor_multiplier $h_mult
+  }
+  if { [sc_cfg_tool_task_exists var pin_thickness_v] } {
+    set v_mult [lindex [sc_cfg_tool_task_get var pin_thickness_v] 0]
+    set_pin_thick_multiplier -ver_multiplier $v_mult
+  }
+  if { [sc_cfg_tool_task_exists {file} ppl_constraints] } {
+    foreach pin_constraint [sc_cfg_tool_task_get {file} ppl_constraints] {
+      puts "Sourcing pin constraints: ${pin_constraint}"
+      source $pin_constraint
+    }
+  }
+
+  set ppl_args []
+  if { [info exists flags(-random)] } {
+    lappend ppl_args "-random"
+  }
+
+  place_pins -hor_layers $sc_hpinmetal \
+    -ver_layers $sc_vpinmetal \
+    {*}$openroad_ppl_arguments \
+    {*}$ppl_args
+}
+
+###########################
+# Check if OR has a GUI
+###########################
+
+proc sc_has_gui {} {
+  return [gui::supported]
+}
+
+###########################
+# Check if design has placed instances
+###########################
+
+proc sc_has_placed_instances {} {
+  foreach inst [[ord::get_db_block] getInsts] {
+    if { [$inst isPlaced] } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Check if design has unplaced instances
+###########################
+
+proc sc_has_unplaced_instances {} {
+  foreach inst [[ord::get_db_block] getInsts] {
+    if { ![$inst isPlaced] } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Check if design has routing
+###########################
+
+proc sc_has_routing {} {
+  foreach net [[ord::get_db_block] getNets] {
+    if { [$net getWire] != "NULL" } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Check if design has global routing
+###########################
+
+proc sc_has_global_routing {} {
+  foreach net [[ord::get_db_block] getNets] {
+    if { [llength [$net getGuides]] != 0 } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Design has unplaced macros
+###########################
+
+# Function adapted from OpenROAD:
+# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/ca3004b85e0d4fbee3470115e63b83c498cfed85/flow/scripts/macro_place.tcl#L26
+proc sc_design_has_unplaced_macros {} {
+  foreach inst [[ord::get_db_block] getInsts] {
+    if { [$inst isBlock] && ![$inst isFixed] } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Design has unplaced pads
+###########################
+
+proc sc_design_has_unplaced_pads {} {
+  foreach inst [[ord::get_db_block] getInsts] {
+    if { [$inst isPad] && ![$inst isFixed] } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Design has placable IOs
+###########################
+
+proc sc_design_has_placeable_ios {} {
+  foreach bterm [[ord::get_db_block] getBTerms] {
+    if { [$bterm getFirstPinPlacementStatus] != "FIXED" &&
+         [$bterm getFirstPinPlacementStatus] != "LOCKED" } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Check if net has placed bpins
+###########################
+
+proc sc_bterm_has_placed_io { net } {
+  set net [[ord::get_db_block] findNet $net]
+
+  foreach bterm [$net getBTerms] {
+    if { [$bterm getFirstPinPlacementStatus] != "UNPLACED" } {
+      return true
+    }
+  }
+  return false
+}
+
+###########################
+# Find nets regex
+###########################
+
+proc sc_find_net_regex { net_name } {
+  set nets []
+
+  foreach net [[ord::get_db_block] getNets] {
+    if { [string match $net_name [$net getName]] } {
+      lappend nets [$net getName]
+    }
+  }
+
+  return $nets
+}
+
+###########################
+# Get supply nets in design
+###########################
+
+proc sc_supply_nets {} {
+  set nets []
+
+  foreach net [[ord::get_db_block] getNets] {
+    set type [$net getSigType]
+    if { $type == "POWER" || $type == "GROUND" } {
+      lappend nets [$net getName]
+    }
+  }
+
+  return $nets
+}
+
+###########################
+# Get nets for PSM to check
+###########################
+
+proc sc_psm_check_nets {} {
+  global openroad_psm_enable
+  global openroad_psm_skip_nets
+
+  if { $openroad_psm_enable == "true" } {
+    set psm_nets []
+
+    foreach net [sc_supply_nets] {
+      set skipped false
+      foreach skip_pattern $openroad_psm_skip_nets {
+        if { [string match $skip_pattern $net] } {
+          set skipped true
+          break
+        }
+      }
+      if { !$skipped } {
+        lappend psm_nets $net
+      }
+    }
+
+    return $psm_nets
+  }
+
+  return []
+}
+
+###########################
+# Save an image
+###########################
+
+proc sc_save_image { title path { pixels 1000 } } {
+  utl::info FLW 1 "Saving \"$title\" to $path"
+
+  save_image -resolution [sc_image_resolution $pixels] \
+    -area [sc_image_area] \
+    $path
+}
+
+###########################
+# Get the image bounding box
+###########################
+
+proc sc_image_area {} {
+  set box [[ord::get_db_block] getDieArea]
+  set width [$box dx]
+  set height [$box dy]
+
+  # apply 5% margin
+  set xmargin [expr { int(0.05 * $width) }]
+  set ymargin [expr { int(0.05 * $height) }]
+
+  set area []
+  lappend area [ord::dbu_to_microns [expr { [$box xMin] - $xmargin }]]
+  lappend area [ord::dbu_to_microns [expr { [$box yMin] - $ymargin }]]
+  lappend area [ord::dbu_to_microns [expr { [$box xMax] + $xmargin }]]
+  lappend area [ord::dbu_to_microns [expr { [$box yMax] + $ymargin }]]
+  return $area
+}
+
+###########################
+# Get the image resolution (um / pixel)
+###########################
+
+proc sc_image_resolution { pixels } {
+  set box [[ord::get_db_block] getDieArea]
+  return [expr { [ord::dbu_to_microns [$box maxDXDY]] / $pixels }]
+}
+
+###########################
+# Clear gui selections
+###########################
+
+proc sc_image_clear_selection {} {
+  gui::clear_highlights -1
+  gui::clear_selections
+}
+
+###########################
+# Setup default GUI setting for images
+###########################
+
+proc sc_image_setup_default {} {
+  gui::restore_display_controls
+
+  sc_image_clear_selection
+
+  gui::fit
+
+  # Setup initial visibility to avoid any previous settings
+  gui::set_display_controls "*" visible false
+  gui::set_display_controls "Layers/*" visible true
+  gui::set_display_controls "Nets/*" visible true
+  gui::set_display_controls "Instances/*" visible true
+  gui::set_display_controls "Shape Types/*" visible true
+  gui::set_display_controls "Misc/Instances/*" visible true
+  gui::set_display_controls "Misc/Instances/Pin Names" visible false
+  gui::set_display_controls "Misc/Scale bar" visible true
+  gui::set_display_controls "Misc/Highlight selected" visible true
+  gui::set_display_controls "Misc/Detailed view" visible true
+}
+
+###########################
+# Count the logic depth of the critical path
+###########################
+
+proc count_logic_depth {} {
+  set count 0
+  set paths [find_timing_paths -sort_by_slack]
+  if { [llength $paths] == 0 } {
+    return 0
+  }
+  set path_ref [[lindex $paths 0] path]
+  set pins [$path_ref pins]
+  foreach pin $pins {
+    if { [$pin is_driver] } {
+      incr count
+    }
+    set vertex [lindex [$pin vertices] 0]
+    # Stop at clock vertex
+    if { [$vertex is_clock] } {
+      break
+    }
+  }
+  # Subtract 1 to account for initial launch
+  return [expr { $count - 1 }]
+}

siliconcompiler/tools/openroad/scripts/sc_rcx.tcl

@@ -0,0 +1,63 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+##############################
+# Schema Helper functions
+###############################
+
+proc sc_get_layer_name { name } {
+  if { [ string is integer $name ] } {
+    set layer [[ord::get_db_tech] findRoutingLayer $name]
+    if { $layer == "NULL" } {
+      utl::error FLW 1 "$name is not a valid routing layer."
+    }
+    return [$layer getName]
+  }
+  return $name
+}
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_tool   openroad
+set sc_step   [sc_cfg_get arg step]
+set sc_index  [sc_cfg_get arg index]
+set sc_flow   [sc_cfg_get option flow]
+set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+# Design
+set sc_design     [sc_top]
+set sc_pdk        [sc_cfg_get option pdk]
+set sc_stackup    [sc_cfg_get option stackup]
+
+# Library
+set sc_libtype [lindex [sc_cfg_tool_task_get {var} libtype] 0]
+
+# PDK Design Rules
+set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype lef]
+
+set sc_threads [sc_cfg_tool_task_get threads]
+
+###############################
+# Read Files
+###############################
+
+# Read techlef
+puts "Reading tech LEF: $sc_techlef"
+read_lef $sc_techlef
+
+###############################
+# Run task
+###############################
+
+set_thread_count $sc_threads
+
+utl::set_metrics_stage "sc__step__{}"
+source -echo "${sc_refdir}/sc_${sc_task}.tcl"
+utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/sc_rcx_bench.tcl

@@ -0,0 +1,20 @@
+#https://github.com/The-OpenROAD-Project/OpenROAD/blob/9b52b1d9cfb532f9872739ffe482afb5ac9def92/src/rcx/calibration/script/generate_rules.tcl
+
+set openroad_bench_length \
+  [lindex [sc_cfg_tool_task_get {var} bench_length] 0]
+
+set sc_maxmetal \
+  [sc_get_layer_name [lindex [sc_cfg_tool_task_get {var} max_layer] 0]]
+set openroad_top_metal_number [[[ord::get_db_tech] findLayer $sc_maxmetal] getRoutingLevel]
+
+# Creates the patterns and
+# store it in the database
+bench_wires \
+  -len $openroad_bench_length \
+  -met_cnt $openroad_top_metal_number \
+  -all
+
+# Writes the verilog netlist
+# of the patterns
+bench_verilog "outputs/${sc_design}.vg"
+write_def "outputs/${sc_design}.def"

siliconcompiler/tools/openroad/scripts/sc_rcx_extract.tcl

@@ -0,0 +1,12 @@
+# https://github.com/The-OpenROAD-Project/OpenROAD/blob/9b52b1d9cfb532f9872739ffe482afb5ac9def92/src/rcx/calibration/script/generate_rules.tcl
+
+set openroad_corner [lindex [sc_cfg_tool_task_get {var} corner] 0]
+
+# Read the patterns design
+read_def "inputs/${sc_design}.def"
+
+# Read the parasitics of the patterns
+bench_read_spef "inputs/${sc_design}.${openroad_corner}.spef"
+
+# Convert the parasitics into openrcx format
+write_rules -db -file "outputs/${sc_design}.${openroad_corner}.rcx"

siliconcompiler/tools/openroad/scripts/sc_route.tcl

@@ -0,0 +1,133 @@
+##########################################################
+# ROUTING
+##########################################################
+
+#######################
+# Helper functions
+#######################
+
+proc insert_fillers {} {
+  upvar sc_filler sc_filler
+  if { $sc_filler != "" } {
+    filler_placement $sc_filler
+  }
+
+  check_placement -verbose
+
+  global_connect
+}
+
+#######################
+# Add Fillers
+#######################
+
+insert_fillers
+
+######################
+# Setup detailed route options
+######################
+
+foreach via $openroad_drt_default_vias {
+  utl::info FLW 1 "Marking $via a default routing via"
+  detailed_route_set_default_via $via
+}
+foreach layer $openroad_drt_unidirectional_layers {
+  utl::info FLW 1 "Marking $layer as a unidirectional routing layer"
+  detailed_route_set_unidirectional_layer $layer
+}
+
+######################
+# GLOBAL ROUTE
+######################
+
+# Pin access
+if { $openroad_grt_use_pin_access == "true" } {
+  set openroad_pin_access_args []
+  if { $openroad_drt_process_node != "false" } {
+    lappend openroad_pin_access_args "-db_process_node" $openroad_drt_process_node
+  }
+
+  pin_access -bottom_routing_layer $sc_minmetal \
+    -top_routing_layer $sc_maxmetal \
+    {*}$openroad_pin_access_args
+}
+
+set sc_grt_arguments []
+if { $openroad_grt_allow_congestion == "true" } {
+  lappend sc_grt_arguments "-allow_congestion"
+}
+if { $openroad_grt_allow_overflow == "true" } {
+  lappend sc_grt_arguments "-allow_overflow"
+}
+
+global_route -guide_file "./route.guide" \
+  -congestion_iterations $openroad_grt_overflow_iter \
+  -congestion_report_file "reports/${sc_design}_congestion.rpt" \
+  -verbose \
+  {*}$sc_grt_arguments
+
+######################
+# Report and Repair Antennas
+######################
+
+estimate_parasitics -global_routing
+if { $openroad_ant_check == "true" && \
+     [check_antennas -report_file "reports/${sc_design}_antenna.rpt"] != 0 } {
+  if { $openroad_ant_repair == "true" && \
+       [llength [sc_cfg_get library $sc_mainlib asic cells antenna]] != 0 } {
+    set sc_antenna [lindex [sc_cfg_get library $sc_mainlib asic cells antenna] 0]
+
+    # Remove filler cells before attempting to repair antennas
+    remove_fillers
+
+    repair_antenna $sc_antenna \
+      -iterations $openroad_ant_iterations \
+      -ratio_margin $openroad_ant_margin
+
+    # Add filler cells back
+    insert_fillers
+
+    # Check antennas again to get final report
+    check_antennas -report_file "reports/${sc_design}_antenna_post_repair.rpt"
+  }
+}
+
+######################
+# Detailed Route
+######################
+
+set openroad_drt_arguments []
+if { $openroad_drt_disable_via_gen == "true" } {
+  lappend openroad_drt_arguments "-disable_via_gen"
+}
+if { $openroad_drt_process_node != "" } {
+  lappend openroad_drt_arguments "-db_process_node" $openroad_drt_process_node
+}
+if { $openroad_drt_via_in_pin_bottom_layer != "" } {
+  lappend openroad_drt_arguments "-via_in_pin_bottom_layer" $openroad_drt_via_in_pin_bottom_layer
+}
+if { $openroad_drt_via_in_pin_top_layer != "" } {
+  lappend openroad_drt_arguments "-via_in_pin_top_layer" $openroad_drt_via_in_pin_top_layer
+}
+if { $openroad_drt_repair_pdn_vias != "" } {
+  lappend openroad_drt_arguments "-repair_pdn_vias" $openroad_drt_repair_pdn_vias
+}
+
+detailed_route -save_guide_updates \
+  -output_drc "reports/${sc_design}_drc.rpt" \
+  -output_maze "reports/${sc_design}_maze.log" \
+  -bottom_routing_layer $sc_minmetal \
+  -top_routing_layer $sc_maxmetal \
+  -verbose 1 \
+  {*}$openroad_drt_arguments
+
+#########################
+# Correct violations with the power grid
+#########################
+
+if { $openroad_drt_via_repair_post_route == "true" } {
+  repair_pdn_vias -all
+}
+
+# estimate for metrics
+estimate_parasitics -global_routing

siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl

@@ -0,0 +1,21 @@
+gui::save_display_controls
+
+set sc_resolution \
+  [lindex [sc_cfg_tool_task_get {var} show_vertical_resolution] 0]
+
+# Show the drc markers (if any)
+if { [file exists reports/${sc_design}_drc.rpt] } {
+  gui::load_drc reports/${sc_design}_drc.rpt
+}
+
+sc_image_setup_default
+
+sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution
+
+gui::restore_display_controls
+
+if { [sc_cfg_tool_task_exists {var} include_report_images] &&
+     [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
+     == "true" } {
+  source -echo "${sc_refdir}/sc_write_images.tcl"
+}

siliconcompiler/tools/openroad/scripts/sc_write.tcl

@@ -0,0 +1,5 @@
+write_db "outputs/${sc_design}.odb"
+write_sdc "outputs/${sc_design}.sdc"
+
+write_def "outputs/${sc_design}.def"
+write_verilog -include_pwr_gnd "outputs/${sc_design}.vg"