siliconcompiler 0.26.5__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/__init__.py +24 -0
- siliconcompiler/__main__.py +12 -0
- siliconcompiler/_common.py +49 -0
- siliconcompiler/_metadata.py +36 -0
- siliconcompiler/apps/__init__.py +0 -0
- siliconcompiler/apps/_common.py +76 -0
- siliconcompiler/apps/sc.py +92 -0
- siliconcompiler/apps/sc_dashboard.py +94 -0
- siliconcompiler/apps/sc_issue.py +178 -0
- siliconcompiler/apps/sc_remote.py +199 -0
- siliconcompiler/apps/sc_server.py +39 -0
- siliconcompiler/apps/sc_show.py +142 -0
- siliconcompiler/apps/smake.py +232 -0
- siliconcompiler/checklists/__init__.py +0 -0
- siliconcompiler/checklists/oh_tapeout.py +41 -0
- siliconcompiler/core.py +3221 -0
- siliconcompiler/data/RobotoMono/LICENSE.txt +202 -0
- siliconcompiler/data/RobotoMono/RobotoMono-Regular.ttf +0 -0
- siliconcompiler/data/heartbeat.v +18 -0
- siliconcompiler/data/logo.png +0 -0
- siliconcompiler/flowgraph.py +570 -0
- siliconcompiler/flows/__init__.py +0 -0
- siliconcompiler/flows/_common.py +67 -0
- siliconcompiler/flows/asicflow.py +180 -0
- siliconcompiler/flows/asictopflow.py +38 -0
- siliconcompiler/flows/dvflow.py +86 -0
- siliconcompiler/flows/fpgaflow.py +202 -0
- siliconcompiler/flows/generate_openroad_rcx.py +66 -0
- siliconcompiler/flows/lintflow.py +35 -0
- siliconcompiler/flows/screenshotflow.py +51 -0
- siliconcompiler/flows/showflow.py +59 -0
- siliconcompiler/flows/signoffflow.py +53 -0
- siliconcompiler/flows/synflow.py +128 -0
- siliconcompiler/fpgas/__init__.py +0 -0
- siliconcompiler/fpgas/lattice_ice40.py +42 -0
- siliconcompiler/fpgas/vpr_example.py +109 -0
- siliconcompiler/issue.py +300 -0
- siliconcompiler/libs/__init__.py +0 -0
- siliconcompiler/libs/asap7sc7p5t.py +8 -0
- siliconcompiler/libs/gf180mcu.py +8 -0
- siliconcompiler/libs/nangate45.py +8 -0
- siliconcompiler/libs/sky130hd.py +8 -0
- siliconcompiler/libs/sky130io.py +8 -0
- siliconcompiler/package.py +412 -0
- siliconcompiler/pdks/__init__.py +0 -0
- siliconcompiler/pdks/asap7.py +8 -0
- siliconcompiler/pdks/freepdk45.py +8 -0
- siliconcompiler/pdks/gf180.py +8 -0
- siliconcompiler/pdks/skywater130.py +8 -0
- siliconcompiler/remote/__init__.py +36 -0
- siliconcompiler/remote/client.py +891 -0
- siliconcompiler/remote/schema.py +106 -0
- siliconcompiler/remote/server.py +507 -0
- siliconcompiler/remote/server_schema/requests/cancel_job.json +51 -0
- siliconcompiler/remote/server_schema/requests/check_progress.json +61 -0
- siliconcompiler/remote/server_schema/requests/check_server.json +38 -0
- siliconcompiler/remote/server_schema/requests/delete_job.json +51 -0
- siliconcompiler/remote/server_schema/requests/get_results.json +48 -0
- siliconcompiler/remote/server_schema/requests/remote_run.json +40 -0
- siliconcompiler/remote/server_schema/responses/cancel_job.json +18 -0
- siliconcompiler/remote/server_schema/responses/check_progress.json +30 -0
- siliconcompiler/remote/server_schema/responses/check_server.json +32 -0
- siliconcompiler/remote/server_schema/responses/delete_job.json +18 -0
- siliconcompiler/remote/server_schema/responses/get_results.json +21 -0
- siliconcompiler/remote/server_schema/responses/remote_run.json +25 -0
- siliconcompiler/report/__init__.py +13 -0
- siliconcompiler/report/html_report.py +74 -0
- siliconcompiler/report/report.py +355 -0
- siliconcompiler/report/streamlit_report.py +137 -0
- siliconcompiler/report/streamlit_viewer.py +944 -0
- siliconcompiler/report/summary_image.py +117 -0
- siliconcompiler/report/summary_table.py +105 -0
- siliconcompiler/report/utils.py +163 -0
- siliconcompiler/scheduler/__init__.py +2092 -0
- siliconcompiler/scheduler/docker_runner.py +253 -0
- siliconcompiler/scheduler/run_node.py +138 -0
- siliconcompiler/scheduler/send_messages.py +178 -0
- siliconcompiler/scheduler/slurm.py +208 -0
- siliconcompiler/scheduler/validation/email_credentials.json +54 -0
- siliconcompiler/schema/__init__.py +7 -0
- siliconcompiler/schema/schema_cfg.py +4014 -0
- siliconcompiler/schema/schema_obj.py +1841 -0
- siliconcompiler/schema/utils.py +93 -0
- siliconcompiler/sphinx_ext/__init__.py +0 -0
- siliconcompiler/sphinx_ext/dynamicgen.py +1006 -0
- siliconcompiler/sphinx_ext/schemagen.py +221 -0
- siliconcompiler/sphinx_ext/utils.py +166 -0
- siliconcompiler/targets/__init__.py +0 -0
- siliconcompiler/targets/asap7_demo.py +68 -0
- siliconcompiler/targets/asic_demo.py +38 -0
- siliconcompiler/targets/fpgaflow_demo.py +47 -0
- siliconcompiler/targets/freepdk45_demo.py +59 -0
- siliconcompiler/targets/gf180_demo.py +77 -0
- siliconcompiler/targets/skywater130_demo.py +70 -0
- siliconcompiler/templates/email/general.j2 +66 -0
- siliconcompiler/templates/email/summary.j2 +43 -0
- siliconcompiler/templates/issue/README.txt +26 -0
- siliconcompiler/templates/issue/run.sh +6 -0
- siliconcompiler/templates/report/bootstrap.min.css +7 -0
- siliconcompiler/templates/report/bootstrap.min.js +7 -0
- siliconcompiler/templates/report/bootstrap_LICENSE.md +24 -0
- siliconcompiler/templates/report/sc_report.j2 +427 -0
- siliconcompiler/templates/slurm/run.sh +9 -0
- siliconcompiler/templates/tcl/manifest.tcl.j2 +137 -0
- siliconcompiler/tools/__init__.py +0 -0
- siliconcompiler/tools/_common/__init__.py +432 -0
- siliconcompiler/tools/_common/asic.py +115 -0
- siliconcompiler/tools/_common/sdc/sc_constraints.sdc +76 -0
- siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl +63 -0
- siliconcompiler/tools/bambu/bambu.py +32 -0
- siliconcompiler/tools/bambu/convert.py +77 -0
- siliconcompiler/tools/bluespec/bluespec.py +40 -0
- siliconcompiler/tools/bluespec/convert.py +103 -0
- siliconcompiler/tools/builtin/_common.py +155 -0
- siliconcompiler/tools/builtin/builtin.py +26 -0
- siliconcompiler/tools/builtin/concatenate.py +85 -0
- siliconcompiler/tools/builtin/join.py +27 -0
- siliconcompiler/tools/builtin/maximum.py +46 -0
- siliconcompiler/tools/builtin/minimum.py +57 -0
- siliconcompiler/tools/builtin/mux.py +70 -0
- siliconcompiler/tools/builtin/nop.py +38 -0
- siliconcompiler/tools/builtin/verify.py +83 -0
- siliconcompiler/tools/chisel/SCDriver.scala +10 -0
- siliconcompiler/tools/chisel/build.sbt +27 -0
- siliconcompiler/tools/chisel/chisel.py +37 -0
- siliconcompiler/tools/chisel/convert.py +140 -0
- siliconcompiler/tools/execute/exec_input.py +41 -0
- siliconcompiler/tools/execute/execute.py +17 -0
- siliconcompiler/tools/genfasm/bitstream.py +61 -0
- siliconcompiler/tools/genfasm/genfasm.py +40 -0
- siliconcompiler/tools/ghdl/convert.py +87 -0
- siliconcompiler/tools/ghdl/ghdl.py +41 -0
- siliconcompiler/tools/icarus/compile.py +87 -0
- siliconcompiler/tools/icarus/icarus.py +36 -0
- siliconcompiler/tools/icepack/bitstream.py +20 -0
- siliconcompiler/tools/icepack/icepack.py +43 -0
- siliconcompiler/tools/klayout/export.py +117 -0
- siliconcompiler/tools/klayout/klayout.py +119 -0
- siliconcompiler/tools/klayout/klayout_export.py +205 -0
- siliconcompiler/tools/klayout/klayout_operations.py +363 -0
- siliconcompiler/tools/klayout/klayout_show.py +242 -0
- siliconcompiler/tools/klayout/klayout_utils.py +176 -0
- siliconcompiler/tools/klayout/operations.py +194 -0
- siliconcompiler/tools/klayout/screenshot.py +98 -0
- siliconcompiler/tools/klayout/show.py +101 -0
- siliconcompiler/tools/magic/drc.py +49 -0
- siliconcompiler/tools/magic/extspice.py +19 -0
- siliconcompiler/tools/magic/magic.py +85 -0
- siliconcompiler/tools/magic/sc_drc.tcl +96 -0
- siliconcompiler/tools/magic/sc_extspice.tcl +54 -0
- siliconcompiler/tools/magic/sc_magic.tcl +47 -0
- siliconcompiler/tools/montage/montage.py +30 -0
- siliconcompiler/tools/montage/tile.py +66 -0
- siliconcompiler/tools/netgen/count_lvs.py +132 -0
- siliconcompiler/tools/netgen/lvs.py +90 -0
- siliconcompiler/tools/netgen/netgen.py +36 -0
- siliconcompiler/tools/netgen/sc_lvs.tcl +46 -0
- siliconcompiler/tools/nextpnr/apr.py +24 -0
- siliconcompiler/tools/nextpnr/nextpnr.py +59 -0
- siliconcompiler/tools/openfpgaloader/openfpgaloader.py +39 -0
- siliconcompiler/tools/openroad/__init__.py +0 -0
- siliconcompiler/tools/openroad/cts.py +45 -0
- siliconcompiler/tools/openroad/dfm.py +66 -0
- siliconcompiler/tools/openroad/export.py +131 -0
- siliconcompiler/tools/openroad/floorplan.py +70 -0
- siliconcompiler/tools/openroad/openroad.py +977 -0
- siliconcompiler/tools/openroad/physyn.py +27 -0
- siliconcompiler/tools/openroad/place.py +41 -0
- siliconcompiler/tools/openroad/rcx_bench.py +95 -0
- siliconcompiler/tools/openroad/rcx_extract.py +34 -0
- siliconcompiler/tools/openroad/route.py +45 -0
- siliconcompiler/tools/openroad/screenshot.py +60 -0
- siliconcompiler/tools/openroad/scripts/sc_apr.tcl +499 -0
- siliconcompiler/tools/openroad/scripts/sc_cts.tcl +64 -0
- siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +20 -0
- siliconcompiler/tools/openroad/scripts/sc_export.tcl +98 -0
- siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +413 -0
- siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +158 -0
- siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +7 -0
- siliconcompiler/tools/openroad/scripts/sc_place.tcl +84 -0
- siliconcompiler/tools/openroad/scripts/sc_procs.tcl +423 -0
- siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +63 -0
- siliconcompiler/tools/openroad/scripts/sc_rcx_bench.tcl +20 -0
- siliconcompiler/tools/openroad/scripts/sc_rcx_extract.tcl +12 -0
- siliconcompiler/tools/openroad/scripts/sc_route.tcl +133 -0
- siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +21 -0
- siliconcompiler/tools/openroad/scripts/sc_write.tcl +5 -0
- siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +361 -0
- siliconcompiler/tools/openroad/show.py +94 -0
- siliconcompiler/tools/openroad/templates/pex.tcl +8 -0
- siliconcompiler/tools/opensta/__init__.py +101 -0
- siliconcompiler/tools/opensta/report_libraries.py +28 -0
- siliconcompiler/tools/opensta/scripts/sc_procs.tcl +47 -0
- siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl +74 -0
- siliconcompiler/tools/opensta/scripts/sc_timing.tcl +268 -0
- siliconcompiler/tools/opensta/timing.py +214 -0
- siliconcompiler/tools/slang/__init__.py +49 -0
- siliconcompiler/tools/slang/lint.py +101 -0
- siliconcompiler/tools/surelog/__init__.py +123 -0
- siliconcompiler/tools/surelog/parse.py +183 -0
- siliconcompiler/tools/surelog/templates/output.v +7 -0
- siliconcompiler/tools/sv2v/convert.py +46 -0
- siliconcompiler/tools/sv2v/sv2v.py +37 -0
- siliconcompiler/tools/template/template.py +125 -0
- siliconcompiler/tools/verilator/compile.py +139 -0
- siliconcompiler/tools/verilator/lint.py +19 -0
- siliconcompiler/tools/verilator/parse.py +27 -0
- siliconcompiler/tools/verilator/verilator.py +172 -0
- siliconcompiler/tools/vivado/__init__.py +7 -0
- siliconcompiler/tools/vivado/bitstream.py +21 -0
- siliconcompiler/tools/vivado/place.py +21 -0
- siliconcompiler/tools/vivado/route.py +21 -0
- siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl +6 -0
- siliconcompiler/tools/vivado/scripts/sc_place.tcl +2 -0
- siliconcompiler/tools/vivado/scripts/sc_route.tcl +4 -0
- siliconcompiler/tools/vivado/scripts/sc_run.tcl +45 -0
- siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl +25 -0
- siliconcompiler/tools/vivado/syn_fpga.py +20 -0
- siliconcompiler/tools/vivado/vivado.py +147 -0
- siliconcompiler/tools/vpr/_json_constraint.py +63 -0
- siliconcompiler/tools/vpr/_xml_constraint.py +109 -0
- siliconcompiler/tools/vpr/place.py +137 -0
- siliconcompiler/tools/vpr/route.py +124 -0
- siliconcompiler/tools/vpr/screenshot.py +54 -0
- siliconcompiler/tools/vpr/show.py +88 -0
- siliconcompiler/tools/vpr/vpr.py +357 -0
- siliconcompiler/tools/xyce/xyce.py +36 -0
- siliconcompiler/tools/yosys/lec.py +56 -0
- siliconcompiler/tools/yosys/prepareLib.py +59 -0
- siliconcompiler/tools/yosys/sc_lec.tcl +84 -0
- siliconcompiler/tools/yosys/sc_syn.tcl +79 -0
- siliconcompiler/tools/yosys/syn_asic.py +565 -0
- siliconcompiler/tools/yosys/syn_asic.tcl +377 -0
- siliconcompiler/tools/yosys/syn_asic_fpga_shared.tcl +31 -0
- siliconcompiler/tools/yosys/syn_fpga.py +146 -0
- siliconcompiler/tools/yosys/syn_fpga.tcl +233 -0
- siliconcompiler/tools/yosys/syn_strategies.tcl +81 -0
- siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v +39 -0
- siliconcompiler/tools/yosys/templates/abc.const +2 -0
- siliconcompiler/tools/yosys/yosys.py +147 -0
- siliconcompiler/units.py +259 -0
- siliconcompiler/use.py +177 -0
- siliconcompiler/utils/__init__.py +423 -0
- siliconcompiler/utils/asic.py +158 -0
- siliconcompiler/utils/showtools.py +25 -0
- siliconcompiler-0.26.5.dist-info/LICENSE +190 -0
- siliconcompiler-0.26.5.dist-info/METADATA +195 -0
- siliconcompiler-0.26.5.dist-info/RECORD +251 -0
- siliconcompiler-0.26.5.dist-info/WHEEL +5 -0
- siliconcompiler-0.26.5.dist-info/entry_points.txt +12 -0
- siliconcompiler-0.26.5.dist-info/top_level.txt +1 -0
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from siliconcompiler.tools.verilator.verilator import setup as setup_tool
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from siliconcompiler.tools.verilator.verilator import runtime_options as runtime_options_tool
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from siliconcompiler.tools._common import get_input_files, get_tool_task
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def setup(chip):
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'''
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Compiles Verilog and C/C++ sources into an executable. In addition to the
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standard RTL inputs, this task reads C/C++ sources from :keypath:`input,
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hll, c`. Outputs an executable in ``outputs/<design>.vexe``.
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This task supports using the :keypath:`option, trace` parameter to enable
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Verilator's ``--trace`` flag.
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'''
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# Generic tool setup.
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setup_tool(chip)
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tool = 'verilator'
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step = chip.get('arg', 'step')
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index = chip.get('arg', 'index')
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_, task = get_tool_task(chip, step, index)
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design = chip.top()
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chip.add('tool', tool, 'task', task, 'require', 'input,hll,c', step=step, index=index)
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chip.set('tool', tool, 'task', task, 'output', f'{design}.vexe', step=step, index=index)
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# var defaults
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chip.set('tool', tool, 'task', task, 'var', 'mode', 'cc', clobber=False, step=step, index=index)
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chip.set('tool', tool, 'task', task, 'var', 'trace', False, clobber=False,
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step=step, index=index)
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chip.set('tool', tool, 'task', task, 'var', 'trace_type', 'vcd', clobber=False,
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step=step, index=index)
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mode = chip.get('tool', tool, 'task', task, 'var', 'mode', step=step, index=index)
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if mode not in (['cc'], ['systemc']):
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chip.error(f"Invalid mode {mode} provided to verilator/compile. Expected one of 'cc' or "
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"'systemc'")
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trace_type = chip.get('tool', tool, 'task', task, 'var', 'trace_type', step=step, index=index)
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if trace_type not in (['vcd'], ['fst']):
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chip.error(f"Invalid trace type {trace_type} provided to verilator/compile. Expected "
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"one of 'vcd' or 'fst'.")
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chip.set('tool', tool, 'task', task, 'var', 'cflags',
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'flags to provide to the C++ compiler invoked by Verilator',
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field='help')
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chip.set('tool', tool, 'task', task, 'var', 'ldflags',
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'flags to provide to the linker invoked by Verilator',
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field='help')
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chip.set('tool', tool, 'task', task, 'var', 'pins_bv',
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'controls datatypes used to represent SystemC inputs/outputs. See --pins-bv in '
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'Verilator docs for more info.',
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field='help')
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chip.set('tool', tool, 'task', task, 'var', 'mode',
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"defines compilation mode for Verilator. Valid options are 'cc' for C++, or 'systemc' "
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"for SystemC.",
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field='help')
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chip.set('tool', tool, 'task', task, 'dir', 'cincludes',
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'include directories to provide to the C++ compiler invoked by Verilator',
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field='help')
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chip.set('tool', tool, 'task', task, 'var', 'trace',
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"if true, enables trace generation.",
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field='help')
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chip.set('tool', tool, 'task', task, 'var', 'trace_type',
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"specifies type of wave file to create when [option, trace] is set. Valid options are "
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"'vcd' or 'fst'. Defaults to 'vcd'.",
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field='help')
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def runtime_options(chip):
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tool = 'verilator'
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step = chip.get('arg', 'step')
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index = chip.get('arg', 'index')
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_, task = get_tool_task(chip, step, index)
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design = chip.top()
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cmdlist = runtime_options_tool(chip)
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cmdlist.extend(['--exe', '--build'])
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threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
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cmdlist.extend(['-j', str(threads)])
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mode = chip.get('tool', tool, 'task', task, 'var', 'mode', step=step, index=index)
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if mode == ['cc']:
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cmdlist.append('--cc')
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elif mode == ['systemc']:
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cmdlist.append('--sc')
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pins_bv = chip.get('tool', tool, 'task', task, 'var', 'pins_bv', step=step, index=index)
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if pins_bv:
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cmdlist.extend(['--pins-bv', pins_bv[0]])
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cmdlist.extend(['-o', f'../outputs/{design}.vexe'])
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c_flags = chip.get('tool', tool, 'task', task, 'var', 'cflags', step=step, index=index)
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c_includes = chip.find_files('tool', tool, 'task', task, 'dir', 'cincludes',
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step=step, index=index)
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if chip.get('tool', tool, 'task', task, 'var', 'trace', step=step, index=index)[0] == 'true':
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trace_type = chip.get('tool', tool, 'task', task, 'var', 'trace_type',
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step=step, index=index)
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if trace_type == ['vcd']:
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ext = 'vcd'
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trace_opt = '--trace'
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elif trace_type == ['fst']:
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ext = 'fst'
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trace_opt = '--trace-fst'
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+
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+
cmdlist.append(trace_opt)
|
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+
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# add siliconcompiler specific defines
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c_flags.append("-DSILICONCOMPILER_TRACE_DIR=\\\"reports\\\"")
|
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+
c_flags.append(f"-DSILICONCOMPILER_TRACE_FILE=\\\"reports/{design}.{ext}\\\"")
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+
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if c_includes:
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+
c_flags.extend([f'-I{include}' for include in c_includes])
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+
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if c_flags:
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cflags_str = ' '.join(c_flags)
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+
cmdlist.extend(['-CFLAGS', f'"{cflags_str}"'])
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+
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+
ld_flags = chip.get('tool', tool, 'task', task, 'var', 'ldflags', step=step, index=index)
|
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+
if ld_flags:
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ldflags_str = ' '.join(ld_flags)
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+
cmdlist.extend(['-LDFLAGS', f'"{ldflags_str}"'])
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+
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+
for value in get_input_files(chip, 'input', 'hll', 'c'):
|
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+
cmdlist.append(value)
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+
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+
return cmdlist
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@@ -0,0 +1,19 @@
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1
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+
from siliconcompiler.tools.verilator.verilator import setup as setup_tool
|
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2
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+
from siliconcompiler.tools.verilator.verilator import runtime_options as runtime_options_tool
|
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3
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+
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4
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+
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5
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+
def setup(chip):
|
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6
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+
'''
|
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7
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+
Lints Verilog source. Results of linting can be programmatically queried
|
|
8
|
+
using errors/warnings metrics.
|
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9
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+
'''
|
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10
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+
|
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11
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+
# Generic tool setup.
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+
setup_tool(chip)
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+
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+
|
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+
def runtime_options(chip):
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+
cmdlist = runtime_options_tool(chip)
|
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+
cmdlist.append('--lint-only')
|
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+
cmdlist.append('--no-timing')
|
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+
return cmdlist
|
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@@ -0,0 +1,27 @@
|
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1
|
+
from siliconcompiler.tools.verilator.verilator import setup as setup_tool
|
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2
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+
from siliconcompiler.tools.verilator.verilator import runtime_options as runtime_options_tool
|
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3
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+
from siliconcompiler.tools._common import get_tool_task
|
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4
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+
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5
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+
|
|
6
|
+
def setup(chip):
|
|
7
|
+
'''
|
|
8
|
+
Lints Verilog source. Results of linting can be programmatically queried
|
|
9
|
+
using errors/warnings metrics.
|
|
10
|
+
'''
|
|
11
|
+
|
|
12
|
+
# Generic tool setup.
|
|
13
|
+
setup_tool(chip)
|
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14
|
+
|
|
15
|
+
step = chip.get('arg', 'step')
|
|
16
|
+
index = chip.get('arg', 'index')
|
|
17
|
+
tool, task = get_tool_task(chip, step, index)
|
|
18
|
+
|
|
19
|
+
chip.set('tool', tool, 'task', task, 'output', f'{chip.top()}.v',
|
|
20
|
+
step=step, index=index)
|
|
21
|
+
|
|
22
|
+
|
|
23
|
+
def runtime_options(chip):
|
|
24
|
+
cmdlist = runtime_options_tool(chip)
|
|
25
|
+
cmdlist.append('--xml-only')
|
|
26
|
+
cmdlist.append('--no-timing')
|
|
27
|
+
return cmdlist
|
|
@@ -0,0 +1,172 @@
|
|
|
1
|
+
'''
|
|
2
|
+
Verilator is a free and open-source software tool which converts Verilog (a
|
|
3
|
+
hardware description language) to a cycle-accurate behavioral model in C++
|
|
4
|
+
or SystemC.
|
|
5
|
+
|
|
6
|
+
All Verilator tasks may consume input either from a single pickled Verilog file
|
|
7
|
+
(``inputs/<design>.v``) generated by a preceding task, or if that file does not
|
|
8
|
+
exist, through the following keypaths:
|
|
9
|
+
|
|
10
|
+
* :keypath:`input, rtl, verilog`
|
|
11
|
+
* :keypath:`input, cmdfile, f`
|
|
12
|
+
* :keypath:`option, ydir`
|
|
13
|
+
* :keypath:`option, vlib`
|
|
14
|
+
* :keypath:`option, idir`
|
|
15
|
+
|
|
16
|
+
For all tasks, this driver runs Verilator using the ``-sv`` switch to enable
|
|
17
|
+
parsing a subset of SystemVerilog features. All tasks also support using
|
|
18
|
+
:keypath:`option, relax` to make warnings nonfatal.
|
|
19
|
+
|
|
20
|
+
Documentation: https://verilator.org/guide/latest
|
|
21
|
+
|
|
22
|
+
Sources: https://github.com/verilator/verilator
|
|
23
|
+
|
|
24
|
+
Installation: https://verilator.org/guide/latest/install.html
|
|
25
|
+
'''
|
|
26
|
+
|
|
27
|
+
import os
|
|
28
|
+
from siliconcompiler.tools._common import (
|
|
29
|
+
add_frontend_requires,
|
|
30
|
+
get_frontend_options,
|
|
31
|
+
add_require_input,
|
|
32
|
+
get_input_files,
|
|
33
|
+
get_tool_task,
|
|
34
|
+
input_provides
|
|
35
|
+
)
|
|
36
|
+
|
|
37
|
+
|
|
38
|
+
####################################################################
|
|
39
|
+
# Make Docs
|
|
40
|
+
####################################################################
|
|
41
|
+
def make_docs(chip):
|
|
42
|
+
chip.load_target("freepdk45_demo")
|
|
43
|
+
|
|
44
|
+
|
|
45
|
+
def setup(chip):
|
|
46
|
+
''' Per tool function that returns a dynamic options string based on
|
|
47
|
+
the dictionary settings. Static settings only.
|
|
48
|
+
'''
|
|
49
|
+
|
|
50
|
+
tool = 'verilator'
|
|
51
|
+
step = chip.get('arg', 'step')
|
|
52
|
+
index = chip.get('arg', 'index')
|
|
53
|
+
_, task = get_tool_task(chip, step, index)
|
|
54
|
+
|
|
55
|
+
# Basic Tool Setup
|
|
56
|
+
chip.set('tool', tool, 'exe', 'verilator')
|
|
57
|
+
chip.set('tool', tool, 'vswitch', '--version')
|
|
58
|
+
chip.set('tool', tool, 'version', '>=4.034', clobber=False)
|
|
59
|
+
|
|
60
|
+
# Common to all tasks
|
|
61
|
+
# Max threads
|
|
62
|
+
chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
|
|
63
|
+
step=step, index=index, clobber=False)
|
|
64
|
+
|
|
65
|
+
# Basic warning and error grep check on logfile
|
|
66
|
+
chip.set('tool', tool, 'task', task, 'regex', 'warnings', r"^\%Warning",
|
|
67
|
+
step=step, index=index, clobber=False)
|
|
68
|
+
chip.set('tool', tool, 'task', task, 'regex', 'errors', r"^\%Error",
|
|
69
|
+
step=step, index=index, clobber=False)
|
|
70
|
+
|
|
71
|
+
chip.set('tool', tool, 'task', task, 'file', 'config',
|
|
72
|
+
'Verilator configuration file',
|
|
73
|
+
field='help')
|
|
74
|
+
|
|
75
|
+
chip.set('tool', tool, 'task', task, 'var', 'enable_assert',
|
|
76
|
+
'true/false, when true assertions are enabled in Verilator.',
|
|
77
|
+
field='help')
|
|
78
|
+
chip.set('tool', tool, 'task', task, 'var', 'enable_assert', 'false',
|
|
79
|
+
step=step, index=index, clobber=False)
|
|
80
|
+
|
|
81
|
+
if f'{chip.top()}.v' not in input_provides(chip, step, index):
|
|
82
|
+
add_require_input(chip, 'input', 'rtl', 'verilog')
|
|
83
|
+
add_require_input(chip, 'input', 'rtl', 'systemverilog')
|
|
84
|
+
add_require_input(chip, 'input', 'cmdfile', 'f')
|
|
85
|
+
add_frontend_requires(chip, ['ydir', 'vlib', 'idir', 'libext', 'param', 'define'])
|
|
86
|
+
|
|
87
|
+
|
|
88
|
+
def runtime_options(chip):
|
|
89
|
+
cmdlist = []
|
|
90
|
+
tool = 'verilator'
|
|
91
|
+
step = chip.get('arg', 'step')
|
|
92
|
+
index = chip.get('arg', 'index')
|
|
93
|
+
_, task = get_tool_task(chip, step, index)
|
|
94
|
+
|
|
95
|
+
design = chip.top()
|
|
96
|
+
|
|
97
|
+
has_input = os.path.isfile(f'inputs/{design}.v')
|
|
98
|
+
opts_supports = ['param', 'libext']
|
|
99
|
+
if not has_input:
|
|
100
|
+
opts_supports.extend(['ydir', 'vlib', 'idir', 'define'])
|
|
101
|
+
|
|
102
|
+
frontend_opts = get_frontend_options(chip, opts_supports)
|
|
103
|
+
|
|
104
|
+
# Even though most of these don't need to be set in runtime_options() in order for the driver to
|
|
105
|
+
# function properly, setting all the CLI options here facilitates a user using ['tool', <tool>,
|
|
106
|
+
# 'task', <task>, 'option'] to supply additional CLI flags.
|
|
107
|
+
|
|
108
|
+
cmdlist.append('-sv')
|
|
109
|
+
cmdlist.extend(['--top-module', design])
|
|
110
|
+
|
|
111
|
+
assertions = chip.get('tool', tool, 'task', task, 'var',
|
|
112
|
+
'enable_assert', step=step, index=index)
|
|
113
|
+
if assertions == ['true']:
|
|
114
|
+
cmdlist.append('--assert')
|
|
115
|
+
|
|
116
|
+
# Converting user setting to verilator specific filter
|
|
117
|
+
for warning in chip.get('tool', tool, 'task', task, 'warningoff', step=step, index=index):
|
|
118
|
+
cmdlist.append(f'-Wno-{warning}')
|
|
119
|
+
|
|
120
|
+
libext = frontend_opts['libext']
|
|
121
|
+
if libext:
|
|
122
|
+
libext_option = f"+libext+.{'+.'.join(libext)}"
|
|
123
|
+
cmdlist.append(libext_option)
|
|
124
|
+
|
|
125
|
+
# Verilator docs recommend this file comes first in CLI arguments
|
|
126
|
+
for value in chip.find_files('tool', tool, 'task', task, 'file', 'config',
|
|
127
|
+
step=step, index=index):
|
|
128
|
+
cmdlist.append(value)
|
|
129
|
+
|
|
130
|
+
for param, value in frontend_opts['param']:
|
|
131
|
+
cmdlist.append(f'-G{param}={value}')
|
|
132
|
+
|
|
133
|
+
if os.path.isfile(f'inputs/{design}.v'):
|
|
134
|
+
cmdlist.append(f'inputs/{design}.v')
|
|
135
|
+
else:
|
|
136
|
+
for value in frontend_opts['ydir']:
|
|
137
|
+
cmdlist.append(f'-y {value}')
|
|
138
|
+
for value in frontend_opts['vlib']:
|
|
139
|
+
cmdlist.append(f'-v {value}')
|
|
140
|
+
for value in frontend_opts['idir']:
|
|
141
|
+
cmdlist.append(f'-I{value}')
|
|
142
|
+
for value in frontend_opts['define']:
|
|
143
|
+
if value == "VERILATOR":
|
|
144
|
+
# Verilator auto defines this and will error if it is defined twice.
|
|
145
|
+
continue
|
|
146
|
+
cmdlist.append(f'-D{value}')
|
|
147
|
+
for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
|
|
148
|
+
cmdlist.append(value)
|
|
149
|
+
for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
|
|
150
|
+
cmdlist.append(value)
|
|
151
|
+
|
|
152
|
+
for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
|
|
153
|
+
cmdlist.append(f'-f {value}')
|
|
154
|
+
|
|
155
|
+
return cmdlist
|
|
156
|
+
|
|
157
|
+
|
|
158
|
+
################################
|
|
159
|
+
# Version Check
|
|
160
|
+
################################
|
|
161
|
+
|
|
162
|
+
|
|
163
|
+
def parse_version(stdout):
|
|
164
|
+
# Verilator 4.104 2020-11-14 rev v4.104
|
|
165
|
+
return stdout.split()[1]
|
|
166
|
+
|
|
167
|
+
|
|
168
|
+
##################################################
|
|
169
|
+
if __name__ == "__main__":
|
|
170
|
+
|
|
171
|
+
chip = make_docs()
|
|
172
|
+
chip.write_manifest("verilator.csv")
|
|
@@ -0,0 +1,21 @@
|
|
|
1
|
+
from siliconcompiler.tools import vivado
|
|
2
|
+
from siliconcompiler.tools.vivado import tool
|
|
3
|
+
from siliconcompiler.tools._common import get_tool_task
|
|
4
|
+
|
|
5
|
+
|
|
6
|
+
def setup(chip):
|
|
7
|
+
'''Generates bitstream of implemented design.'''
|
|
8
|
+
step = chip.get('arg', 'step')
|
|
9
|
+
index = chip.get('arg', 'index')
|
|
10
|
+
_, task = get_tool_task(chip, step, index)
|
|
11
|
+
vivado.setup_task(chip, task)
|
|
12
|
+
|
|
13
|
+
design = chip.top()
|
|
14
|
+
chip.set('tool', tool, 'task', task, 'input', f'{design}_checkpoint.dcp',
|
|
15
|
+
step=step, index=index)
|
|
16
|
+
chip.set('tool', tool, 'task', task, 'output', f'{design}.bit',
|
|
17
|
+
step=step, index=index)
|
|
18
|
+
|
|
19
|
+
|
|
20
|
+
def post_process(chip):
|
|
21
|
+
vivado.post_process(chip)
|
|
@@ -0,0 +1,21 @@
|
|
|
1
|
+
from siliconcompiler.tools import vivado
|
|
2
|
+
from siliconcompiler.tools.vivado import tool
|
|
3
|
+
from siliconcompiler.tools._common import get_tool_task
|
|
4
|
+
|
|
5
|
+
|
|
6
|
+
def setup(chip):
|
|
7
|
+
'''Performs placement.'''
|
|
8
|
+
step = chip.get('arg', 'step')
|
|
9
|
+
index = chip.get('arg', 'index')
|
|
10
|
+
_, task = get_tool_task(chip, step, index)
|
|
11
|
+
vivado.setup_task(chip, task)
|
|
12
|
+
|
|
13
|
+
design = chip.top()
|
|
14
|
+
chip.set('tool', tool, 'task', task, 'input', f'{design}_checkpoint.dcp',
|
|
15
|
+
step=step, index=index)
|
|
16
|
+
chip.set('tool', tool, 'task', task, 'output', f'{design}_checkpoint.dcp',
|
|
17
|
+
step=step, index=index)
|
|
18
|
+
|
|
19
|
+
|
|
20
|
+
def post_process(chip):
|
|
21
|
+
vivado.post_process(chip)
|
|
@@ -0,0 +1,21 @@
|
|
|
1
|
+
from siliconcompiler.tools import vivado
|
|
2
|
+
from siliconcompiler.tools.vivado import tool
|
|
3
|
+
from siliconcompiler.tools._common import get_tool_task
|
|
4
|
+
|
|
5
|
+
|
|
6
|
+
def setup(chip):
|
|
7
|
+
'''Performs routing.'''
|
|
8
|
+
step = chip.get('arg', 'step')
|
|
9
|
+
index = chip.get('arg', 'index')
|
|
10
|
+
_, task = get_tool_task(chip, step, index)
|
|
11
|
+
vivado.setup_task(chip, task)
|
|
12
|
+
|
|
13
|
+
design = chip.top()
|
|
14
|
+
chip.set('tool', tool, 'task', task, 'input', f'{design}_checkpoint.dcp',
|
|
15
|
+
step=step, index=index)
|
|
16
|
+
chip.set('tool', tool, 'task', task, 'output', f'{design}_checkpoint.dcp',
|
|
17
|
+
step=step, index=index)
|
|
18
|
+
|
|
19
|
+
|
|
20
|
+
def post_process(chip):
|
|
21
|
+
vivado.post_process(chip)
|
|
@@ -0,0 +1,45 @@
|
|
|
1
|
+
|
|
2
|
+
###############################
|
|
3
|
+
# Reading SC Schema
|
|
4
|
+
###############################
|
|
5
|
+
|
|
6
|
+
source ./sc_manifest.tcl
|
|
7
|
+
|
|
8
|
+
##############################
|
|
9
|
+
# Schema Adapter
|
|
10
|
+
##############################
|
|
11
|
+
|
|
12
|
+
set sc_design [sc_top]
|
|
13
|
+
if { [sc_cfg_exists input fpga xdc] } {
|
|
14
|
+
set sc_constraint [sc_cfg_get input fpga xdc]
|
|
15
|
+
} else {
|
|
16
|
+
set sc_constraint ""
|
|
17
|
+
}
|
|
18
|
+
set sc_tool "vivado"
|
|
19
|
+
set sc_partname [sc_cfg_get fpga partname]
|
|
20
|
+
set sc_step [sc_cfg_get arg step]
|
|
21
|
+
set sc_index [sc_cfg_get arg index]
|
|
22
|
+
set sc_flow [sc_cfg_get option flow]
|
|
23
|
+
set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
|
|
24
|
+
set sc_refdir [sc_cfg_tool_task_get refdir]
|
|
25
|
+
|
|
26
|
+
source $sc_refdir/sc_$sc_task.tcl
|
|
27
|
+
|
|
28
|
+
##############################
|
|
29
|
+
# Checkpoint
|
|
30
|
+
##############################
|
|
31
|
+
|
|
32
|
+
write_checkpoint -force "outputs/${sc_design}_checkpoint"
|
|
33
|
+
|
|
34
|
+
##############################
|
|
35
|
+
# Reports / Metrics
|
|
36
|
+
##############################
|
|
37
|
+
|
|
38
|
+
report_timing_summary -file "reports/timing_summary.rpt"
|
|
39
|
+
report_timing -sort_by group -max_paths 100 -path_type summary -file "reports/timing.rpt"
|
|
40
|
+
report_utilization -file "reports/total_utilization.rpt"
|
|
41
|
+
report_clock_utilization -file "reports/clock_utilization.rpt"
|
|
42
|
+
report_drc -file "reports/drc.rpt"
|
|
43
|
+
report_cdc -details -file "reports/cdc.rpt"
|
|
44
|
+
|
|
45
|
+
report_design_analysis -qor_summary -json "qor_summary.json"
|
|
@@ -0,0 +1,25 @@
|
|
|
1
|
+
# set up project
|
|
2
|
+
create_project $sc_design -force
|
|
3
|
+
set_property part $sc_partname [current_project]
|
|
4
|
+
set_property target_language Verilog [current_project]
|
|
5
|
+
|
|
6
|
+
# add imported files
|
|
7
|
+
if { [string equal [get_filesets -quiet sources_1] ""] } {
|
|
8
|
+
create_fileset -srcset sources_1
|
|
9
|
+
}
|
|
10
|
+
add_files -norecurse -fileset [get_filesets sources_1] "inputs/$sc_design.v"
|
|
11
|
+
set_property top $sc_design [current_fileset]
|
|
12
|
+
|
|
13
|
+
# add constraints
|
|
14
|
+
if { $sc_constraint != "" } {
|
|
15
|
+
if { [string equal [get_filesets -quiet constrs_1] ""] } {
|
|
16
|
+
create_fileset -constrset constrs_1
|
|
17
|
+
}
|
|
18
|
+
foreach item $sc_constraint {
|
|
19
|
+
add_files -norecurse -fileset [current_fileset] $item
|
|
20
|
+
}
|
|
21
|
+
}
|
|
22
|
+
|
|
23
|
+
# run synthesis
|
|
24
|
+
synth_design -top $sc_design
|
|
25
|
+
opt_design
|
|
@@ -0,0 +1,20 @@
|
|
|
1
|
+
from siliconcompiler.tools import vivado
|
|
2
|
+
from siliconcompiler.tools.vivado import tool
|
|
3
|
+
from siliconcompiler.tools._common import get_tool_task
|
|
4
|
+
|
|
5
|
+
|
|
6
|
+
def setup(chip):
|
|
7
|
+
'''Performs FPGA synthesis.'''
|
|
8
|
+
step = chip.get('arg', 'step')
|
|
9
|
+
index = chip.get('arg', 'index')
|
|
10
|
+
_, task = get_tool_task(chip, step, index)
|
|
11
|
+
vivado.setup_task(chip, task)
|
|
12
|
+
|
|
13
|
+
design = chip.top()
|
|
14
|
+
chip.set('tool', tool, 'task', task, 'input', f'{design}.v', step=step, index=index)
|
|
15
|
+
chip.set('tool', tool, 'task', task, 'output', f'{design}_checkpoint.dcp',
|
|
16
|
+
step=step, index=index)
|
|
17
|
+
|
|
18
|
+
|
|
19
|
+
def post_process(chip):
|
|
20
|
+
vivado.post_process(chip)
|