siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_write_images.tcl

@@ -0,0 +1,361 @@
+# Adopted from https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3f9740e6b3643835e918d78ae1d377d65af0f0fb/flow/scripts/save_images.tcl
+
+proc sc_image_heatmap { name ident image_name title { allow_bin_adjust 1 } } {
+  global openroad_ord_heatmap_bins_x
+  global openroad_ord_heatmap_bins_y
+
+  file mkdir reports/images/heatmap
+
+  gui::set_heatmap $ident ShowLegend 1
+  gui::set_heatmap $ident ShowNumbers 1
+
+  if { $allow_bin_adjust } {
+    set heatmap_xn $openroad_ord_heatmap_bins_x
+    set heatmap_yn $openroad_ord_heatmap_bins_y
+
+    if { $heatmap_xn < 1 } {
+      set heatmap_xn 1
+    }
+    if { $heatmap_yn < 1 } {
+      set heatmap_yn 1
+    }
+
+    set min_heatmap_bin 1.0
+    set max_heatmap_bin 100.0
+
+    set box [[ord::get_db_block] getDieArea]
+    set heatmap_x [expr { [ord::dbu_to_microns [$box dx]] / $heatmap_xn }]
+    set heatmap_y [expr { [ord::dbu_to_microns [$box dy]] / $heatmap_yn }]
+
+    if { $heatmap_x < $min_heatmap_bin } {
+      set heatmap_x $min_heatmap_bin
+    } elseif { $heatmap_x > $max_heatmap_bin } {
+      set heatmap_x $max_heatmap_bin
+    }
+    if { $heatmap_y < $min_heatmap_bin } {
+      set heatmap_y $min_heatmap_bin
+    } elseif { $heatmap_y > $max_heatmap_bin } {
+      set heatmap_y $max_heatmap_bin
+    }
+    gui::set_heatmap $ident GridX $heatmap_x
+    gui::set_heatmap $ident GridY $heatmap_y
+  }
+
+  gui::set_heatmap $ident rebuild
+
+  if { ![gui::get_heatmap_bool $ident has_data] } {
+    return
+  }
+
+  gui::set_display_controls "Heat Maps/${name}" visible true
+
+  sc_save_image "$title heatmap" reports/images/heatmap/${image_name}
+
+  gui::set_display_controls "Heat Maps/${name}" visible false
+}
+
+proc sc_image_placement {} {
+  if { ![sc_has_placed_instances] } {
+    return
+  }
+
+  global sc_design
+
+  sc_image_setup_default
+
+  # The placement view without routing
+  gui::set_display_controls "Layers/*" visible false
+  gui::set_display_controls "Instances/Physical/*" visible false
+
+  sc_save_image "placement" reports/images/${sc_design}.placement.png
+}
+
+proc sc_image_routing {} {
+  if { ![sc_has_routing] } {
+    return
+  }
+
+  global sc_design
+
+  sc_image_setup_default
+
+  gui::set_display_controls "Nets/Power" visible false
+  gui::set_display_controls "Nets/Ground" visible false
+
+  sc_save_image "routing" reports/images/${sc_design}.routing.png
+}
+
+proc sc_image_everything {} {
+  global sc_design
+
+  sc_image_setup_default
+  sc_save_image "snapshot" reports/images/${sc_design}.png
+}
+
+proc sc_image_irdrop { net corner } {
+  if { ![sc_has_placed_instances] || [sc_has_unplaced_instances] } {
+    return
+  }
+
+  sc_image_setup_default
+
+  file mkdir reports/images/heatmap/irdrop
+
+  # suppress error message related to failed analysis,
+  # that is okay, we just won't take a screenshot
+  set msgs "38 39 69"
+  foreach msg $msgs {
+    suppress_message PSM $msg
+  }
+  set failed [catch { analyze_power_grid -net $net -corner $corner -source_type STRAPS } err]
+  foreach msg $msgs {
+    unsuppress_message PSM $msg
+  }
+  if { $failed } {
+    utl::warn FLW 1 "Unable to generate IR drop heatmap for $net on $corner"
+    return
+  }
+
+  foreach layer [[ord::get_db_tech] getLayers] {
+    if { [$layer getRoutingLevel] == 0 } {
+      continue
+    }
+    set layer_name [$layer getName]
+
+    gui::set_heatmap IRDrop Net $net
+    gui::set_heatmap IRDrop Corner $corner
+    gui::set_heatmap IRDrop Layer $layer_name
+    gui::set_heatmap IRDrop rebuild
+
+    sc_image_heatmap "IR Drop" \
+      "IRDrop" \
+      "irdrop/${net}.${corner}.${layer_name}.png" \
+      "IR drop for $net on $layer_name for $corner"
+  }
+}
+
+proc sc_image_routing_congestion {} {
+  if { ![sc_has_global_routing] } {
+    return
+  }
+
+  sc_image_setup_default
+
+  sc_image_heatmap "Routing Congestion" \
+    "Routing" \
+    "routing_congestion.png" \
+    "routing congestion" \
+    0
+}
+
+proc sc_image_estimated_routing_congestion {} {
+  if { ![sc_has_placed_instances] } {
+    return
+  }
+
+  sc_image_setup_default
+
+  suppress_message GRT 10
+  catch { \
+    sc_image_heatmap "Estimated Congestion (RUDY)" \
+      "RUDY" \
+      "estimated_routing_congestion.png" \
+      "estimated routing congestion" \
+      0 } err
+  unsuppress_message GRT 10
+}
+
+proc sc_image_power_density {} {
+  if { ![sc_has_placed_instances] } {
+    return
+  }
+
+  sc_image_setup_default
+
+  file mkdir reports/images/heatmap/power_density
+
+  foreach corner [sta::corners] {
+    set corner_name [$corner name]
+
+    gui::set_heatmap Power Corner $corner_name
+    gui::set_heatmap Power rebuild
+
+    sc_image_heatmap "Power Density" \
+      "Power" \
+      "power_density/${corner_name}.png" \
+      "power density for $corner_name"
+  }
+}
+
+proc sc_image_placement_density {} {
+  if { ![sc_has_placed_instances] } {
+    return
+  }
+
+  sc_image_setup_default
+
+  sc_image_heatmap "Placement Density" \
+    "Placement" \
+    "placement_density.png" \
+    "placement density"
+}
+
+proc sc_image_clocks {} {
+  if { ![sc_has_placed_instances] } {
+    return
+  }
+
+  global sc_design
+  sc_image_setup_default
+
+  # The clock view: all clock nets and buffers
+  gui::set_display_controls "Layers/*" visible true
+  gui::set_display_controls "Nets/*" visible false
+  gui::set_display_controls "Nets/Clock" visible true
+  gui::set_display_controls "Instances/*" visible false
+  gui::set_display_controls "Instances/StdCells/Clock tree/*" visible true
+  if { [select -name "clk*" -type Inst] == 0 } {
+    # Nothing selected
+    return
+  }
+
+  sc_save_image "clocks" reports/images/${sc_design}.clocks.png
+}
+
+proc sc_image_clocktree {} {
+  gui::show_widget "Clock Tree Viewer"
+  global sc_scenarios
+
+  set clock_state []
+  foreach clock [all_clocks] {
+    lappend clock_state $clock [$clock is_propagated]
+  }
+  set_propagated_clock [all_clocks]
+
+  foreach clock [get_clocks *] {
+    if { [llength [get_property $clock sources]] == 0 } {
+      # Skip virtual clocks
+      continue
+    }
+    file mkdir reports/images/clocktree
+
+    set clock_name [get_name $clock]
+    foreach corner $sc_scenarios {
+      set path reports/images/clocktree/${clock_name}.${corner}.png
+      utl::info FLW 1 "Saving $clock_name clock tree for $corner in $path"
+      save_clocktree_image $path \
+        -clock $clock_name \
+        -width 1024 \
+        -height 1024 \
+        -corner $corner
+    }
+  }
+
+  foreach {clock state} $clock_state {
+    if { $state } {
+      set_propagated_clock $clock
+    } else {
+      unset_propagated_clock $clock
+    }
+  }
+
+  gui::hide_widget "Clock Tree Viewer"
+}
+
+proc sc_image_optimizer {} {
+  global sc_design
+  sc_image_setup_default
+
+  # The resizer view: all instances created by the resizer grouped
+  gui::set_display_controls "Layers/*" visible false
+  gui::set_display_controls "Instances/*" visible true
+  gui::set_display_controls "Instances/Physical/*" visible false
+
+  set hold_count       [select -name "hold*" -type Inst -highlight 0]       ;# green
+  set input_count      [select -name "input*" -type Inst -highlight 1]      ;# yellow
+  set output_count     [select -name "output*" -type Inst -highlight 1]
+  set repeater_count   [select -name "repeater*" -type Inst -highlight 3]   ;# magenta
+  set fanout_count     [select -name "fanout*" -type Inst -highlight 3]
+  set load_slew_count  [select -name "load_slew*" -type Inst -highlight 3]
+  set max_cap_count    [select -name "max_cap*" -type Inst -highlight 3]
+  set max_length_count [select -name "max_length*" -type Inst -highlight 3]
+  set wire_count       [select -name "wire*" -type Inst -highlight 3]
+  set rebuffer_count   [select -name "rebuffer*" -type Inst -highlight 4]   ;# red
+  set split_count      [select -name "split*" -type Inst -highlight 5]      ;# dark green
+
+  set select_count [expr { \
+    $hold_count + \
+    $input_count + \
+    $output_count + \
+    $repeater_count + \
+    $fanout_count + \
+    $load_slew_count + \
+    $max_cap_count + \
+    $max_length_count + \
+    $wire_count + \
+    $rebuffer_count + \
+    $split_count }]
+
+  if { $select_count == 0 } {
+    # Nothing selected
+    return
+  }
+
+  sc_save_image "optimizer" reports/images/${sc_design}.optimizer.png
+}
+
+# Setup
+file mkdir reports/images
+gui::save_display_controls
+sc_image_setup_default
+
+if { [file exists reports/${sc_design}_drc.rpt] } {
+  # Show the drc markers (if any)
+  gui::load_drc reports/${sc_design}_drc.rpt
+}
+
+# General images
+sc_image_everything
+sc_image_placement
+sc_image_routing
+
+# Heatmaps
+if { [sc_cfg_tool_task_check_in_list placement_density var reports] } {
+  sc_image_placement_density
+}
+
+if { [sc_cfg_tool_task_check_in_list routing_congestion var reports] } {
+  sc_image_estimated_routing_congestion
+  sc_image_routing_congestion
+}
+
+if { [sc_cfg_tool_task_check_in_list power var reports] } {
+  if { [sc_cfg_tool_task_check_in_list power_density var reports] } {
+    sc_image_power_density
+  }
+
+  if { [sc_cfg_tool_task_check_in_list ir_drop var reports] } {
+    foreach net [sc_psm_check_nets] {
+      foreach corner $sc_scenarios {
+        sc_image_irdrop $net $corner
+      }
+    }
+  }
+}
+
+# Clocks
+if { [sc_cfg_tool_task_check_in_list clock_placement var reports] } {
+  sc_image_clocks
+}
+if { [sc_cfg_tool_task_check_in_list clock_trees var reports] } {
+  sc_image_clocktree
+}
+
+# Optimizations
+if { [sc_cfg_tool_task_check_in_list optimization_placement var reports] } {
+  sc_image_optimizer
+}
+
+# Restore
+sc_image_clear_selection
+gui::restore_display_controls

siliconcompiler/tools/openroad/show.py

@@ -0,0 +1,94 @@
+import shutil
+import os
+
+from siliconcompiler.tools.openroad import openroad
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools._common import find_incoming_ext, input_provides, get_tool_task
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    openroad.make_docs(chip)
+    chip.set('tool', 'openroad', 'task', 'show', 'var', 'show_filepath', '<path>')
+
+
+def setup(chip):
+    '''
+    Show a design in openroad
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    generic_show_setup(chip, 'show', False)
+
+
+def generic_show_setup(chip, task, exit):
+    tool = 'openroad'
+    design = chip.top()
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    option = "-no_init -gui"
+
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit', "true" if exit else "false",
+             step=step, index=index, clobber=False)
+    if chip.valid('tool', tool, 'task', task, 'var', 'show_filepath'):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'show_filepath']),
+                 step=step, index=index)
+    else:
+        incoming_ext = find_incoming_ext(chip, ('odb', 'def'), 'def')
+        chip.set('tool', tool, 'task', task, 'var', 'show_filetype', incoming_ext,
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.{incoming_ext}',
+                 step=step, index=index)
+        if f'{design}.sdc' in input_provides(chip, step, index):
+            chip.add('tool', tool, 'task', task, 'input', f'{design}.sdc',
+                     step=step, index=index)
+
+    # Add to option string.
+    cur_options = ' '.join(chip.get('tool', tool, 'task', task, 'option', step=step, index=index))
+    new_options = f'{cur_options} {option}'
+    chip.set('tool', tool, 'task', task, 'option', new_options,
+             step=step, index=index, clobber=True)
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    copy_show_files(chip)
+    build_pex_corners(chip)
+
+
+def copy_show_files(chip):
+
+    tool = 'openroad'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    if chip.valid('tool', tool, 'task', task, 'var', 'show_filepath'):
+        show_file = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',
+                             step=step, index=index)[0]
+        show_type = chip.get('tool', tool, 'task', task, 'var', 'show_filetype',
+                             step=step, index=index)[0]
+        show_job = chip.get('tool', tool, 'task', task, 'var', 'show_job',
+                            step=step, index=index)
+        show_step = chip.get('tool', tool, 'task', task, 'var', 'show_step',
+                             step=step, index=index)
+        show_index = chip.get('tool', tool, 'task', task, 'var', 'show_index',
+                              step=step, index=index)
+
+        # copy source in to keep sc_apr.tcl simple
+        dst_file = f"inputs/{chip.top()}.{show_type}"
+        shutil.copy2(show_file, dst_file)
+        if show_job and show_step and show_index:
+            sdc_file = chip.find_result('sdc', show_step[0],
+                                        jobname=show_job[0],
+                                        index=show_index[0])
+            if sdc_file and os.path.exists(sdc_file):
+                shutil.copy2(sdc_file, f"inputs/{chip.top()}.sdc")

siliconcompiler/tools/openroad/templates/pex.tcl

@@ -0,0 +1,8 @@
+################################################################
+# Constraint "{{ constraint }}" -> PEX corner "{{ pexcorner }}"
+# Source file: {{ source }}
+################################################################
+
+{{ pex }}
+
+################################################################

siliconcompiler/tools/opensta/__init__.py

@@ -0,0 +1,101 @@
+'''
+OpenSTA is a gate level static timing verifier.
+
+Documentation: https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf
+
+Sources: https://github.com/The-OpenROAD-Project/OpenSTA
+
+Installation: https://github.com/The-OpenROAD-Project/OpenSTA (also installed with OpenROAD)
+'''
+
+import os
+from siliconcompiler.tools.openroad.openroad import get_library_timing_keypaths
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common.asic import get_libraries
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    chip.load_target("asap7_demo")
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'sta')
+    chip.set('tool', tool, 'vswitch', '-version')
+    chip.set('tool', tool, 'version', '>=v2.5.0', clobber=False)
+    chip.set('tool', tool, 'format', 'tcl')
+
+    targetlibs = get_libraries(chip, 'logic')
+    macrolibs = get_libraries(chip, 'macro')
+    delaymodel = chip.get('asic', 'delaymodel', step=step, index=index)
+
+    # Input/Output requirements for default asicflow steps
+    chip.set('tool', tool, 'task', task, 'refdir', 'tools/opensta/scripts',
+             step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    if delaymodel != 'nldm':
+        chip.logger.error(f'{delaymodel} delay model is not supported by {tool}, only nldm')
+
+    if targetlibs:
+        # Note: only one footprint supported in mainlib
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['asic', 'logiclib']),
+                 step=step, index=index)
+
+        for lib in targetlibs:
+            for timing_key in get_library_timing_keypaths(chip, lib).values():
+                chip.add('tool', tool, 'task', task, 'require', ",".join(timing_key),
+                         step=step, index=index)
+        for lib in macrolibs:
+            for timing_key in get_library_timing_keypaths(chip, lib).values():
+                if chip.valid(*timing_key):
+                    chip.add('tool', tool, 'task', task, 'require', ",".join(timing_key),
+                             step=step, index=index)
+    else:
+        chip.error('logiclib parameters required for OpenSTA.')
+
+    # basic warning and error grep check on logfile
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'^\[WARNING|^Warning',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'^\[ERROR',
+             step=step, index=index, clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    return stdout.strip()
+
+
+################################
+# Runtime options
+################################
+def runtime_options(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    # exit automatically in batch mode and not breakpoint
+    option = []
+    if not chip.get('option', 'breakpoint', step=step, index=index):
+        option.append("-exit")
+
+    tool, task = get_tool_task(chip, step, index)
+    option.extend([
+        '-threads',
+        str(chip.get('tool', tool, 'task', task, 'threads', step=step, index=index))
+    ])
+
+    return option

siliconcompiler/tools/opensta/report_libraries.py

@@ -0,0 +1,28 @@
+import os
+from siliconcompiler.tools.opensta import setup as tool_setup
+from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Report information about the timing libraries.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    tool_setup(chip)
+
+    chip.set('tool', tool, 'task', task, 'script', 'sc_report_libraries.tcl',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index)
+
+
+################################
+# Runtime options
+################################
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/opensta/scripts/sc_procs.tcl

@@ -0,0 +1,47 @@
+
+###########################
+# Count the logic depth of the critical path
+###########################
+
+proc sc_count_logic_depth {} {
+    set count 0
+    set paths [find_timing_paths -sort_by_slack]
+    if { [llength $paths] == 0 } {
+        return 0
+    }
+    set path_ref [[lindex $paths 0] path]
+    set pins [$path_ref pins]
+    foreach pin $pins {
+        if { [$pin is_driver] } {
+            incr count
+        }
+        set vertex [lindex [$pin vertices] 0]
+        # Stop at clock vertex
+        if { [$vertex is_clock] } {
+            break
+        }
+    }
+    # Subtract 1 to account for initial launch
+    return [expr { $count - 1 }]
+}
+
+proc sc_design_area {} {
+    set area 0
+    foreach inst [get_cells -hierarchical *] {
+        set lib_cell [$inst liberty_cell]
+        if { $lib_cell != "NULL" } {
+            set area [expr { $area + [get_property $lib_cell area] }]
+        }
+    }
+    return $area
+}
+
+proc sc_display_report {report} {
+    if { ![file exists $report] } {
+        return
+    }
+    set fid [open $report r]
+    set report_content [read $fid]
+    close $fid
+    puts $report_content
+}