siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/vivado/vivado.py

@@ -0,0 +1,147 @@
+'''
+Vivado is an FPGA programming tool suite from Xilinx used to
+program Xilinx devices.
+
+Documentation: https://www.xilinx.com/products/design-tools/vivado.html
+'''
+
+import json
+import os
+import re
+from siliconcompiler import sc_open
+from siliconcompiler.tools._common import record_metric
+
+
+def make_docs(chip):
+    chip.set('fpga', 'partname', 'ice40up5k-sg48')
+    chip.load_target("fpgaflow_demo")
+
+
+tool = 'vivado'
+
+
+def setup(chip):
+    vendor = 'xilinx'
+
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vendor', vendor)
+    chip.set('tool', tool, 'vswitch', '-version')
+    chip.set('tool', tool, 'format', 'tcl')
+
+    # report_design_analysis -json flag requires Vivado 2021 or greater
+    chip.set('tool', tool, 'version', '>=2021', clobber=False)
+
+
+def setup_task(chip, task):
+    setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    script = 'sc_run.tcl'
+
+    refdir = f'tools/{tool}/scripts'
+    option = ['-nolog', '-nojournal', '-mode', 'batch', '-source']
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'^ERROR:',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'^(CRITICAL )?WARNING:',
+             step=step, index=index, clobber=False)
+
+
+def parse_version(stdout):
+    # Vivado v2021.2 (64-bit)
+    return stdout.split()[1]
+
+
+def normalize_version(version):
+    return version.lstrip('v')
+
+
+def _parse_qor_summary(chip, step, index):
+    if not os.path.isfile('qor_summary.json'):
+        return
+
+    with sc_open('qor_summary.json') as f:
+        data = json.load(f)
+
+        # Data is organized as list of tasks that Vivado has completed, with
+        # metrics associated with each. The tasks appear to be in chronological
+        # order, so we pull metrics from the last one.
+        task = data['Design QoR Summary'][-1]
+        setup_wns = task['Wns(ns)']
+        setup_tns = task['Tns(ns)']
+        hold_wns = task['Whs(ns)']
+        hold_tns = task['Ths(ns)']
+
+        if setup_wns:
+            record_metric(chip, step, index, 'setupwns', setup_wns,
+                          'qor_summary.json',
+                          source_unit='ns')
+        if setup_tns:
+            record_metric(chip, step, index, 'setuptns', setup_tns,
+                          'qor_summary.json',
+                          source_unit='ns')
+        if hold_wns:
+            record_metric(chip, step, index, 'holdwns', hold_wns,
+                          'qor_summary.json',
+                          source_unit='ns')
+        if hold_tns:
+            record_metric(chip, step, index, 'holdtns', hold_tns,
+                          'qor_summary.json',
+                          source_unit='ns')
+
+
+def _parse_utilization(chip, step, index):
+    if not os.path.isfile('reports/total_utilization.rpt'):
+        return
+
+    with sc_open('reports/total_utilization.rpt') as f:
+        regexes = {
+            'luts': (re.compile(r'(?:CLB|Slice) LUTs\*?\s+\|\s+(\d+)'), int),
+            'regs': (re.compile(r'(?:CLB|Slice) Registers\s+\|\s+(\d+)'), int),
+            'bram': (re.compile(r'Block RAM Tile\s+\|\s+(\d+(.\d+)?)'), float),
+            # TODO: should URAM be float?
+            'uram': (re.compile(r'URAM\s+\|\s+(\d+(.\d+)?)'), float)
+        }
+        vals = {}
+
+        for line in f:
+            for metric, (regex, datatype) in regexes.items():
+                if metric in vals:
+                    continue
+                match = regex.search(line)
+                if match:
+                    vals[metric] = datatype(match.group(1))
+                    continue
+
+        if 'luts' in vals:
+            record_metric(chip, step, index, 'luts', vals['luts'],
+                          'reports/total_utilization.rpt')
+        if 'regs' in vals:
+            record_metric(chip, step, index, 'registers', vals['regs'],
+                          'reports/total_utilization.rpt')
+
+        total_bram = 0
+        if 'bram' in vals:
+            total_bram += vals['bram']
+        if 'uram' in vals:
+            total_bram += vals['uram']
+        if 'bram' in vals or 'uram' in vals:
+            record_metric(chip, step, index, 'brams', total_bram,
+                          'reports/total_utilization.rpt')
+
+
+def post_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    _parse_qor_summary(chip, step, index)
+    _parse_utilization(chip, step, index)

siliconcompiler/tools/vpr/_json_constraint.py

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+import json
+
+
+def load_json_constraints(json_constraints_file):
+
+    json_generic_constraints = {}
+    with (open(json_constraints_file, "r")) as json_constraints_data:
+        json_generic_constraints = json.loads(json_constraints_data.read())
+
+    return json_generic_constraints
+
+
+def load_constraints_map(constraints_map_file):
+
+    constraints_map = {}
+    with (open(constraints_map_file, "r")) as constraints_map_data:
+        constraints_map = json.loads(constraints_map_data.read())
+
+    return constraints_map
+
+
+def map_constraints(chip,
+                    json_generic_constraints,
+                    constraints_map):
+
+    design_constraints = {}
+    errors = 0
+
+    # If no constraints map is provided pass the constraints directly
+    if not constraints_map:
+
+        for design_pin in json_generic_constraints:
+            design_constraints[design_pin] = json_generic_constraints[design_pin]['pin']
+
+    # Otherwise use the constraints map to remap the constraints to the correct
+    # internal FPGA core pin:
+    else:
+        for design_pin in json_generic_constraints:
+
+            # VPR has a quirk that it prepends "out:" to outputs to differentiate
+            # the pin from any block name that may have inherited its instance name
+            # from an output.  Compensate for that quirk here
+            if (json_generic_constraints[design_pin]['direction'] == "output"):
+                named_design_pin = f'out:{design_pin}'
+            else:
+                named_design_pin = design_pin
+
+            design_pin_assignment = json_generic_constraints[design_pin]['pin']
+
+            if (design_pin_assignment in constraints_map):
+                # Convert the dictionary entries in the constraints map into a tuple:
+                design_pin_constraint_assignment = (
+                    constraints_map[design_pin_assignment]['x'],
+                    constraints_map[design_pin_assignment]['y'],
+                    constraints_map[design_pin_assignment]['subtile'])
+
+                design_constraints[named_design_pin] = design_pin_constraint_assignment
+
+            else:
+                chip.logger.error(f'Cannot map to pin {design_pin_assignment}')
+                errors += 1
+
+    return design_constraints, errors

siliconcompiler/tools/vpr/_xml_constraint.py

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+import xml.etree.ElementTree as ET
+import xml.dom.minidom
+
+
+def generate_vpr_constraints_xml_file(pin_map, filename):
+
+    constraints_xml = generate_vpr_constraints_xml(pin_map)
+    write_vpr_constraints_xml_file(constraints_xml, filename)
+
+
+def generate_vpr_constraints_xml(pin_map):
+
+    constraints_xml = ET.Element("vpr_constraints")
+
+    # Generate partition list section
+    partition_list = generate_partition_list_xml(pin_map)
+
+    constraints_xml.append(partition_list)
+
+    return constraints_xml
+
+
+def generate_partition_list_xml(pin_map):
+
+    partition_list = ET.Element("partition_list")
+
+    # ***ASSUMPTION:  pin map is a dictionary of block names
+    #                 and tuples, where the tuples specify the
+    #                 (X,Y,subtile) locations that each block
+    #                 is constrained to
+    for pin, region in pin_map.items():
+
+        cur_partition = generate_partition_xml(pin, region)
+        partition_list.append(cur_partition)
+
+    return partition_list
+
+
+def generate_partition_xml(pin, pin_region):
+
+    partition = ET.Element("partition")
+
+    partition_name = generate_partition_name(pin)
+    partition.set("name", partition_name)
+
+    atom_xml = generate_add_atom_xml(pin)
+    partition.append(atom_xml)
+
+    x_low, x_high, y_low, y_high, subtile = generate_region_from_pin(pin_region)
+    region_xml = generate_add_region_xml(x_low, x_high, y_low, y_high, subtile)
+    partition.append(region_xml)
+
+    return partition
+
+
+def generate_region_from_pin(pin_region):
+
+    # ***ASSUMPTION:  Pin region is a 3-element tuple
+    #                 containing (X,Y,subtile) coordinates
+
+    # TODO figure out a scheme that supports VPR's notion
+    # of specifying a region size of > 1x1
+    x_low = int(pin_region[0])
+    x_high = int(pin_region[0])
+    y_low = int(pin_region[1])
+    y_high = int(pin_region[1])
+    subtile = int(pin_region[2])
+    return x_low, x_high, y_low, y_high, subtile
+
+
+def generate_partition_name(pin):
+
+    partition_name = pin
+    partition_name = partition_name.replace('[', '_')
+    partition_name = partition_name.replace(']', '')
+    partition_name = "part_" + partition_name
+
+    return partition_name
+
+
+def generate_add_atom_xml(pin_name):
+
+    atom_xml = ET.Element("add_atom")
+
+    atom_xml.set("name_pattern", str(pin_name))
+
+    return atom_xml
+
+
+def generate_add_region_xml(x_low, x_high, y_low, y_high, subtile):
+
+    region_xml = ET.Element("add_region")
+
+    region_xml.set("x_low", str(x_low))
+    region_xml.set("y_low", str(y_low))
+    region_xml.set("x_high", str(x_high))
+    region_xml.set("y_high", str(y_high))
+    region_xml.set("subtile", str(subtile))
+
+    return region_xml
+
+
+def write_vpr_constraints_xml_file(constraints: ET.Element, filename: str):
+
+    dom = xml.dom.minidom.parseString(ET.tostring(constraints))
+    xml_string = dom.toprettyxml()
+
+    with open(filename, 'w') as xfile:
+        xfile.write(str(xml_string))

siliconcompiler/tools/vpr/place.py

@@ -0,0 +1,137 @@
+import os
+import shutil
+from siliconcompiler import SiliconCompilerError
+from siliconcompiler.tools.vpr import vpr
+from siliconcompiler.tools.vpr._json_constraint import load_constraints_map
+from siliconcompiler.tools.vpr._json_constraint import load_json_constraints
+from siliconcompiler.tools.vpr._json_constraint import map_constraints
+from siliconcompiler.tools.vpr._xml_constraint import generate_vpr_constraints_xml_file
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip, clobber=True):
+    '''
+    Perform automated place and route with VPR
+    '''
+
+    tool = 'vpr'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    vpr.setup_tool(chip, clobber=clobber)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    design = chip.top()
+    chip.set('tool', tool, 'task', task, 'input', design + '.blif', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'output', design + '.blif', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.net', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.place', step=step, index=index)
+
+
+def runtime_options(chip):
+    '''Command line options to vpr for the place step
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    options = vpr.runtime_options(chip)
+
+    blif = f"inputs/{design}.blif"
+    options.append(blif)
+
+    options.append('--pack')
+    options.append('--place')
+
+    enable_images = chip.get('tool', tool, 'task', task, 'var', 'enable_images',
+                             step=step, index=index)[0]
+
+    if enable_images == 'true':
+        graphics_commands = vpr.get_common_graphics(chip)
+
+        graphics_command_str = " ".join(graphics_commands)
+
+        options.append("--graphics_commands")
+        options.append(f"\"{graphics_command_str}\"")
+
+    return options
+
+
+################################
+# Pre_process (pre executable)
+################################
+
+
+def pre_process(chip):
+    ''' Tool specific function to run before step execution
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    part_name = chip.get('fpga', 'partname')
+
+    # If the user explicitly provides an XML constraints file, give that
+    # priority over other constraints input types:
+    if 'vpr_pins' in chip.getkeys('input', 'constraint'):
+        constraint_file = vpr.find_single_file(chip, 'input', 'constraint', 'vpr_pins',
+                                               step=step, index=index,
+                                               file_not_found_msg="VPR constraints file not found")
+
+        if (constraint_file is not None):
+            shutil.copy2(constraint_file, vpr.auto_constraints())
+
+    elif 'pcf' in chip.getkeys('input', 'constraint'):
+        constraint_file = vpr.find_single_file(chip, 'input', 'constraint', 'pcf',
+                                               step=step, index=index,
+                                               file_not_found_msg="PCF constraints file not found")
+
+        map_file = vpr.find_single_file(chip, 'fpga', part_name, 'file', 'constraints_map',
+                                        file_not_found_msg="constraints map not found")
+
+        if not map_file:
+            raise SiliconCompilerError('FPGA does not have required constraints map', chip=chip)
+
+        constraints_map = load_constraints_map(map_file)
+        json_constraints = load_json_constraints(constraint_file)
+        all_place_constraints, missing_pins = map_constraints(chip,
+                                                              json_constraints,
+                                                              constraints_map)
+        if (missing_pins > 0):
+            raise SiliconCompilerError(
+                "Pin constraints specify I/O ports not in this architecture", chip=chip)
+
+        generate_vpr_constraints_xml_file(all_place_constraints, vpr.auto_constraints())
+
+    else:
+        all_component_constraints = chip.getkeys('constraint', 'component')
+        all_place_constraints = {}
+        for component in all_component_constraints:
+            place_constraint = chip.get('constraint', 'component', component, 'placement',
+                                        step=step, index=index)
+            chip.logger.info(f'Place constraint for {component} at {place_constraint}')
+            all_place_constraints[component] = place_constraint
+
+        if all_place_constraints:
+            generate_vpr_constraints_xml_file(all_place_constraints, vpr.auto_constraints())
+
+
+################################
+# Post_process (post executable)
+################################
+
+
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+    vpr.vpr_post_process(chip)
+
+    design = chip.top()
+    shutil.copy2(f'inputs/{design}.blif', 'outputs')

siliconcompiler/tools/vpr/route.py

@@ -0,0 +1,124 @@
+import os
+import shutil
+
+from siliconcompiler.tools.vpr import vpr
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip, clobber=True):
+    '''
+    Perform automated place and route with VPR
+    '''
+
+    tool = 'vpr'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    vpr.setup_tool(chip, clobber=clobber)
+
+    # Match VPR's default max router iterations value so that
+    # the parameter is traceable by SC through the flow.
+    chip.set('tool', tool, 'task', task, 'var', 'max_router_iterations', "50",
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'max_router_iterations',
+             'set maximum number of routing iterations',
+             field='help')
+
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'max_router_iterations']),
+             step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=clobber)
+
+    # TO-DO: PRIOROTIZE the post-routing packing results?
+    design = chip.top()
+    chip.set('tool', tool, 'task', task, 'input', design + '.blif', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'input', design + '.net', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'input', design + '.place', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'output', design + '.route', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.blif', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.net', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.place', step=step, index=index)
+
+
+def runtime_options(chip):
+    '''Command line options to vpr for the route step
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    options = vpr.runtime_options(chip)
+
+    blif = f"inputs/{design}.blif"
+    options.append(blif)
+
+    options.append('--route')
+    # To run only the routing step we need to pass in the placement files
+    options.append(f'--net_file inputs/{design}.net')
+    options.append(f'--place_file inputs/{design}.place')
+
+    enable_images = chip.get('tool', tool, 'task', task, 'var', 'enable_images',
+                             step=step, index=index)[0]
+
+    route_iterations = chip.get('tool', tool, 'task', task, 'var', 'max_router_iterations',
+                                step=step, index=index)
+
+    if (len(route_iterations) > 0):
+        options.append(f'--max_router_iterations {route_iterations[0]}')
+
+    if enable_images == 'true':
+        design = chip.top()
+
+        graphics_commands = vpr.get_common_graphics(chip)
+
+        # set_draw_block_text 0 hides the label for various blocks in the design
+        # set_draw_block_outlines 0 removes the outline/boundary for various blocks in the design
+        # set_routing_util 1 displays the routing utilization as a heat map
+        # set_routing_util 4 displays the routing utilization as a heat map over placed blocks
+        # Refer: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/
+        # vpr/src/draw/draw_types.h#L89
+        # save_graphics saves the block diagram as a png/svg/pdf
+        # Refer:
+        # https://docs.verilogtorouting.org/en/latest/vpr/command_line_usage/#graphics-options
+        graphics_commands.append("set_draw_block_text 0; " +
+                                 "set_draw_block_outlines 0; " +
+                                 "set_routing_util 1; " +
+                                 "save_graphics "
+                                 f"reports/{design}_route_utilization_with_placement.png;")
+        graphics_commands.append("set_draw_block_text 0; " +
+                                 "set_draw_block_outlines 0; " +
+                                 "set_routing_util 4; " +
+                                 "save_graphics "
+                                 f"reports/{design}_route_utilization.png;")
+
+        graphics_command_str = " ".join(graphics_commands)
+
+        options.append("--graphics_commands")
+        options.append(f"\"{graphics_command_str}\"")
+
+    return options
+
+
+################################
+# Post_process (post executable)
+################################
+
+
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+    vpr.vpr_post_process(chip)
+
+    design = chip.top()
+    # Forward all of the prior step inputs forward for bitstream generation
+    shutil.copy2(f'inputs/{design}.blif', 'outputs')
+    shutil.copy2(f'inputs/{design}.net', 'outputs')
+    shutil.copy2(f'inputs/{design}.place', 'outputs')

siliconcompiler/tools/vpr/screenshot.py

@@ -0,0 +1,54 @@
+from siliconcompiler import SiliconCompilerError
+from siliconcompiler.tools.vpr import show
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip, clobber=True):
+    '''
+    Screenshot placed and/or routed designs
+    '''
+
+    show.setup(chip, clobber=clobber)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.png', step=step, index=index)
+
+
+def runtime_options(chip):
+    '''Command line options to vpr for screenshot
+    '''
+
+    design = chip.top()
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if chip.valid('tool', tool, 'task', task, 'var', 'show_filepath'):
+        show_type = chip.get('tool', tool, 'task', task, 'var', 'show_filetype',
+                             step=step, index=index)[0]
+    else:
+        raise SiliconCompilerError("Invalid filepath", chip=chip)
+
+    options = show.generic_show_options(chip)
+
+    if show_type == 'route':
+        screenshot_command_str = ("set_draw_block_text 0; " +
+                                  "set_draw_block_outlines 0; " +
+                                  "set_routing_util 1; " +
+                                  f"save_graphics outputs/{design}.png;")
+    elif show_type == 'place':
+        screenshot_command_str = ("set_draw_block_text 1; " +
+                                  "set_draw_block_outlines 1; " +
+                                  f"save_graphics outputs/{design}.png;")
+    else:
+        raise SiliconCompilerError(f"Incorrect file type {show_type}", chip=chip)
+
+    options.append("--graphics_commands")
+    options.append(f"\"{screenshot_command_str}\"")
+
+    return options