siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/openroad/physyn.py

@@ -0,0 +1,27 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import set_pnr_inputs, set_pnr_outputs
+
+
+def setup(chip):
+    '''
+    Not implemented yet
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/place.py

@@ -0,0 +1,41 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+
+
+def setup(chip):
+    '''
+    Perform global and detail placements along with design violation repairs
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    _set_reports(chip, [
+        'setup',
+        'unconstrained',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/rcx_bench.py

@@ -0,0 +1,95 @@
+from siliconcompiler.tools.openroad import openroad
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup_tool(chip):
+    ''' Helper method for configs specific to extraction tasks.
+    '''
+
+    openroad.setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'sc_rcx.tcl', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index)
+
+
+def setup_task(chip):
+    # Generic tool setup.
+    setup_tool(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+
+    chip.set('tool', tool, 'task', task, 'var', 'libtype',
+             list(chip.getkeys('pdk', pdk, 'aprtech', tool, stackup))[0],
+             clobber=False, step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'var', 'libtype',
+             'Library type used to select the lef file',
+             field='help')
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'libtype']),
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['pdk',
+                       pdk,
+                       'aprtech',
+                       tool,
+                       stackup,
+                       chip.get('tool', tool, 'task', task, 'var', 'libtype',
+                                step=step, index=index)[0],
+                       'lef']),
+             step=step, index=index)
+
+
+def setup(chip):
+    ''' Helper method for configs specific to extraction tasks.
+    '''
+
+    # Generic tool setup.
+    setup_task(chip)
+
+    design = chip.top()
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.def', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.vg', step=step, index=index)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+
+    if chip.valid('pdk', pdk, 'var', 'openroad', 'rcx_bench_max_layer', stackup):
+        chip.set('tool', tool, 'task', task, 'var', 'max_layer',
+                 chip.get('pdk', pdk, 'var', 'openroad', 'rcx_bench_max_layer', stackup)[0],
+                 clobber=False, step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['pdk', pdk, 'var', 'openroad', 'rcx_bench_max_layer', stackup]),
+                 step=step, index=index)
+    else:
+        chip.set('tool', tool, 'task', task, 'var', 'max_layer',
+                 chip.get('pdk', pdk, 'maxlayer', stackup),
+                 clobber=False, step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'var', 'max_layer',
+             'Maximum layer to generate extraction bench for',
+             field='help')
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'max_layer']),
+             step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'bench_length', '100',
+             clobber=False, step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'var', 'bench_length',
+             'Length of bench wires',
+             field='help')
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'bench_length']),
+             step=step, index=index)

siliconcompiler/tools/openroad/rcx_extract.py

@@ -0,0 +1,34 @@
+from siliconcompiler.tools.openroad.rcx_bench import setup_task
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    ''' Helper method for configs specific to extraction tasks.
+    '''
+
+    # Generic tool setup.
+    setup_task(chip)
+
+    design = chip.top()
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'corner',
+             'Parasitic corner to generate RCX file for',
+             field='help')
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'corner']),
+             step=step, index=index)
+
+    if chip.valid('tool', tool, 'task', task, 'var', 'corner') and \
+       chip.get('tool', tool, 'task', task, 'var', 'corner', step=step, index=index):
+        corner = chip.get('tool', tool, 'task', task, 'var', 'corner', step=step, index=index)[0]
+    else:
+        # Placeholder since require will cause this to fail
+        corner = 'corner'
+
+    chip.add('tool', tool, 'task', task, 'input', f'{design}.def', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'input', f'{design}.{corner}.spef', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.{corner}.rcx', step=step, index=index)

siliconcompiler/tools/openroad/route.py

@@ -0,0 +1,45 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+
+
+def setup(chip):
+    '''
+    Performs filler insertion, global routing, antenna repair, and detailed routing
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    _set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/screenshot.py

@@ -0,0 +1,60 @@
+from siliconcompiler.tools.openroad import openroad
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.show import copy_show_files, generic_show_setup
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports
+from siliconcompiler.tools._common import get_tool_task
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    openroad.make_docs(chip)
+    chip.set('tool', 'openroad', 'task', 'screenshot', 'var', 'show_filepath', '<path>')
+
+
+def setup(chip):
+    '''
+    Generate a PNG file from a layout file
+    '''
+
+    tool = 'openroad'
+    design = chip.top()
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    generic_show_setup(chip, task, True)
+
+    chip.add('tool', tool, 'task', task, 'output', design + '.png', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'show_vertical_resolution', '1024',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'include_report_images', 'false',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'include_report_images',
+             'true/false, include the images in reports/',
+             field='help')
+
+    _set_reports(chip, [
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'ir_drop',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    copy_show_files(chip)
+    build_pex_corners(chip)