siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/netgen/count_lvs.py

@@ -0,0 +1,132 @@
+#!/usr/bin/python3
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# ---------------------------------------------------------
+# LVS failure check
+#
+# This is a Python script that parses the comp.json
+# output from netgen and reports on the number of
+# errors in the top-level netlist.
+#
+# ---------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# Pulled from qflow GUI as standalone script Aug 20, 2018
+# ---------------------------------------------------------
+
+import re
+import json
+import argparse
+from siliconcompiler import sc_open
+
+
+def count_LVS_failures(filename):
+    with sc_open(filename) as cfile:
+        lvsdata = json.load(cfile)
+
+    # Count errors in the JSON file
+    failures = 0
+    devfail = 0
+    netfail = 0
+    pinfail = 0
+    propfail = 0
+    netdiff = 0
+    devdiff = 0
+    ncells = len(lvsdata)
+    for c in range(0, ncells):
+        cellrec = lvsdata[c]
+
+        if c == ncells - 1:
+            topcell = True
+        else:
+            topcell = False
+
+        # Most errors must only be counted for the top cell, because individual
+        # failing cells are flattened and the matching attempted again on the
+        # flattened netlist.
+
+        if topcell:
+            if 'devices' in cellrec:
+                devices = cellrec['devices']
+                devlist = [val for pair in zip(devices[0], devices[1]) for val in pair]
+                devpair = list(devlist[p:p + 2] for p in range(0, len(devlist), 2))
+                for dev in devpair:
+                    c1dev = dev[0]
+                    c2dev = dev[1]
+                    diffdevs = abs(c1dev[1] - c2dev[1])
+                    failures += diffdevs
+                    devdiff += diffdevs
+
+            if 'nets' in cellrec:
+                nets = cellrec['nets']
+                diffnets = abs(nets[0] - nets[1])
+                failures += diffnets
+                netdiff += diffnets
+
+            if 'badnets' in cellrec:
+                badnets = cellrec['badnets']
+                failures += len(badnets)
+                netfail += len(badnets)
+
+            if 'badelements' in cellrec:
+                badelements = cellrec['badelements']
+                failures += len(badelements)
+                devfail += len(badelements)
+
+            if 'pins' in cellrec:
+                pins = cellrec['pins']
+                pinlist = [val for pair in zip(pins[0], pins[1]) for val in pair]
+                pinpair = list(pinlist[p:p + 2] for p in range(0, len(pinlist), 2))
+                for pin in pinpair:
+                    # Avoid flagging global vs. local names, e.g., "gnd" vs. "gnd!,"
+                    # and ignore case when comparing pins.
+                    pin0 = re.sub('!$', '', pin[0].lower())
+                    pin1 = re.sub('!$', '', pin[1].lower())
+                    if pin0 != pin1:
+                        failures += 1
+                        pinfail += 1
+
+        # Property errors must be counted for every cell
+        if 'properties' in cellrec:
+            properties = cellrec['properties']
+            failures += len(properties)
+            propfail += len(properties)
+
+    return [failures, netfail, devfail, pinfail, propfail, netdiff, devdiff]
+
+
+if __name__ == '__main__':
+
+    parser = argparse.ArgumentParser(description='Parses netgen lvs')
+    parser.add_argument('--file', '-f', required=True)
+    args = parser.parse_args()
+    failures = count_LVS_failures(args.file)
+    total = failures[0]
+    if total > 0:
+        failed = True
+        print('LVS reports:')
+        print('    net count difference = ' + str(failures[5]))
+        print('    device count difference = ' + str(failures[6]))
+        print('    unmatched nets = ' + str(failures[1]))
+        print('    unmatched devices = ' + str(failures[2]))
+        print('    unmatched pins = ' + str(failures[3]))
+        print('    property failures = ' + str(failures[4]))
+    else:
+        print('LVS reports no net, device, pin, or property mismatches.')
+
+    print('')
+    print('Total errors = ' + str(total))

siliconcompiler/tools/netgen/lvs.py

@@ -0,0 +1,90 @@
+import os
+
+from siliconcompiler.tools.netgen import count_lvs
+from siliconcompiler import sc_open
+from siliconcompiler.tools._common import get_tool_task, record_metric
+
+
+def setup(chip):
+    '''
+    Perform LVS on the supplied netlists
+    '''
+
+    tool = 'netgen'
+    refdir = 'tools/' + tool
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # magic used for drc and lvs
+    script = 'sc_lvs.tcl'
+
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '-batch')
+    chip.set('tool', tool, 'version', '>=1.5.192', clobber=False)
+    chip.set('tool', tool, 'format', 'tcl')
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'script', script,
+             step=step, index=index, clobber=False)
+
+    # set options
+    options = []
+    options.append('-batch')
+    options.append('source')
+    chip.set('tool', tool, 'task', task, 'option', options, step=step, index=index, clobber=False)
+
+    design = chip.top()
+    chip.add('tool', tool, 'task', task, 'input', f'{design}.spice', step=step, index=index)
+    if chip.valid('input', 'netlist', 'verilog'):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['input', 'netlist', 'verilog']),
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.vg', step=step, index=index)
+
+    # Netgen doesn't have a standard error prefix that we can grep for, but it
+    # does print all errors to stderr, so we can redirect them to <step>.errors
+    # and use that file to count errors.
+    chip.set('tool', tool, 'task', task, 'stderr', 'suffix', 'errors', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', '^Warning:',
+             step=step, index=index, clobber=False)
+
+
+################################
+# Post_process (post executable)
+################################
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+
+    Reads error count from output and fills in appropriate entry in metrics
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    design = chip.top()
+
+    with sc_open(f'{step}.errors') as f:
+        errors = len([line for line in f.readlines() if not line.startswith("Note:")])
+    record_metric(chip, step, index, 'errors', errors, f'{step}.errors')
+
+    # Export metrics
+    lvs_report = f'reports/{design}.lvs.json'
+    if not os.path.isfile(lvs_report):
+        chip.logger.warning('No LVS report generated. Netgen may have encountered errors.')
+        return
+
+    lvs_failures = count_lvs.count_LVS_failures(lvs_report)
+
+    # We don't count top-level pin mismatches as errors b/c we seem to get
+    # false positives for disconnected pins. Report them as warnings
+    # instead, the designer can then take a look at the full report for
+    # details.
+    pin_failures = lvs_failures[3]
+    errors = lvs_failures[0] - pin_failures
+    record_metric(chip, step, index, 'drcs', errors, lvs_report)
+    record_metric(chip, step, index, 'warnings', pin_failures, lvs_report)

siliconcompiler/tools/netgen/netgen.py

@@ -0,0 +1,36 @@
+
+'''
+Netgen is a tool for comparing netlists. By comparing a Verilog netlist with
+one extracted from a circuit layout, it can be used to perform LVS
+verification.
+
+Documentation: http://www.opencircuitdesign.com/netgen/
+
+Installation: https://github.com/RTimothyEdwards/netgen
+
+Sources: https://github.com/RTimothyEdwards/netgen
+'''
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    from siliconcompiler.tools.netgen.lvs import setup
+    setup(chip)
+    return chip
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # First line: Netgen 1.5.190 compiled on Fri Jun 25 16:05:36 EDT 2021
+    return stdout.split()[1]
+
+
+##################################################
+if __name__ == "__main__":
+
+    chip = make_docs()
+    chip.write_manifest("netgen.json")

siliconcompiler/tools/netgen/sc_lvs.tcl

@@ -0,0 +1,46 @@
+source ./sc_manifest.tcl
+
+set sc_step    [sc_cfg_get arg step]
+set sc_index   [sc_cfg_get arg index]
+set sc_task    $sc_step
+
+set sc_design [sc_top]
+set sc_macrolibs [sc_get_asic_libraries macro]
+set sc_stackup [sc_cfg_get option stackup]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_runset [sc_cfg_get pdk $sc_pdk lvs runset netgen $sc_stackup basic]
+
+if { [sc_cfg_tool_task_exists var exclude] } {
+    set sc_exclude [sc_cfg_tool_task_get var exclude]
+} else {
+    set sc_exclude [list]
+}
+
+set layout_file "inputs/$sc_design.spice"
+if { [sc_cfg_exists "input" netlist verilog] } {
+    set schematic_file [sc_cfg_get "input" netlist verilog]
+} else {
+    set schematic_file "inputs/$sc_design.vg"
+}
+
+# readnet returns a number that can be used to associate additional files with
+# each netlist read in here
+set layout_fileset [readnet spice $layout_file]
+set schematic_fileset [readnet verilog $schematic_file]
+
+# Read netlists associated with all non-excluded macro libraries
+foreach lib $sc_macrolibs {
+    if { [lsearch -exact $sc_exclude $lib] < 0 } {
+        set netlist [sc_cfg_get library $lib output netlist verilog]
+        # Read $netlist into group of files associated with schematic
+        readnet verilog $netlist $schematic_fileset
+    }
+}
+
+lvs "$layout_file $sc_design" \
+    "$schematic_file $sc_design" \
+    $sc_runset \
+    reports/$sc_design.lvs.out \
+    -json
+
+exit

siliconcompiler/tools/nextpnr/apr.py

@@ -0,0 +1,24 @@
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Perform automated place and route on FPGAs
+    '''
+
+    tool = 'nextpnr'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    topmodule = chip.top()
+
+    clobber = False
+    chip.set('tool', tool, 'exe', 'nextpnr-ice40')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=0.2', clobber=clobber)
+
+    chip.set('tool', tool, 'task', task, 'option', "", step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.netlist.json',
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.asc', step=step, index=index)

siliconcompiler/tools/nextpnr/nextpnr.py

@@ -0,0 +1,59 @@
+'''
+nextpnr is a vendor neutral FPGA place and route tool with
+support for the ICE40, ECP5, and Nexus devices from Lattice.
+
+Documentation: https://github.com/YosysHQ/nextpnr
+
+Sources: https://github.com/YosysHQ/nextpnr
+
+Installation: https://github.com/YosysHQ/nextpnr
+'''
+
+
+#####################################################################
+# Make Docs
+#####################################################################
+def make_docs(chip):
+    from siliconcompiler.tools.nextpnr.apr import setup
+    setup(chip)
+    return chip
+
+
+################################
+#  Custom runtime options
+################################
+def runtime_options(chip):
+    ''' Custom runtime options, returns list of command line options.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    partname = chip.get('fpga', 'partname')
+    topmodule = chip.top()
+
+    options = []
+
+    options.append('--json inputs/' + topmodule + '.netlist.json')
+    options.append('--asc outputs/' + topmodule + '.asc')
+
+    if partname == 'ice40up5k-sg48':
+        options.append('--up5k --package sg48')
+
+    for constraint_file in chip.find_files('input', 'constraint', 'pcf', step=step, index=index):
+        options.append('--pcf ' + constraint_file)
+
+    return options
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # Examples:
+    # nextpnr-ice40 -- Next Generation Place and Route (Version c73d4cf6)
+    # nextpnr-ice40 -- Next Generation Place and Route (Version nextpnr-0.2)
+    version = stdout.split()[-1].rstrip(')')
+    if version.startswith('nextpnr-'):
+        return version.split('-')[1]
+    else:
+        return version

siliconcompiler/tools/openfpgaloader/openfpgaloader.py

@@ -0,0 +1,39 @@
+'''
+The OpenFPGALoader is a universal utility for programming
+FPGAs. Compatible with many boards, cables and FPGA from
+major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin,
+Efinix, Anlogic). openFPGALoader works on Linux, Windows and
+macOS.
+
+Documentation: https://github.com/trabucayre/openFPGALoader
+
+Sources: https://github.com/trabucayre/openFPGALoader
+
+Installation: https://github.com/trabucayre/openFPGALoader
+
+Status: SC integration WIP
+'''
+from siliconcompiler.tools._common import get_tool_task
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    ''' openFPGALoader setup function
+    '''
+
+    # If the 'lock' bit is set, don't reconfigure.
+    tool = 'openfpgaloader'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # tool setup
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '--Version', clobber=False)
+    chip.set('tool', tool, 'version', '0.5.0', clobber=False)
+
+    options = []
+    options.append("inputs" + chip.top() + ".bit")
+    chip.add('tool', tool, 'task', task, 'option', options, step=step, index=index)

siliconcompiler/tools/openroad/cts.py

@@ -0,0 +1,45 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+
+
+def setup(chip):
+    '''
+    Perform clock tree synthesis and timing repair
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    _set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/dfm.py

@@ -0,0 +1,66 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common.asic import get_mainlib
+from siliconcompiler import NodeStatus
+
+
+def setup(chip):
+    '''
+    Design for manufacturing step will insert fill if specified
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    _set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    if not chip.find_files('tool', tool, 'task', task, 'prescript',
+                           step=step, index=index) and \
+            not chip.find_files('tool', tool, 'task', task, 'postscript',
+                                step=step, index=index) and \
+            chip.get('tool', tool, 'task', task, 'var', 'fin_add_fill',
+                     step=step, index=index) == ["true"]:
+        pdk = chip.get('option', 'pdk')
+        stackup = chip.get('option', 'stackup')
+        mainlib = get_mainlib(chip)
+        libtype = chip.get('library', mainlib, 'asic', 'libarch', step=step, index=index)
+
+        if not chip.find_files('pdk', pdk, 'aprtech', tool, stackup, libtype, 'fill'):
+            chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
+            chip.logger.warning(f'{step}{index} will be skipped since there is nothing to do.')
+
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/export.py

@@ -0,0 +1,131 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Generate abstract views (LEF), timing libraries (liberty files),
+    circuit descriptions (CDL), and parasitic annotation files (SPEF)
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    tool = 'openroad'
+    design = chip.top()
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Set thread count to 1 while issue related to write_timing_model segfaulting
+    # when multiple threads are on is resolved.
+    chip.set('tool', tool, 'task', task, 'threads', 1,
+             step=step, index=index, clobber=True)
+
+    stackup = chip.get('option', 'stackup')
+    pdk = chip.get('option', 'pdk')
+
+    targetlibs = get_libraries(chip, 'logic')
+    macrolibs = get_libraries(chip, 'macro')
+
+    # Determine if exporting the cdl
+    set_tool_task_var(chip, param_key='write_cdl',
+                      default_value='false',
+                      schelp='true/false, when true enables writing the CDL file for the design')
+    do_cdl = chip.get('tool', tool, 'task', task, 'var', 'write_cdl',
+                      step=step, index=index)[0] == 'true'
+
+    if do_cdl:
+        chip.add('tool', tool, 'task', task, 'output', design + '.cdl', step=step, index=index)
+        for lib in targetlibs + macrolibs:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ",".join(['library', lib, 'output', stackup, 'cdl']),
+                     step=step, index=index)
+
+    set_tool_task_var(chip, param_key='write_spef',
+                      default_value='true',
+                      schelp='true/false, when true enables writing the SPEF file for the design')
+    do_spef = chip.get('tool', tool, 'task', task, 'var', 'write_spef',
+                       step=step, index=index)[0] == 'true'
+    set_tool_task_var(chip, param_key='use_spef',
+                      default_value=do_spef,
+                      schelp='true/false, when true enables reading in SPEF files.')
+
+    if do_spef:
+        # Require openrcx pex models
+        for corner in chip.get('tool', tool, 'task', task, 'var', 'pex_corners',
+                               step=step, index=index):
+            chip.add('tool', tool, 'task', task, 'require',
+                     ",".join(['pdk', pdk, 'pexmodel', 'openroad-openrcx', stackup, corner]),
+                     step=step, index=index)
+
+        # Add outputs SPEF in the format {design}.{pexcorner}.spef
+        for corner in chip.get('tool', tool, 'task', task, 'var', 'pex_corners',
+                               step=step, index=index):
+            chip.add('tool', tool, 'task', task, 'output', design + '.' + corner + '.spef',
+                     step=step, index=index)
+
+    # Add outputs LEF
+    chip.add('tool', tool, 'task', task, 'output', design + '.lef', step=step, index=index)
+
+    set_tool_task_var(chip, param_key='write_liberty',
+                      default_value='true',
+                      schelp='true/false, when true enables writing the liberty '
+                             'timing model for the design')
+    do_liberty = chip.get('tool', tool, 'task', task, 'var', 'write_liberty',
+                          step=step, index=index)[0] == 'true'
+
+    if do_liberty:
+        # Add outputs liberty model in the format {design}.{libcorner}.lib
+        for corner in chip.getkeys('constraint', 'timing'):
+            chip.add('tool', tool, 'task', task, 'output', design + '.' + corner + '.lib',
+                     step=step, index=index)
+
+    set_tool_task_var(chip, param_key='write_sdf',
+                      default_value='true',
+                      schelp='true/false, when true enables writing the SDF timing model '
+                             'for the design')
+    do_sdf = chip.get('tool', tool, 'task', task, 'var', 'write_sdf',
+                      step=step, index=index)[0] == 'true'
+    if do_sdf:
+        # Add outputs liberty model in the format {design}.{libcorner}.sdf
+        for corner in chip.getkeys('constraint', 'timing'):
+            chip.add('tool', tool, 'task', task, 'output', design + '.' + corner + '.sdf',
+                     step=step, index=index)
+
+    _set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'ir_drop',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)