siliconcompiler 0.26.5__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/__init__.py +24 -0
- siliconcompiler/__main__.py +12 -0
- siliconcompiler/_common.py +49 -0
- siliconcompiler/_metadata.py +36 -0
- siliconcompiler/apps/__init__.py +0 -0
- siliconcompiler/apps/_common.py +76 -0
- siliconcompiler/apps/sc.py +92 -0
- siliconcompiler/apps/sc_dashboard.py +94 -0
- siliconcompiler/apps/sc_issue.py +178 -0
- siliconcompiler/apps/sc_remote.py +199 -0
- siliconcompiler/apps/sc_server.py +39 -0
- siliconcompiler/apps/sc_show.py +142 -0
- siliconcompiler/apps/smake.py +232 -0
- siliconcompiler/checklists/__init__.py +0 -0
- siliconcompiler/checklists/oh_tapeout.py +41 -0
- siliconcompiler/core.py +3221 -0
- siliconcompiler/data/RobotoMono/LICENSE.txt +202 -0
- siliconcompiler/data/RobotoMono/RobotoMono-Regular.ttf +0 -0
- siliconcompiler/data/heartbeat.v +18 -0
- siliconcompiler/data/logo.png +0 -0
- siliconcompiler/flowgraph.py +570 -0
- siliconcompiler/flows/__init__.py +0 -0
- siliconcompiler/flows/_common.py +67 -0
- siliconcompiler/flows/asicflow.py +180 -0
- siliconcompiler/flows/asictopflow.py +38 -0
- siliconcompiler/flows/dvflow.py +86 -0
- siliconcompiler/flows/fpgaflow.py +202 -0
- siliconcompiler/flows/generate_openroad_rcx.py +66 -0
- siliconcompiler/flows/lintflow.py +35 -0
- siliconcompiler/flows/screenshotflow.py +51 -0
- siliconcompiler/flows/showflow.py +59 -0
- siliconcompiler/flows/signoffflow.py +53 -0
- siliconcompiler/flows/synflow.py +128 -0
- siliconcompiler/fpgas/__init__.py +0 -0
- siliconcompiler/fpgas/lattice_ice40.py +42 -0
- siliconcompiler/fpgas/vpr_example.py +109 -0
- siliconcompiler/issue.py +300 -0
- siliconcompiler/libs/__init__.py +0 -0
- siliconcompiler/libs/asap7sc7p5t.py +8 -0
- siliconcompiler/libs/gf180mcu.py +8 -0
- siliconcompiler/libs/nangate45.py +8 -0
- siliconcompiler/libs/sky130hd.py +8 -0
- siliconcompiler/libs/sky130io.py +8 -0
- siliconcompiler/package.py +412 -0
- siliconcompiler/pdks/__init__.py +0 -0
- siliconcompiler/pdks/asap7.py +8 -0
- siliconcompiler/pdks/freepdk45.py +8 -0
- siliconcompiler/pdks/gf180.py +8 -0
- siliconcompiler/pdks/skywater130.py +8 -0
- siliconcompiler/remote/__init__.py +36 -0
- siliconcompiler/remote/client.py +891 -0
- siliconcompiler/remote/schema.py +106 -0
- siliconcompiler/remote/server.py +507 -0
- siliconcompiler/remote/server_schema/requests/cancel_job.json +51 -0
- siliconcompiler/remote/server_schema/requests/check_progress.json +61 -0
- siliconcompiler/remote/server_schema/requests/check_server.json +38 -0
- siliconcompiler/remote/server_schema/requests/delete_job.json +51 -0
- siliconcompiler/remote/server_schema/requests/get_results.json +48 -0
- siliconcompiler/remote/server_schema/requests/remote_run.json +40 -0
- siliconcompiler/remote/server_schema/responses/cancel_job.json +18 -0
- siliconcompiler/remote/server_schema/responses/check_progress.json +30 -0
- siliconcompiler/remote/server_schema/responses/check_server.json +32 -0
- siliconcompiler/remote/server_schema/responses/delete_job.json +18 -0
- siliconcompiler/remote/server_schema/responses/get_results.json +21 -0
- siliconcompiler/remote/server_schema/responses/remote_run.json +25 -0
- siliconcompiler/report/__init__.py +13 -0
- siliconcompiler/report/html_report.py +74 -0
- siliconcompiler/report/report.py +355 -0
- siliconcompiler/report/streamlit_report.py +137 -0
- siliconcompiler/report/streamlit_viewer.py +944 -0
- siliconcompiler/report/summary_image.py +117 -0
- siliconcompiler/report/summary_table.py +105 -0
- siliconcompiler/report/utils.py +163 -0
- siliconcompiler/scheduler/__init__.py +2092 -0
- siliconcompiler/scheduler/docker_runner.py +253 -0
- siliconcompiler/scheduler/run_node.py +138 -0
- siliconcompiler/scheduler/send_messages.py +178 -0
- siliconcompiler/scheduler/slurm.py +208 -0
- siliconcompiler/scheduler/validation/email_credentials.json +54 -0
- siliconcompiler/schema/__init__.py +7 -0
- siliconcompiler/schema/schema_cfg.py +4014 -0
- siliconcompiler/schema/schema_obj.py +1841 -0
- siliconcompiler/schema/utils.py +93 -0
- siliconcompiler/sphinx_ext/__init__.py +0 -0
- siliconcompiler/sphinx_ext/dynamicgen.py +1006 -0
- siliconcompiler/sphinx_ext/schemagen.py +221 -0
- siliconcompiler/sphinx_ext/utils.py +166 -0
- siliconcompiler/targets/__init__.py +0 -0
- siliconcompiler/targets/asap7_demo.py +68 -0
- siliconcompiler/targets/asic_demo.py +38 -0
- siliconcompiler/targets/fpgaflow_demo.py +47 -0
- siliconcompiler/targets/freepdk45_demo.py +59 -0
- siliconcompiler/targets/gf180_demo.py +77 -0
- siliconcompiler/targets/skywater130_demo.py +70 -0
- siliconcompiler/templates/email/general.j2 +66 -0
- siliconcompiler/templates/email/summary.j2 +43 -0
- siliconcompiler/templates/issue/README.txt +26 -0
- siliconcompiler/templates/issue/run.sh +6 -0
- siliconcompiler/templates/report/bootstrap.min.css +7 -0
- siliconcompiler/templates/report/bootstrap.min.js +7 -0
- siliconcompiler/templates/report/bootstrap_LICENSE.md +24 -0
- siliconcompiler/templates/report/sc_report.j2 +427 -0
- siliconcompiler/templates/slurm/run.sh +9 -0
- siliconcompiler/templates/tcl/manifest.tcl.j2 +137 -0
- siliconcompiler/tools/__init__.py +0 -0
- siliconcompiler/tools/_common/__init__.py +432 -0
- siliconcompiler/tools/_common/asic.py +115 -0
- siliconcompiler/tools/_common/sdc/sc_constraints.sdc +76 -0
- siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl +63 -0
- siliconcompiler/tools/bambu/bambu.py +32 -0
- siliconcompiler/tools/bambu/convert.py +77 -0
- siliconcompiler/tools/bluespec/bluespec.py +40 -0
- siliconcompiler/tools/bluespec/convert.py +103 -0
- siliconcompiler/tools/builtin/_common.py +155 -0
- siliconcompiler/tools/builtin/builtin.py +26 -0
- siliconcompiler/tools/builtin/concatenate.py +85 -0
- siliconcompiler/tools/builtin/join.py +27 -0
- siliconcompiler/tools/builtin/maximum.py +46 -0
- siliconcompiler/tools/builtin/minimum.py +57 -0
- siliconcompiler/tools/builtin/mux.py +70 -0
- siliconcompiler/tools/builtin/nop.py +38 -0
- siliconcompiler/tools/builtin/verify.py +83 -0
- siliconcompiler/tools/chisel/SCDriver.scala +10 -0
- siliconcompiler/tools/chisel/build.sbt +27 -0
- siliconcompiler/tools/chisel/chisel.py +37 -0
- siliconcompiler/tools/chisel/convert.py +140 -0
- siliconcompiler/tools/execute/exec_input.py +41 -0
- siliconcompiler/tools/execute/execute.py +17 -0
- siliconcompiler/tools/genfasm/bitstream.py +61 -0
- siliconcompiler/tools/genfasm/genfasm.py +40 -0
- siliconcompiler/tools/ghdl/convert.py +87 -0
- siliconcompiler/tools/ghdl/ghdl.py +41 -0
- siliconcompiler/tools/icarus/compile.py +87 -0
- siliconcompiler/tools/icarus/icarus.py +36 -0
- siliconcompiler/tools/icepack/bitstream.py +20 -0
- siliconcompiler/tools/icepack/icepack.py +43 -0
- siliconcompiler/tools/klayout/export.py +117 -0
- siliconcompiler/tools/klayout/klayout.py +119 -0
- siliconcompiler/tools/klayout/klayout_export.py +205 -0
- siliconcompiler/tools/klayout/klayout_operations.py +363 -0
- siliconcompiler/tools/klayout/klayout_show.py +242 -0
- siliconcompiler/tools/klayout/klayout_utils.py +176 -0
- siliconcompiler/tools/klayout/operations.py +194 -0
- siliconcompiler/tools/klayout/screenshot.py +98 -0
- siliconcompiler/tools/klayout/show.py +101 -0
- siliconcompiler/tools/magic/drc.py +49 -0
- siliconcompiler/tools/magic/extspice.py +19 -0
- siliconcompiler/tools/magic/magic.py +85 -0
- siliconcompiler/tools/magic/sc_drc.tcl +96 -0
- siliconcompiler/tools/magic/sc_extspice.tcl +54 -0
- siliconcompiler/tools/magic/sc_magic.tcl +47 -0
- siliconcompiler/tools/montage/montage.py +30 -0
- siliconcompiler/tools/montage/tile.py +66 -0
- siliconcompiler/tools/netgen/count_lvs.py +132 -0
- siliconcompiler/tools/netgen/lvs.py +90 -0
- siliconcompiler/tools/netgen/netgen.py +36 -0
- siliconcompiler/tools/netgen/sc_lvs.tcl +46 -0
- siliconcompiler/tools/nextpnr/apr.py +24 -0
- siliconcompiler/tools/nextpnr/nextpnr.py +59 -0
- siliconcompiler/tools/openfpgaloader/openfpgaloader.py +39 -0
- siliconcompiler/tools/openroad/__init__.py +0 -0
- siliconcompiler/tools/openroad/cts.py +45 -0
- siliconcompiler/tools/openroad/dfm.py +66 -0
- siliconcompiler/tools/openroad/export.py +131 -0
- siliconcompiler/tools/openroad/floorplan.py +70 -0
- siliconcompiler/tools/openroad/openroad.py +977 -0
- siliconcompiler/tools/openroad/physyn.py +27 -0
- siliconcompiler/tools/openroad/place.py +41 -0
- siliconcompiler/tools/openroad/rcx_bench.py +95 -0
- siliconcompiler/tools/openroad/rcx_extract.py +34 -0
- siliconcompiler/tools/openroad/route.py +45 -0
- siliconcompiler/tools/openroad/screenshot.py +60 -0
- siliconcompiler/tools/openroad/scripts/sc_apr.tcl +499 -0
- siliconcompiler/tools/openroad/scripts/sc_cts.tcl +64 -0
- siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +20 -0
- siliconcompiler/tools/openroad/scripts/sc_export.tcl +98 -0
- siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +413 -0
- siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +158 -0
- siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +7 -0
- siliconcompiler/tools/openroad/scripts/sc_place.tcl +84 -0
- siliconcompiler/tools/openroad/scripts/sc_procs.tcl +423 -0
- siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +63 -0
- siliconcompiler/tools/openroad/scripts/sc_rcx_bench.tcl +20 -0
- siliconcompiler/tools/openroad/scripts/sc_rcx_extract.tcl +12 -0
- siliconcompiler/tools/openroad/scripts/sc_route.tcl +133 -0
- siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +21 -0
- siliconcompiler/tools/openroad/scripts/sc_write.tcl +5 -0
- siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +361 -0
- siliconcompiler/tools/openroad/show.py +94 -0
- siliconcompiler/tools/openroad/templates/pex.tcl +8 -0
- siliconcompiler/tools/opensta/__init__.py +101 -0
- siliconcompiler/tools/opensta/report_libraries.py +28 -0
- siliconcompiler/tools/opensta/scripts/sc_procs.tcl +47 -0
- siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl +74 -0
- siliconcompiler/tools/opensta/scripts/sc_timing.tcl +268 -0
- siliconcompiler/tools/opensta/timing.py +214 -0
- siliconcompiler/tools/slang/__init__.py +49 -0
- siliconcompiler/tools/slang/lint.py +101 -0
- siliconcompiler/tools/surelog/__init__.py +123 -0
- siliconcompiler/tools/surelog/parse.py +183 -0
- siliconcompiler/tools/surelog/templates/output.v +7 -0
- siliconcompiler/tools/sv2v/convert.py +46 -0
- siliconcompiler/tools/sv2v/sv2v.py +37 -0
- siliconcompiler/tools/template/template.py +125 -0
- siliconcompiler/tools/verilator/compile.py +139 -0
- siliconcompiler/tools/verilator/lint.py +19 -0
- siliconcompiler/tools/verilator/parse.py +27 -0
- siliconcompiler/tools/verilator/verilator.py +172 -0
- siliconcompiler/tools/vivado/__init__.py +7 -0
- siliconcompiler/tools/vivado/bitstream.py +21 -0
- siliconcompiler/tools/vivado/place.py +21 -0
- siliconcompiler/tools/vivado/route.py +21 -0
- siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl +6 -0
- siliconcompiler/tools/vivado/scripts/sc_place.tcl +2 -0
- siliconcompiler/tools/vivado/scripts/sc_route.tcl +4 -0
- siliconcompiler/tools/vivado/scripts/sc_run.tcl +45 -0
- siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl +25 -0
- siliconcompiler/tools/vivado/syn_fpga.py +20 -0
- siliconcompiler/tools/vivado/vivado.py +147 -0
- siliconcompiler/tools/vpr/_json_constraint.py +63 -0
- siliconcompiler/tools/vpr/_xml_constraint.py +109 -0
- siliconcompiler/tools/vpr/place.py +137 -0
- siliconcompiler/tools/vpr/route.py +124 -0
- siliconcompiler/tools/vpr/screenshot.py +54 -0
- siliconcompiler/tools/vpr/show.py +88 -0
- siliconcompiler/tools/vpr/vpr.py +357 -0
- siliconcompiler/tools/xyce/xyce.py +36 -0
- siliconcompiler/tools/yosys/lec.py +56 -0
- siliconcompiler/tools/yosys/prepareLib.py +59 -0
- siliconcompiler/tools/yosys/sc_lec.tcl +84 -0
- siliconcompiler/tools/yosys/sc_syn.tcl +79 -0
- siliconcompiler/tools/yosys/syn_asic.py +565 -0
- siliconcompiler/tools/yosys/syn_asic.tcl +377 -0
- siliconcompiler/tools/yosys/syn_asic_fpga_shared.tcl +31 -0
- siliconcompiler/tools/yosys/syn_fpga.py +146 -0
- siliconcompiler/tools/yosys/syn_fpga.tcl +233 -0
- siliconcompiler/tools/yosys/syn_strategies.tcl +81 -0
- siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v +39 -0
- siliconcompiler/tools/yosys/templates/abc.const +2 -0
- siliconcompiler/tools/yosys/yosys.py +147 -0
- siliconcompiler/units.py +259 -0
- siliconcompiler/use.py +177 -0
- siliconcompiler/utils/__init__.py +423 -0
- siliconcompiler/utils/asic.py +158 -0
- siliconcompiler/utils/showtools.py +25 -0
- siliconcompiler-0.26.5.dist-info/LICENSE +190 -0
- siliconcompiler-0.26.5.dist-info/METADATA +195 -0
- siliconcompiler-0.26.5.dist-info/RECORD +251 -0
- siliconcompiler-0.26.5.dist-info/WHEEL +5 -0
- siliconcompiler-0.26.5.dist-info/entry_points.txt +12 -0
- siliconcompiler-0.26.5.dist-info/top_level.txt +1 -0
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from siliconcompiler._common import NodeStatus, SiliconCompilerError
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from siliconcompiler.utils import sc_open
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from siliconcompiler.core import Chip
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from siliconcompiler.schema import Schema
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from siliconcompiler._metadata import version as __version__
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from siliconcompiler.use import PDK, FPGA, Library, Flow, Checklist
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__all__ = [
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"__version__",
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"Chip",
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"SiliconCompilerError",
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"NodeStatus",
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"PDK",
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"FPGA",
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"Library",
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"Flow",
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"Checklist",
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"Schema",
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]
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class NodeStatus():
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# node ready to run and waiting
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# node running
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# node exit status
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SUCCESS = 'success'
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ERROR = 'error'
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SKIPPED = 'skipped'
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TIMEOUT = 'timeout'
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def is_done(status):
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return status in (
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NodeStatus.SUCCESS,
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NodeStatus.ERROR,
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NodeStatus.SKIPPED,
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NodeStatus.TIMEOUT
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)
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def is_running(status):
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NodeStatus.QUEUED,
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)
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def is_waiting(status):
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)
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###############################################################################
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# Package Customization classes
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###############################################################################
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class SiliconCompilerError(Exception):
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''' Minimal Exception wrapper used to raise sc runtime errors.
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'''
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super(Exception, self).__init__(message)
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# Version number following semver standard.
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version = '0.26.5'
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# Default server address for remote runs, if unspecified.
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default_server = 'https://server.siliconcompiler.com'
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# This is the list of significant contributors to SiliconCompiler in
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# chronological order.
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#
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# especially since many employees of one corporation may be contributing.
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# To see the full list of contributors, see the git revision history
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authors = [
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'Andreas Olofsson',
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'William Ransohoff',
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'Noah Moroze',
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'Zachary Yedidia',
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'Massimiliano Giacometti',
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'Kimia Talaei',
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'Peter Gadfort',
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'Aulihan Teng',
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'Peter Grossmann',
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'Gabriel Aguirre',
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'Martin Troiber'
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]
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# CLI entry banner autogenerated using pyfiglet.
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# >> pyfiglet.figlet_format("Silicon Compiler")
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banner = r'''
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____ _ _ _ ____ _ _
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/ ___|(_) (_) ___ ___ _ __ / ___|___ _ __ ___ _ __ (_) | ___ _ __
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\___ \| | | |/ __/ _ \| '_ \ | | / _ \| '_ ` _ \| '_ \| | |/ _ \ '__|
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___) | | | | (_| (_) | | | | | |__| (_) | | | | | | |_) | | | __/ |
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|____/|_|_|_|\___\___/|_| |_| \____\___/|_| |_| |_| .__/|_|_|\___|_|
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'''
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import os
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def manifest_switches():
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'''
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Returns a list of manifest switches that can be used
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to find the manifest based on their values
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'''
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return ['-design',
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'-cfg',
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'-arg_step',
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'-arg_index',
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'-jobname']
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def load_manifest(chip, src_file):
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manifest = None
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if (src_file is not None) and (not chip.get('option', 'cfg')):
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if not os.path.exists(src_file):
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chip.logger.error(f'{src_file} cannot be found.')
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return False
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# only autoload manifest if user doesn't supply manually
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manifest = _get_manifest(os.path.dirname(src_file))
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if not manifest:
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design = os.path.splitext(os.path.basename(src_file))[0]
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|
27
|
+
chip.logger.error(f'Unable to automatically find manifest for design {design}. '
|
|
28
|
+
'Please provide a manifest explicitly using -cfg.')
|
|
29
|
+
return False
|
|
30
|
+
elif not chip.get('option', 'cfg'):
|
|
31
|
+
manifest = _get_manifest_from_design(chip)
|
|
32
|
+
if not manifest:
|
|
33
|
+
chip.logger.error(f'Could not find manifest for {chip.design}')
|
|
34
|
+
return False
|
|
35
|
+
|
|
36
|
+
if manifest:
|
|
37
|
+
chip.logger.info(f'Loading manifest: {manifest}')
|
|
38
|
+
chip.read_manifest(manifest)
|
|
39
|
+
return True
|
|
40
|
+
|
|
41
|
+
|
|
42
|
+
def _get_manifest(dirname, design='*'):
|
|
43
|
+
# pkg.json file may have a different name from the design due to the entrypoint
|
|
44
|
+
glob_paths = [os.path.join(dirname, f'{design}.pkg.json'),
|
|
45
|
+
os.path.join(dirname, 'outputs', f'{design}.pkg.json')]
|
|
46
|
+
manifest = None
|
|
47
|
+
for path in glob_paths:
|
|
48
|
+
manifest = glob.glob(path)
|
|
49
|
+
if manifest:
|
|
50
|
+
manifest = manifest[0]
|
|
51
|
+
break
|
|
52
|
+
|
|
53
|
+
if not manifest or not os.path.isfile(manifest):
|
|
54
|
+
return None
|
|
55
|
+
return manifest
|
|
56
|
+
|
|
57
|
+
|
|
58
|
+
def _get_manifest_from_design(chip):
|
|
59
|
+
for jobname, step, index in [
|
|
60
|
+
(chip.get('option', 'jobname'),
|
|
61
|
+
chip.get('arg', 'step'),
|
|
62
|
+
chip.get('arg', 'index')),
|
|
63
|
+
(chip.get('option', 'jobname'),
|
|
64
|
+
None,
|
|
65
|
+
None),
|
|
66
|
+
(chip.schema.get_default('option', 'jobname'),
|
|
67
|
+
chip.get('arg', 'step'),
|
|
68
|
+
chip.get('arg', 'index')),
|
|
69
|
+
(chip.schema.get_default('option', 'jobname'),
|
|
70
|
+
None,
|
|
71
|
+
None)]:
|
|
72
|
+
manifest = _get_manifest(chip.getworkdir(jobname=jobname, step=step, index=index))
|
|
73
|
+
|
|
74
|
+
if manifest:
|
|
75
|
+
return manifest
|
|
76
|
+
return None
|
|
@@ -0,0 +1,92 @@
|
|
|
1
|
+
# Copyright 2020 Silicon Compiler Authors. All Rights Reserved.
|
|
2
|
+
|
|
3
|
+
# Standard Modules
|
|
4
|
+
import os
|
|
5
|
+
import sys
|
|
6
|
+
|
|
7
|
+
import siliconcompiler
|
|
8
|
+
from siliconcompiler.utils import get_default_iomap
|
|
9
|
+
from siliconcompiler.targets import skywater130_demo
|
|
10
|
+
from siliconcompiler import SiliconCompilerError
|
|
11
|
+
|
|
12
|
+
|
|
13
|
+
###########################
|
|
14
|
+
def main():
|
|
15
|
+
progname = "sc"
|
|
16
|
+
description = """
|
|
17
|
+
------------------------------------------------------------
|
|
18
|
+
SiliconCompiler is an open source compiler framework that
|
|
19
|
+
aims to enable automated translation from source code to
|
|
20
|
+
silicon.
|
|
21
|
+
|
|
22
|
+
The sc program includes the following steps.
|
|
23
|
+
|
|
24
|
+
1. Read command line arguments
|
|
25
|
+
2. If not set, 'design' is set to base of first source file.
|
|
26
|
+
3. If not set, 'target' is set to 'skywater130_demo'.
|
|
27
|
+
4. Run compilation
|
|
28
|
+
5. Display summary
|
|
29
|
+
|
|
30
|
+
Sources: https://github.com/siliconcompiler/siliconcompiler
|
|
31
|
+
------------------------------------------------------------
|
|
32
|
+
"""
|
|
33
|
+
# TODO: this is a hack to get around design name requirement: since legal
|
|
34
|
+
# design names probably can't contain spaces, we can detect if it is unset.
|
|
35
|
+
UNSET_DESIGN = ' unset '
|
|
36
|
+
|
|
37
|
+
# Create a base chip class.
|
|
38
|
+
chip = siliconcompiler.Chip(UNSET_DESIGN)
|
|
39
|
+
|
|
40
|
+
# Read command-line inputs and generate Chip objects to run the flow on.
|
|
41
|
+
try:
|
|
42
|
+
chip.create_cmdline(progname,
|
|
43
|
+
description=description,
|
|
44
|
+
input_map=get_default_iomap())
|
|
45
|
+
except Exception as e:
|
|
46
|
+
chip.logger.error(e)
|
|
47
|
+
return 1
|
|
48
|
+
|
|
49
|
+
# Set design if none specified
|
|
50
|
+
if chip.get('design') == UNSET_DESIGN:
|
|
51
|
+
topfile = None
|
|
52
|
+
for sourceset in ('rtl', 'hll'):
|
|
53
|
+
for filetype in chip.getkeys('input', sourceset):
|
|
54
|
+
all_vals = chip.schema._getvals('input', sourceset, filetype)
|
|
55
|
+
if all_vals:
|
|
56
|
+
# just look at first value
|
|
57
|
+
sources, _, _ = all_vals[0]
|
|
58
|
+
# grab first source
|
|
59
|
+
topfile = sources[0]
|
|
60
|
+
break
|
|
61
|
+
if topfile:
|
|
62
|
+
break
|
|
63
|
+
|
|
64
|
+
if not topfile:
|
|
65
|
+
chip.logger.error('Invalid arguments: either specify -design or provide sources.')
|
|
66
|
+
return 1
|
|
67
|
+
|
|
68
|
+
topmodule = os.path.splitext(os.path.basename(topfile))[0]
|
|
69
|
+
chip.set('design', topmodule)
|
|
70
|
+
|
|
71
|
+
# Set demo target if none specified
|
|
72
|
+
if not chip.get('option', 'target'):
|
|
73
|
+
chip.load_target(skywater130_demo)
|
|
74
|
+
|
|
75
|
+
try:
|
|
76
|
+
# Run flow
|
|
77
|
+
chip.run()
|
|
78
|
+
|
|
79
|
+
# Print Job Summary
|
|
80
|
+
chip.summary()
|
|
81
|
+
except SiliconCompilerError:
|
|
82
|
+
return 1
|
|
83
|
+
except Exception as e:
|
|
84
|
+
chip.logger.error(e)
|
|
85
|
+
return 1
|
|
86
|
+
|
|
87
|
+
return 0
|
|
88
|
+
|
|
89
|
+
|
|
90
|
+
#########################
|
|
91
|
+
if __name__ == "__main__":
|
|
92
|
+
sys.exit(main())
|
|
@@ -0,0 +1,94 @@
|
|
|
1
|
+
# Copyright 2023 Silicon Compiler Authors. All Rights Reserved.
|
|
2
|
+
import sys
|
|
3
|
+
import siliconcompiler
|
|
4
|
+
import os
|
|
5
|
+
from siliconcompiler.apps._common import load_manifest, manifest_switches
|
|
6
|
+
|
|
7
|
+
|
|
8
|
+
def main():
|
|
9
|
+
progname = "sc-dashboard"
|
|
10
|
+
description = """
|
|
11
|
+
-----------------------------------------------------------
|
|
12
|
+
SC app to open a dashboard for a given manifest.
|
|
13
|
+
|
|
14
|
+
To open:
|
|
15
|
+
sc-dashboard -cfg <path to manifest>
|
|
16
|
+
|
|
17
|
+
To specify a different port than the default:
|
|
18
|
+
sc-dashboard -cfg <path to manifest> -port 10000
|
|
19
|
+
|
|
20
|
+
To include another chip object to compare to:
|
|
21
|
+
sc-dashboard -cfg <path to manifest> -graph_cfg <name of manifest> <path to other manifest>
|
|
22
|
+
-graph_cfg <path to other manifest> ...
|
|
23
|
+
-----------------------------------------------------------
|
|
24
|
+
"""
|
|
25
|
+
|
|
26
|
+
# TODO: this is a hack to get around design name requirement: since legal
|
|
27
|
+
# design names probably can't contain spaces, we can detect if it is unset.
|
|
28
|
+
UNSET_DESIGN = ' unset '
|
|
29
|
+
|
|
30
|
+
# Create a base chip class.
|
|
31
|
+
chip = siliconcompiler.Chip(UNSET_DESIGN)
|
|
32
|
+
|
|
33
|
+
dashboard_arguments = {
|
|
34
|
+
"-port": {'type': int,
|
|
35
|
+
'help': 'port to open the dashboard app on',
|
|
36
|
+
'metavar': '<port>',
|
|
37
|
+
'sc_print': False},
|
|
38
|
+
"-graph_cfg": {'type': str,
|
|
39
|
+
'nargs': '+',
|
|
40
|
+
'action': 'append',
|
|
41
|
+
'help': 'chip name - optional, path to chip manifest (json)',
|
|
42
|
+
'metavar': '<[manifest name, manifest path>',
|
|
43
|
+
'sc_print': False}
|
|
44
|
+
}
|
|
45
|
+
|
|
46
|
+
try:
|
|
47
|
+
switches = chip.create_cmdline(
|
|
48
|
+
progname,
|
|
49
|
+
switchlist=[*manifest_switches(),
|
|
50
|
+
'-loglevel'],
|
|
51
|
+
description=description,
|
|
52
|
+
additional_args=dashboard_arguments)
|
|
53
|
+
except Exception as e:
|
|
54
|
+
chip.logger.error(e)
|
|
55
|
+
return 1
|
|
56
|
+
|
|
57
|
+
# Error checking
|
|
58
|
+
design = chip.get('design')
|
|
59
|
+
if design == UNSET_DESIGN:
|
|
60
|
+
chip.logger.error('Design not loaded')
|
|
61
|
+
return 1
|
|
62
|
+
|
|
63
|
+
if not load_manifest(chip, None):
|
|
64
|
+
return 1
|
|
65
|
+
|
|
66
|
+
graph_chips = []
|
|
67
|
+
if switches['graph_cfg']:
|
|
68
|
+
for i, name_and_file_path in enumerate(switches['graph_cfg']):
|
|
69
|
+
args = len(name_and_file_path)
|
|
70
|
+
if args == 0:
|
|
71
|
+
continue
|
|
72
|
+
elif args == 1:
|
|
73
|
+
name = f'cfg{i}'
|
|
74
|
+
file_path = name_and_file_path[0]
|
|
75
|
+
elif args == 2:
|
|
76
|
+
name = name_and_file_path[0]
|
|
77
|
+
file_path = name_and_file_path[1]
|
|
78
|
+
else:
|
|
79
|
+
raise ValueError(('graph_cfg accepts a max of 2 values, you supplied'
|
|
80
|
+
f' {args} in "-graph_cfg {name_and_file_path}"'))
|
|
81
|
+
if not os.path.isfile(file_path):
|
|
82
|
+
raise ValueError(f'not a valid file path : {file_path}')
|
|
83
|
+
graph_chip = siliconcompiler.core.Chip(design='')
|
|
84
|
+
graph_chip.read_manifest(file_path)
|
|
85
|
+
graph_chips.append({'chip': graph_chip, 'name': name})
|
|
86
|
+
|
|
87
|
+
chip._dashboard(wait=True, port=switches['port'], graph_chips=graph_chips)
|
|
88
|
+
|
|
89
|
+
return 0
|
|
90
|
+
|
|
91
|
+
|
|
92
|
+
#########################
|
|
93
|
+
if __name__ == "__main__":
|
|
94
|
+
sys.exit(main())
|
|
@@ -0,0 +1,178 @@
|
|
|
1
|
+
# Copyright 2023 Silicon Compiler Authors. All Rights Reserved.
|
|
2
|
+
import sys
|
|
3
|
+
import os
|
|
4
|
+
import siliconcompiler
|
|
5
|
+
import tarfile
|
|
6
|
+
import json
|
|
7
|
+
import importlib
|
|
8
|
+
from siliconcompiler.scheduler import _runtask, _executenode
|
|
9
|
+
from siliconcompiler.issue import generate_testcase
|
|
10
|
+
from siliconcompiler.tools._common import get_tool_task
|
|
11
|
+
|
|
12
|
+
|
|
13
|
+
def main():
|
|
14
|
+
progname = "sc-issue"
|
|
15
|
+
chip = siliconcompiler.Chip(progname)
|
|
16
|
+
switchlist = ['-cfg',
|
|
17
|
+
'-arg_step',
|
|
18
|
+
'-arg_index',
|
|
19
|
+
'-tool_task_var',
|
|
20
|
+
'-tool_task_option',
|
|
21
|
+
'-loglevel']
|
|
22
|
+
description = """
|
|
23
|
+
-----------------------------------------------------------
|
|
24
|
+
Restricted SC app that generates a sharable testcase from a
|
|
25
|
+
failed flow or runs an issue generated with this program.
|
|
26
|
+
|
|
27
|
+
To generate a testcase, use:
|
|
28
|
+
sc-issue -cfg <stepdir>/outputs/<design>.pkg.json
|
|
29
|
+
|
|
30
|
+
or include a different step/index than what the cfg_file is pointing to:
|
|
31
|
+
sc-issue -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
|
|
32
|
+
|
|
33
|
+
or include specific libraries while excluding others:
|
|
34
|
+
sc-issue -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
|
|
35
|
+
|
|
36
|
+
To run a testcase, use:
|
|
37
|
+
sc-issue -run -file sc_issue_<...>.tar.gz
|
|
38
|
+
-----------------------------------------------------------
|
|
39
|
+
""" # noqa E501
|
|
40
|
+
|
|
41
|
+
issue_arguments = {
|
|
42
|
+
'-exclude_libraries': {'action': 'store_true',
|
|
43
|
+
'help': 'flag to ensure libraries are excluded in the testcase',
|
|
44
|
+
'sc_print': False},
|
|
45
|
+
'-exclude_pdks': {'action': 'store_true',
|
|
46
|
+
'help': 'flag to ensure pdks are excluded in the testcase',
|
|
47
|
+
'sc_print': False},
|
|
48
|
+
'-hash_files': {'action': 'store_true',
|
|
49
|
+
'help': 'flag to hash the files in the schema before generating '
|
|
50
|
+
'the manifest',
|
|
51
|
+
'sc_print': False},
|
|
52
|
+
|
|
53
|
+
'-run': {'action': 'store_true',
|
|
54
|
+
'help': 'run a provided testcase',
|
|
55
|
+
'sc_print': False},
|
|
56
|
+
|
|
57
|
+
'-use': {'action': 'append',
|
|
58
|
+
'help': 'modules to load into test run',
|
|
59
|
+
'metavar': '<module>',
|
|
60
|
+
'sc_print': False},
|
|
61
|
+
|
|
62
|
+
'-add_library': {'action': 'append',
|
|
63
|
+
'help': 'library to include in the testcase, if not provided all '
|
|
64
|
+
'libraries will be added according to the -exclude_libraries flag',
|
|
65
|
+
'metavar': '<library>',
|
|
66
|
+
'sc_print': False},
|
|
67
|
+
'-add_pdk': {'action': 'append',
|
|
68
|
+
'help': 'pdk to include in the testcase, if not provided all libraries '
|
|
69
|
+
'will be added according to the -exclude_pdks flag',
|
|
70
|
+
'metavar': '<pdk>',
|
|
71
|
+
'sc_print': False},
|
|
72
|
+
|
|
73
|
+
'-file': {'help': 'filename for the generated testcase',
|
|
74
|
+
'metavar': '<file>',
|
|
75
|
+
'sc_print': False},
|
|
76
|
+
}
|
|
77
|
+
|
|
78
|
+
try:
|
|
79
|
+
switches = chip.create_cmdline(progname,
|
|
80
|
+
switchlist=switchlist,
|
|
81
|
+
description=description,
|
|
82
|
+
additional_args=issue_arguments)
|
|
83
|
+
except Exception as e:
|
|
84
|
+
chip.logger.error(e)
|
|
85
|
+
return 1
|
|
86
|
+
|
|
87
|
+
if not switches['run']:
|
|
88
|
+
step = chip.get('arg', 'step')
|
|
89
|
+
index = chip.get('arg', 'index')
|
|
90
|
+
|
|
91
|
+
if not step:
|
|
92
|
+
chip.logger.error('Unable to determine step from manifest')
|
|
93
|
+
if not index:
|
|
94
|
+
chip.logger.error('Unable to determine index from manifest')
|
|
95
|
+
if not step or not index:
|
|
96
|
+
# Exit out
|
|
97
|
+
return 1
|
|
98
|
+
|
|
99
|
+
generate_testcase(chip,
|
|
100
|
+
step,
|
|
101
|
+
index,
|
|
102
|
+
switches['file'],
|
|
103
|
+
include_pdks=not switches['exclude_pdks'],
|
|
104
|
+
include_specific_pdks=switches['add_pdk'],
|
|
105
|
+
include_libraries=not switches['exclude_libraries'],
|
|
106
|
+
include_specific_libraries=switches['add_library'],
|
|
107
|
+
hash_files=switches['hash_files'])
|
|
108
|
+
|
|
109
|
+
return 0
|
|
110
|
+
|
|
111
|
+
if switches['run']:
|
|
112
|
+
if not switches['file']:
|
|
113
|
+
raise ValueError('-file must be provided')
|
|
114
|
+
|
|
115
|
+
test_dir = os.path.basename(switches['file']).split('.')[0]
|
|
116
|
+
with tarfile.open(switches['file'], 'r:gz') as f:
|
|
117
|
+
f.extractall(path='.')
|
|
118
|
+
|
|
119
|
+
chip.read_manifest(f'{test_dir}/orig_manifest.json')
|
|
120
|
+
|
|
121
|
+
with open(f'{test_dir}/issue.json', 'r') as f:
|
|
122
|
+
issue_info = json.load(f)
|
|
123
|
+
|
|
124
|
+
# Report major information
|
|
125
|
+
sc_version = issue_info['version']['sc']
|
|
126
|
+
if 'commit' in issue_info['version']['git']:
|
|
127
|
+
sc_source = issue_info['version']['git']['commit']
|
|
128
|
+
else:
|
|
129
|
+
sc_source = 'installed'
|
|
130
|
+
|
|
131
|
+
chip.logger.info(f"Design: {chip.design}")
|
|
132
|
+
chip.logger.info(f"SiliconCompiler version: {sc_version} / {sc_source}")
|
|
133
|
+
chip.logger.info(f"Schema version: {issue_info['version']['schema']}")
|
|
134
|
+
chip.logger.info(f"Python version: {issue_info['python']['version']}")
|
|
135
|
+
|
|
136
|
+
sc_machine = issue_info['machine']
|
|
137
|
+
sc_os = sc_machine['system']
|
|
138
|
+
if 'distro' in sc_machine:
|
|
139
|
+
sc_os += f" {sc_machine['distro']}"
|
|
140
|
+
sc_os += f" {sc_machine['osversion']} {sc_machine['arch']} {sc_machine['kernelversion']}"
|
|
141
|
+
chip.logger.info(f"Machine: {sc_os}")
|
|
142
|
+
chip.logger.info(f"Date: {issue_info['date']}")
|
|
143
|
+
|
|
144
|
+
step = issue_info['run']['step']
|
|
145
|
+
index = issue_info['run']['index']
|
|
146
|
+
|
|
147
|
+
chip.set('arg', 'step', step)
|
|
148
|
+
chip.set('arg', 'index', index)
|
|
149
|
+
tool, task = get_tool_task(chip, step, index)
|
|
150
|
+
chip.logger.info(f'Preparing run for {step}{index} - {tool}/{task}')
|
|
151
|
+
|
|
152
|
+
# Modify run environment to point to extracted files
|
|
153
|
+
builddir_key = ['option', 'builddir']
|
|
154
|
+
new_builddir = f"{test_dir}/{chip.get(*builddir_key)}"
|
|
155
|
+
chip.logger.info(f"Changing {builddir_key} to '{new_builddir}'")
|
|
156
|
+
chip.set(*builddir_key, new_builddir)
|
|
157
|
+
|
|
158
|
+
if switches['use']:
|
|
159
|
+
for use in switches['use']:
|
|
160
|
+
try:
|
|
161
|
+
module = importlib.import_module(use)
|
|
162
|
+
chip.logger.info(f"Loading '{use}' module")
|
|
163
|
+
chip.use(module)
|
|
164
|
+
except ModuleNotFoundError:
|
|
165
|
+
chip.logger.error(f"Unable to use '{use}' module")
|
|
166
|
+
|
|
167
|
+
# Run task
|
|
168
|
+
# Rerun setup task, assumed to be running in its own thread so
|
|
169
|
+
# multiprocess is not needed
|
|
170
|
+
flow = chip.get('option', 'flow')
|
|
171
|
+
_runtask(chip, flow, step, index, _executenode, replay=True)
|
|
172
|
+
|
|
173
|
+
return 0
|
|
174
|
+
|
|
175
|
+
|
|
176
|
+
#########################
|
|
177
|
+
if __name__ == "__main__":
|
|
178
|
+
sys.exit(main())
|