siliconcompiler 0.26.5__py3-none-any.whl

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Files changed (251) hide show
  1. siliconcompiler/__init__.py +24 -0
  2. siliconcompiler/__main__.py +12 -0
  3. siliconcompiler/_common.py +49 -0
  4. siliconcompiler/_metadata.py +36 -0
  5. siliconcompiler/apps/__init__.py +0 -0
  6. siliconcompiler/apps/_common.py +76 -0
  7. siliconcompiler/apps/sc.py +92 -0
  8. siliconcompiler/apps/sc_dashboard.py +94 -0
  9. siliconcompiler/apps/sc_issue.py +178 -0
  10. siliconcompiler/apps/sc_remote.py +199 -0
  11. siliconcompiler/apps/sc_server.py +39 -0
  12. siliconcompiler/apps/sc_show.py +142 -0
  13. siliconcompiler/apps/smake.py +232 -0
  14. siliconcompiler/checklists/__init__.py +0 -0
  15. siliconcompiler/checklists/oh_tapeout.py +41 -0
  16. siliconcompiler/core.py +3221 -0
  17. siliconcompiler/data/RobotoMono/LICENSE.txt +202 -0
  18. siliconcompiler/data/RobotoMono/RobotoMono-Regular.ttf +0 -0
  19. siliconcompiler/data/heartbeat.v +18 -0
  20. siliconcompiler/data/logo.png +0 -0
  21. siliconcompiler/flowgraph.py +570 -0
  22. siliconcompiler/flows/__init__.py +0 -0
  23. siliconcompiler/flows/_common.py +67 -0
  24. siliconcompiler/flows/asicflow.py +180 -0
  25. siliconcompiler/flows/asictopflow.py +38 -0
  26. siliconcompiler/flows/dvflow.py +86 -0
  27. siliconcompiler/flows/fpgaflow.py +202 -0
  28. siliconcompiler/flows/generate_openroad_rcx.py +66 -0
  29. siliconcompiler/flows/lintflow.py +35 -0
  30. siliconcompiler/flows/screenshotflow.py +51 -0
  31. siliconcompiler/flows/showflow.py +59 -0
  32. siliconcompiler/flows/signoffflow.py +53 -0
  33. siliconcompiler/flows/synflow.py +128 -0
  34. siliconcompiler/fpgas/__init__.py +0 -0
  35. siliconcompiler/fpgas/lattice_ice40.py +42 -0
  36. siliconcompiler/fpgas/vpr_example.py +109 -0
  37. siliconcompiler/issue.py +300 -0
  38. siliconcompiler/libs/__init__.py +0 -0
  39. siliconcompiler/libs/asap7sc7p5t.py +8 -0
  40. siliconcompiler/libs/gf180mcu.py +8 -0
  41. siliconcompiler/libs/nangate45.py +8 -0
  42. siliconcompiler/libs/sky130hd.py +8 -0
  43. siliconcompiler/libs/sky130io.py +8 -0
  44. siliconcompiler/package.py +412 -0
  45. siliconcompiler/pdks/__init__.py +0 -0
  46. siliconcompiler/pdks/asap7.py +8 -0
  47. siliconcompiler/pdks/freepdk45.py +8 -0
  48. siliconcompiler/pdks/gf180.py +8 -0
  49. siliconcompiler/pdks/skywater130.py +8 -0
  50. siliconcompiler/remote/__init__.py +36 -0
  51. siliconcompiler/remote/client.py +891 -0
  52. siliconcompiler/remote/schema.py +106 -0
  53. siliconcompiler/remote/server.py +507 -0
  54. siliconcompiler/remote/server_schema/requests/cancel_job.json +51 -0
  55. siliconcompiler/remote/server_schema/requests/check_progress.json +61 -0
  56. siliconcompiler/remote/server_schema/requests/check_server.json +38 -0
  57. siliconcompiler/remote/server_schema/requests/delete_job.json +51 -0
  58. siliconcompiler/remote/server_schema/requests/get_results.json +48 -0
  59. siliconcompiler/remote/server_schema/requests/remote_run.json +40 -0
  60. siliconcompiler/remote/server_schema/responses/cancel_job.json +18 -0
  61. siliconcompiler/remote/server_schema/responses/check_progress.json +30 -0
  62. siliconcompiler/remote/server_schema/responses/check_server.json +32 -0
  63. siliconcompiler/remote/server_schema/responses/delete_job.json +18 -0
  64. siliconcompiler/remote/server_schema/responses/get_results.json +21 -0
  65. siliconcompiler/remote/server_schema/responses/remote_run.json +25 -0
  66. siliconcompiler/report/__init__.py +13 -0
  67. siliconcompiler/report/html_report.py +74 -0
  68. siliconcompiler/report/report.py +355 -0
  69. siliconcompiler/report/streamlit_report.py +137 -0
  70. siliconcompiler/report/streamlit_viewer.py +944 -0
  71. siliconcompiler/report/summary_image.py +117 -0
  72. siliconcompiler/report/summary_table.py +105 -0
  73. siliconcompiler/report/utils.py +163 -0
  74. siliconcompiler/scheduler/__init__.py +2092 -0
  75. siliconcompiler/scheduler/docker_runner.py +253 -0
  76. siliconcompiler/scheduler/run_node.py +138 -0
  77. siliconcompiler/scheduler/send_messages.py +178 -0
  78. siliconcompiler/scheduler/slurm.py +208 -0
  79. siliconcompiler/scheduler/validation/email_credentials.json +54 -0
  80. siliconcompiler/schema/__init__.py +7 -0
  81. siliconcompiler/schema/schema_cfg.py +4014 -0
  82. siliconcompiler/schema/schema_obj.py +1841 -0
  83. siliconcompiler/schema/utils.py +93 -0
  84. siliconcompiler/sphinx_ext/__init__.py +0 -0
  85. siliconcompiler/sphinx_ext/dynamicgen.py +1006 -0
  86. siliconcompiler/sphinx_ext/schemagen.py +221 -0
  87. siliconcompiler/sphinx_ext/utils.py +166 -0
  88. siliconcompiler/targets/__init__.py +0 -0
  89. siliconcompiler/targets/asap7_demo.py +68 -0
  90. siliconcompiler/targets/asic_demo.py +38 -0
  91. siliconcompiler/targets/fpgaflow_demo.py +47 -0
  92. siliconcompiler/targets/freepdk45_demo.py +59 -0
  93. siliconcompiler/targets/gf180_demo.py +77 -0
  94. siliconcompiler/targets/skywater130_demo.py +70 -0
  95. siliconcompiler/templates/email/general.j2 +66 -0
  96. siliconcompiler/templates/email/summary.j2 +43 -0
  97. siliconcompiler/templates/issue/README.txt +26 -0
  98. siliconcompiler/templates/issue/run.sh +6 -0
  99. siliconcompiler/templates/report/bootstrap.min.css +7 -0
  100. siliconcompiler/templates/report/bootstrap.min.js +7 -0
  101. siliconcompiler/templates/report/bootstrap_LICENSE.md +24 -0
  102. siliconcompiler/templates/report/sc_report.j2 +427 -0
  103. siliconcompiler/templates/slurm/run.sh +9 -0
  104. siliconcompiler/templates/tcl/manifest.tcl.j2 +137 -0
  105. siliconcompiler/tools/__init__.py +0 -0
  106. siliconcompiler/tools/_common/__init__.py +432 -0
  107. siliconcompiler/tools/_common/asic.py +115 -0
  108. siliconcompiler/tools/_common/sdc/sc_constraints.sdc +76 -0
  109. siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl +63 -0
  110. siliconcompiler/tools/bambu/bambu.py +32 -0
  111. siliconcompiler/tools/bambu/convert.py +77 -0
  112. siliconcompiler/tools/bluespec/bluespec.py +40 -0
  113. siliconcompiler/tools/bluespec/convert.py +103 -0
  114. siliconcompiler/tools/builtin/_common.py +155 -0
  115. siliconcompiler/tools/builtin/builtin.py +26 -0
  116. siliconcompiler/tools/builtin/concatenate.py +85 -0
  117. siliconcompiler/tools/builtin/join.py +27 -0
  118. siliconcompiler/tools/builtin/maximum.py +46 -0
  119. siliconcompiler/tools/builtin/minimum.py +57 -0
  120. siliconcompiler/tools/builtin/mux.py +70 -0
  121. siliconcompiler/tools/builtin/nop.py +38 -0
  122. siliconcompiler/tools/builtin/verify.py +83 -0
  123. siliconcompiler/tools/chisel/SCDriver.scala +10 -0
  124. siliconcompiler/tools/chisel/build.sbt +27 -0
  125. siliconcompiler/tools/chisel/chisel.py +37 -0
  126. siliconcompiler/tools/chisel/convert.py +140 -0
  127. siliconcompiler/tools/execute/exec_input.py +41 -0
  128. siliconcompiler/tools/execute/execute.py +17 -0
  129. siliconcompiler/tools/genfasm/bitstream.py +61 -0
  130. siliconcompiler/tools/genfasm/genfasm.py +40 -0
  131. siliconcompiler/tools/ghdl/convert.py +87 -0
  132. siliconcompiler/tools/ghdl/ghdl.py +41 -0
  133. siliconcompiler/tools/icarus/compile.py +87 -0
  134. siliconcompiler/tools/icarus/icarus.py +36 -0
  135. siliconcompiler/tools/icepack/bitstream.py +20 -0
  136. siliconcompiler/tools/icepack/icepack.py +43 -0
  137. siliconcompiler/tools/klayout/export.py +117 -0
  138. siliconcompiler/tools/klayout/klayout.py +119 -0
  139. siliconcompiler/tools/klayout/klayout_export.py +205 -0
  140. siliconcompiler/tools/klayout/klayout_operations.py +363 -0
  141. siliconcompiler/tools/klayout/klayout_show.py +242 -0
  142. siliconcompiler/tools/klayout/klayout_utils.py +176 -0
  143. siliconcompiler/tools/klayout/operations.py +194 -0
  144. siliconcompiler/tools/klayout/screenshot.py +98 -0
  145. siliconcompiler/tools/klayout/show.py +101 -0
  146. siliconcompiler/tools/magic/drc.py +49 -0
  147. siliconcompiler/tools/magic/extspice.py +19 -0
  148. siliconcompiler/tools/magic/magic.py +85 -0
  149. siliconcompiler/tools/magic/sc_drc.tcl +96 -0
  150. siliconcompiler/tools/magic/sc_extspice.tcl +54 -0
  151. siliconcompiler/tools/magic/sc_magic.tcl +47 -0
  152. siliconcompiler/tools/montage/montage.py +30 -0
  153. siliconcompiler/tools/montage/tile.py +66 -0
  154. siliconcompiler/tools/netgen/count_lvs.py +132 -0
  155. siliconcompiler/tools/netgen/lvs.py +90 -0
  156. siliconcompiler/tools/netgen/netgen.py +36 -0
  157. siliconcompiler/tools/netgen/sc_lvs.tcl +46 -0
  158. siliconcompiler/tools/nextpnr/apr.py +24 -0
  159. siliconcompiler/tools/nextpnr/nextpnr.py +59 -0
  160. siliconcompiler/tools/openfpgaloader/openfpgaloader.py +39 -0
  161. siliconcompiler/tools/openroad/__init__.py +0 -0
  162. siliconcompiler/tools/openroad/cts.py +45 -0
  163. siliconcompiler/tools/openroad/dfm.py +66 -0
  164. siliconcompiler/tools/openroad/export.py +131 -0
  165. siliconcompiler/tools/openroad/floorplan.py +70 -0
  166. siliconcompiler/tools/openroad/openroad.py +977 -0
  167. siliconcompiler/tools/openroad/physyn.py +27 -0
  168. siliconcompiler/tools/openroad/place.py +41 -0
  169. siliconcompiler/tools/openroad/rcx_bench.py +95 -0
  170. siliconcompiler/tools/openroad/rcx_extract.py +34 -0
  171. siliconcompiler/tools/openroad/route.py +45 -0
  172. siliconcompiler/tools/openroad/screenshot.py +60 -0
  173. siliconcompiler/tools/openroad/scripts/sc_apr.tcl +499 -0
  174. siliconcompiler/tools/openroad/scripts/sc_cts.tcl +64 -0
  175. siliconcompiler/tools/openroad/scripts/sc_dfm.tcl +20 -0
  176. siliconcompiler/tools/openroad/scripts/sc_export.tcl +98 -0
  177. siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl +413 -0
  178. siliconcompiler/tools/openroad/scripts/sc_metrics.tcl +158 -0
  179. siliconcompiler/tools/openroad/scripts/sc_physyn.tcl +7 -0
  180. siliconcompiler/tools/openroad/scripts/sc_place.tcl +84 -0
  181. siliconcompiler/tools/openroad/scripts/sc_procs.tcl +423 -0
  182. siliconcompiler/tools/openroad/scripts/sc_rcx.tcl +63 -0
  183. siliconcompiler/tools/openroad/scripts/sc_rcx_bench.tcl +20 -0
  184. siliconcompiler/tools/openroad/scripts/sc_rcx_extract.tcl +12 -0
  185. siliconcompiler/tools/openroad/scripts/sc_route.tcl +133 -0
  186. siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl +21 -0
  187. siliconcompiler/tools/openroad/scripts/sc_write.tcl +5 -0
  188. siliconcompiler/tools/openroad/scripts/sc_write_images.tcl +361 -0
  189. siliconcompiler/tools/openroad/show.py +94 -0
  190. siliconcompiler/tools/openroad/templates/pex.tcl +8 -0
  191. siliconcompiler/tools/opensta/__init__.py +101 -0
  192. siliconcompiler/tools/opensta/report_libraries.py +28 -0
  193. siliconcompiler/tools/opensta/scripts/sc_procs.tcl +47 -0
  194. siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl +74 -0
  195. siliconcompiler/tools/opensta/scripts/sc_timing.tcl +268 -0
  196. siliconcompiler/tools/opensta/timing.py +214 -0
  197. siliconcompiler/tools/slang/__init__.py +49 -0
  198. siliconcompiler/tools/slang/lint.py +101 -0
  199. siliconcompiler/tools/surelog/__init__.py +123 -0
  200. siliconcompiler/tools/surelog/parse.py +183 -0
  201. siliconcompiler/tools/surelog/templates/output.v +7 -0
  202. siliconcompiler/tools/sv2v/convert.py +46 -0
  203. siliconcompiler/tools/sv2v/sv2v.py +37 -0
  204. siliconcompiler/tools/template/template.py +125 -0
  205. siliconcompiler/tools/verilator/compile.py +139 -0
  206. siliconcompiler/tools/verilator/lint.py +19 -0
  207. siliconcompiler/tools/verilator/parse.py +27 -0
  208. siliconcompiler/tools/verilator/verilator.py +172 -0
  209. siliconcompiler/tools/vivado/__init__.py +7 -0
  210. siliconcompiler/tools/vivado/bitstream.py +21 -0
  211. siliconcompiler/tools/vivado/place.py +21 -0
  212. siliconcompiler/tools/vivado/route.py +21 -0
  213. siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl +6 -0
  214. siliconcompiler/tools/vivado/scripts/sc_place.tcl +2 -0
  215. siliconcompiler/tools/vivado/scripts/sc_route.tcl +4 -0
  216. siliconcompiler/tools/vivado/scripts/sc_run.tcl +45 -0
  217. siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl +25 -0
  218. siliconcompiler/tools/vivado/syn_fpga.py +20 -0
  219. siliconcompiler/tools/vivado/vivado.py +147 -0
  220. siliconcompiler/tools/vpr/_json_constraint.py +63 -0
  221. siliconcompiler/tools/vpr/_xml_constraint.py +109 -0
  222. siliconcompiler/tools/vpr/place.py +137 -0
  223. siliconcompiler/tools/vpr/route.py +124 -0
  224. siliconcompiler/tools/vpr/screenshot.py +54 -0
  225. siliconcompiler/tools/vpr/show.py +88 -0
  226. siliconcompiler/tools/vpr/vpr.py +357 -0
  227. siliconcompiler/tools/xyce/xyce.py +36 -0
  228. siliconcompiler/tools/yosys/lec.py +56 -0
  229. siliconcompiler/tools/yosys/prepareLib.py +59 -0
  230. siliconcompiler/tools/yosys/sc_lec.tcl +84 -0
  231. siliconcompiler/tools/yosys/sc_syn.tcl +79 -0
  232. siliconcompiler/tools/yosys/syn_asic.py +565 -0
  233. siliconcompiler/tools/yosys/syn_asic.tcl +377 -0
  234. siliconcompiler/tools/yosys/syn_asic_fpga_shared.tcl +31 -0
  235. siliconcompiler/tools/yosys/syn_fpga.py +146 -0
  236. siliconcompiler/tools/yosys/syn_fpga.tcl +233 -0
  237. siliconcompiler/tools/yosys/syn_strategies.tcl +81 -0
  238. siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v +39 -0
  239. siliconcompiler/tools/yosys/templates/abc.const +2 -0
  240. siliconcompiler/tools/yosys/yosys.py +147 -0
  241. siliconcompiler/units.py +259 -0
  242. siliconcompiler/use.py +177 -0
  243. siliconcompiler/utils/__init__.py +423 -0
  244. siliconcompiler/utils/asic.py +158 -0
  245. siliconcompiler/utils/showtools.py +25 -0
  246. siliconcompiler-0.26.5.dist-info/LICENSE +190 -0
  247. siliconcompiler-0.26.5.dist-info/METADATA +195 -0
  248. siliconcompiler-0.26.5.dist-info/RECORD +251 -0
  249. siliconcompiler-0.26.5.dist-info/WHEEL +5 -0
  250. siliconcompiler-0.26.5.dist-info/entry_points.txt +12 -0
  251. siliconcompiler-0.26.5.dist-info/top_level.txt +1 -0
@@ -0,0 +1,24 @@
1
+ from siliconcompiler._common import NodeStatus, SiliconCompilerError
2
+
3
+ from siliconcompiler.utils import sc_open
4
+
5
+ from siliconcompiler.core import Chip
6
+ from siliconcompiler.schema import Schema
7
+
8
+ from siliconcompiler._metadata import version as __version__
9
+
10
+ from siliconcompiler.use import PDK, FPGA, Library, Flow, Checklist
11
+
12
+ __all__ = [
13
+ "__version__",
14
+ "Chip",
15
+ "SiliconCompilerError",
16
+ "NodeStatus",
17
+ "PDK",
18
+ "FPGA",
19
+ "Library",
20
+ "Flow",
21
+ "Checklist",
22
+ "Schema",
23
+ "sc_open"
24
+ ]
@@ -0,0 +1,12 @@
1
+ # Copyright 2020 Silicon Compiler Authors. All Rights Reserved.
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+
3
+
4
+ from siliconcompiler.apps import sc
5
+
6
+
7
+ def main():
8
+ sc.main()
9
+
10
+
11
+ if __name__ == '__main__':
12
+ main()
@@ -0,0 +1,49 @@
1
+ class NodeStatus():
2
+ # node waiting to run
3
+ PENDING = 'pending'
4
+
5
+ # node ready to run and waiting
6
+ QUEUED = 'queued'
7
+
8
+ # node running
9
+ RUNNING = 'running'
10
+
11
+ # node exit status
12
+ SUCCESS = 'success'
13
+ ERROR = 'error'
14
+ SKIPPED = 'skipped'
15
+ TIMEOUT = 'timeout'
16
+
17
+ def is_done(status):
18
+ return status in (
19
+ NodeStatus.SUCCESS,
20
+ NodeStatus.ERROR,
21
+ NodeStatus.SKIPPED,
22
+ NodeStatus.TIMEOUT
23
+ )
24
+
25
+ def is_running(status):
26
+ return status in (
27
+ NodeStatus.QUEUED,
28
+ NodeStatus.RUNNING
29
+ )
30
+
31
+ def is_waiting(status):
32
+ return status in (
33
+ NodeStatus.PENDING,
34
+ )
35
+
36
+
37
+ ###############################################################################
38
+ # Package Customization classes
39
+ ###############################################################################
40
+ class SiliconCompilerError(Exception):
41
+ ''' Minimal Exception wrapper used to raise sc runtime errors.
42
+ '''
43
+ def __init__(self, message, chip=None):
44
+ super(Exception, self).__init__(message)
45
+
46
+ if chip:
47
+ logger = getattr(chip, 'logger', None)
48
+ if logger:
49
+ logger.error(message)
@@ -0,0 +1,36 @@
1
+ # Version number following semver standard.
2
+ version = '0.26.5'
3
+
4
+ # Default server address for remote runs, if unspecified.
5
+ default_server = 'https://server.siliconcompiler.com'
6
+
7
+ # This is the list of significant contributors to SiliconCompiler in
8
+ # chronological order.
9
+ #
10
+ # This does not necessarily list everyone who has contributed code,
11
+ # especially since many employees of one corporation may be contributing.
12
+ # To see the full list of contributors, see the git revision history
13
+ authors = [
14
+ 'Andreas Olofsson',
15
+ 'William Ransohoff',
16
+ 'Noah Moroze',
17
+ 'Zachary Yedidia',
18
+ 'Massimiliano Giacometti',
19
+ 'Kimia Talaei',
20
+ 'Peter Gadfort',
21
+ 'Aulihan Teng',
22
+ 'Peter Grossmann',
23
+ 'Gabriel Aguirre',
24
+ 'Martin Troiber'
25
+ ]
26
+
27
+ # CLI entry banner autogenerated using pyfiglet.
28
+ # >> pyfiglet.figlet_format("Silicon Compiler")
29
+ banner = r'''
30
+ ____ _ _ _ ____ _ _
31
+ / ___|(_) (_) ___ ___ _ __ / ___|___ _ __ ___ _ __ (_) | ___ _ __
32
+ \___ \| | | |/ __/ _ \| '_ \ | | / _ \| '_ ` _ \| '_ \| | |/ _ \ '__|
33
+ ___) | | | | (_| (_) | | | | | |__| (_) | | | | | | |_) | | | __/ |
34
+ |____/|_|_|_|\___\___/|_| |_| \____\___/|_| |_| |_| .__/|_|_|\___|_|
35
+ |_|
36
+ '''
File without changes
@@ -0,0 +1,76 @@
1
+ import glob
2
+ import os
3
+
4
+
5
+ def manifest_switches():
6
+ '''
7
+ Returns a list of manifest switches that can be used
8
+ to find the manifest based on their values
9
+ '''
10
+ return ['-design',
11
+ '-cfg',
12
+ '-arg_step',
13
+ '-arg_index',
14
+ '-jobname']
15
+
16
+
17
+ def load_manifest(chip, src_file):
18
+ manifest = None
19
+ if (src_file is not None) and (not chip.get('option', 'cfg')):
20
+ if not os.path.exists(src_file):
21
+ chip.logger.error(f'{src_file} cannot be found.')
22
+ return False
23
+ # only autoload manifest if user doesn't supply manually
24
+ manifest = _get_manifest(os.path.dirname(src_file))
25
+ if not manifest:
26
+ design = os.path.splitext(os.path.basename(src_file))[0]
27
+ chip.logger.error(f'Unable to automatically find manifest for design {design}. '
28
+ 'Please provide a manifest explicitly using -cfg.')
29
+ return False
30
+ elif not chip.get('option', 'cfg'):
31
+ manifest = _get_manifest_from_design(chip)
32
+ if not manifest:
33
+ chip.logger.error(f'Could not find manifest for {chip.design}')
34
+ return False
35
+
36
+ if manifest:
37
+ chip.logger.info(f'Loading manifest: {manifest}')
38
+ chip.read_manifest(manifest)
39
+ return True
40
+
41
+
42
+ def _get_manifest(dirname, design='*'):
43
+ # pkg.json file may have a different name from the design due to the entrypoint
44
+ glob_paths = [os.path.join(dirname, f'{design}.pkg.json'),
45
+ os.path.join(dirname, 'outputs', f'{design}.pkg.json')]
46
+ manifest = None
47
+ for path in glob_paths:
48
+ manifest = glob.glob(path)
49
+ if manifest:
50
+ manifest = manifest[0]
51
+ break
52
+
53
+ if not manifest or not os.path.isfile(manifest):
54
+ return None
55
+ return manifest
56
+
57
+
58
+ def _get_manifest_from_design(chip):
59
+ for jobname, step, index in [
60
+ (chip.get('option', 'jobname'),
61
+ chip.get('arg', 'step'),
62
+ chip.get('arg', 'index')),
63
+ (chip.get('option', 'jobname'),
64
+ None,
65
+ None),
66
+ (chip.schema.get_default('option', 'jobname'),
67
+ chip.get('arg', 'step'),
68
+ chip.get('arg', 'index')),
69
+ (chip.schema.get_default('option', 'jobname'),
70
+ None,
71
+ None)]:
72
+ manifest = _get_manifest(chip.getworkdir(jobname=jobname, step=step, index=index))
73
+
74
+ if manifest:
75
+ return manifest
76
+ return None
@@ -0,0 +1,92 @@
1
+ # Copyright 2020 Silicon Compiler Authors. All Rights Reserved.
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+
3
+ # Standard Modules
4
+ import os
5
+ import sys
6
+
7
+ import siliconcompiler
8
+ from siliconcompiler.utils import get_default_iomap
9
+ from siliconcompiler.targets import skywater130_demo
10
+ from siliconcompiler import SiliconCompilerError
11
+
12
+
13
+ ###########################
14
+ def main():
15
+ progname = "sc"
16
+ description = """
17
+ ------------------------------------------------------------
18
+ SiliconCompiler is an open source compiler framework that
19
+ aims to enable automated translation from source code to
20
+ silicon.
21
+
22
+ The sc program includes the following steps.
23
+
24
+ 1. Read command line arguments
25
+ 2. If not set, 'design' is set to base of first source file.
26
+ 3. If not set, 'target' is set to 'skywater130_demo'.
27
+ 4. Run compilation
28
+ 5. Display summary
29
+
30
+ Sources: https://github.com/siliconcompiler/siliconcompiler
31
+ ------------------------------------------------------------
32
+ """
33
+ # TODO: this is a hack to get around design name requirement: since legal
34
+ # design names probably can't contain spaces, we can detect if it is unset.
35
+ UNSET_DESIGN = ' unset '
36
+
37
+ # Create a base chip class.
38
+ chip = siliconcompiler.Chip(UNSET_DESIGN)
39
+
40
+ # Read command-line inputs and generate Chip objects to run the flow on.
41
+ try:
42
+ chip.create_cmdline(progname,
43
+ description=description,
44
+ input_map=get_default_iomap())
45
+ except Exception as e:
46
+ chip.logger.error(e)
47
+ return 1
48
+
49
+ # Set design if none specified
50
+ if chip.get('design') == UNSET_DESIGN:
51
+ topfile = None
52
+ for sourceset in ('rtl', 'hll'):
53
+ for filetype in chip.getkeys('input', sourceset):
54
+ all_vals = chip.schema._getvals('input', sourceset, filetype)
55
+ if all_vals:
56
+ # just look at first value
57
+ sources, _, _ = all_vals[0]
58
+ # grab first source
59
+ topfile = sources[0]
60
+ break
61
+ if topfile:
62
+ break
63
+
64
+ if not topfile:
65
+ chip.logger.error('Invalid arguments: either specify -design or provide sources.')
66
+ return 1
67
+
68
+ topmodule = os.path.splitext(os.path.basename(topfile))[0]
69
+ chip.set('design', topmodule)
70
+
71
+ # Set demo target if none specified
72
+ if not chip.get('option', 'target'):
73
+ chip.load_target(skywater130_demo)
74
+
75
+ try:
76
+ # Run flow
77
+ chip.run()
78
+
79
+ # Print Job Summary
80
+ chip.summary()
81
+ except SiliconCompilerError:
82
+ return 1
83
+ except Exception as e:
84
+ chip.logger.error(e)
85
+ return 1
86
+
87
+ return 0
88
+
89
+
90
+ #########################
91
+ if __name__ == "__main__":
92
+ sys.exit(main())
@@ -0,0 +1,94 @@
1
+ # Copyright 2023 Silicon Compiler Authors. All Rights Reserved.
2
+ import sys
3
+ import siliconcompiler
4
+ import os
5
+ from siliconcompiler.apps._common import load_manifest, manifest_switches
6
+
7
+
8
+ def main():
9
+ progname = "sc-dashboard"
10
+ description = """
11
+ -----------------------------------------------------------
12
+ SC app to open a dashboard for a given manifest.
13
+
14
+ To open:
15
+ sc-dashboard -cfg <path to manifest>
16
+
17
+ To specify a different port than the default:
18
+ sc-dashboard -cfg <path to manifest> -port 10000
19
+
20
+ To include another chip object to compare to:
21
+ sc-dashboard -cfg <path to manifest> -graph_cfg <name of manifest> <path to other manifest>
22
+ -graph_cfg <path to other manifest> ...
23
+ -----------------------------------------------------------
24
+ """
25
+
26
+ # TODO: this is a hack to get around design name requirement: since legal
27
+ # design names probably can't contain spaces, we can detect if it is unset.
28
+ UNSET_DESIGN = ' unset '
29
+
30
+ # Create a base chip class.
31
+ chip = siliconcompiler.Chip(UNSET_DESIGN)
32
+
33
+ dashboard_arguments = {
34
+ "-port": {'type': int,
35
+ 'help': 'port to open the dashboard app on',
36
+ 'metavar': '<port>',
37
+ 'sc_print': False},
38
+ "-graph_cfg": {'type': str,
39
+ 'nargs': '+',
40
+ 'action': 'append',
41
+ 'help': 'chip name - optional, path to chip manifest (json)',
42
+ 'metavar': '<[manifest name, manifest path>',
43
+ 'sc_print': False}
44
+ }
45
+
46
+ try:
47
+ switches = chip.create_cmdline(
48
+ progname,
49
+ switchlist=[*manifest_switches(),
50
+ '-loglevel'],
51
+ description=description,
52
+ additional_args=dashboard_arguments)
53
+ except Exception as e:
54
+ chip.logger.error(e)
55
+ return 1
56
+
57
+ # Error checking
58
+ design = chip.get('design')
59
+ if design == UNSET_DESIGN:
60
+ chip.logger.error('Design not loaded')
61
+ return 1
62
+
63
+ if not load_manifest(chip, None):
64
+ return 1
65
+
66
+ graph_chips = []
67
+ if switches['graph_cfg']:
68
+ for i, name_and_file_path in enumerate(switches['graph_cfg']):
69
+ args = len(name_and_file_path)
70
+ if args == 0:
71
+ continue
72
+ elif args == 1:
73
+ name = f'cfg{i}'
74
+ file_path = name_and_file_path[0]
75
+ elif args == 2:
76
+ name = name_and_file_path[0]
77
+ file_path = name_and_file_path[1]
78
+ else:
79
+ raise ValueError(('graph_cfg accepts a max of 2 values, you supplied'
80
+ f' {args} in "-graph_cfg {name_and_file_path}"'))
81
+ if not os.path.isfile(file_path):
82
+ raise ValueError(f'not a valid file path : {file_path}')
83
+ graph_chip = siliconcompiler.core.Chip(design='')
84
+ graph_chip.read_manifest(file_path)
85
+ graph_chips.append({'chip': graph_chip, 'name': name})
86
+
87
+ chip._dashboard(wait=True, port=switches['port'], graph_chips=graph_chips)
88
+
89
+ return 0
90
+
91
+
92
+ #########################
93
+ if __name__ == "__main__":
94
+ sys.exit(main())
@@ -0,0 +1,178 @@
1
+ # Copyright 2023 Silicon Compiler Authors. All Rights Reserved.
2
+ import sys
3
+ import os
4
+ import siliconcompiler
5
+ import tarfile
6
+ import json
7
+ import importlib
8
+ from siliconcompiler.scheduler import _runtask, _executenode
9
+ from siliconcompiler.issue import generate_testcase
10
+ from siliconcompiler.tools._common import get_tool_task
11
+
12
+
13
+ def main():
14
+ progname = "sc-issue"
15
+ chip = siliconcompiler.Chip(progname)
16
+ switchlist = ['-cfg',
17
+ '-arg_step',
18
+ '-arg_index',
19
+ '-tool_task_var',
20
+ '-tool_task_option',
21
+ '-loglevel']
22
+ description = """
23
+ -----------------------------------------------------------
24
+ Restricted SC app that generates a sharable testcase from a
25
+ failed flow or runs an issue generated with this program.
26
+
27
+ To generate a testcase, use:
28
+ sc-issue -cfg <stepdir>/outputs/<design>.pkg.json
29
+
30
+ or include a different step/index than what the cfg_file is pointing to:
31
+ sc-issue -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
32
+
33
+ or include specific libraries while excluding others:
34
+ sc-issue -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
35
+
36
+ To run a testcase, use:
37
+ sc-issue -run -file sc_issue_<...>.tar.gz
38
+ -----------------------------------------------------------
39
+ """ # noqa E501
40
+
41
+ issue_arguments = {
42
+ '-exclude_libraries': {'action': 'store_true',
43
+ 'help': 'flag to ensure libraries are excluded in the testcase',
44
+ 'sc_print': False},
45
+ '-exclude_pdks': {'action': 'store_true',
46
+ 'help': 'flag to ensure pdks are excluded in the testcase',
47
+ 'sc_print': False},
48
+ '-hash_files': {'action': 'store_true',
49
+ 'help': 'flag to hash the files in the schema before generating '
50
+ 'the manifest',
51
+ 'sc_print': False},
52
+
53
+ '-run': {'action': 'store_true',
54
+ 'help': 'run a provided testcase',
55
+ 'sc_print': False},
56
+
57
+ '-use': {'action': 'append',
58
+ 'help': 'modules to load into test run',
59
+ 'metavar': '<module>',
60
+ 'sc_print': False},
61
+
62
+ '-add_library': {'action': 'append',
63
+ 'help': 'library to include in the testcase, if not provided all '
64
+ 'libraries will be added according to the -exclude_libraries flag',
65
+ 'metavar': '<library>',
66
+ 'sc_print': False},
67
+ '-add_pdk': {'action': 'append',
68
+ 'help': 'pdk to include in the testcase, if not provided all libraries '
69
+ 'will be added according to the -exclude_pdks flag',
70
+ 'metavar': '<pdk>',
71
+ 'sc_print': False},
72
+
73
+ '-file': {'help': 'filename for the generated testcase',
74
+ 'metavar': '<file>',
75
+ 'sc_print': False},
76
+ }
77
+
78
+ try:
79
+ switches = chip.create_cmdline(progname,
80
+ switchlist=switchlist,
81
+ description=description,
82
+ additional_args=issue_arguments)
83
+ except Exception as e:
84
+ chip.logger.error(e)
85
+ return 1
86
+
87
+ if not switches['run']:
88
+ step = chip.get('arg', 'step')
89
+ index = chip.get('arg', 'index')
90
+
91
+ if not step:
92
+ chip.logger.error('Unable to determine step from manifest')
93
+ if not index:
94
+ chip.logger.error('Unable to determine index from manifest')
95
+ if not step or not index:
96
+ # Exit out
97
+ return 1
98
+
99
+ generate_testcase(chip,
100
+ step,
101
+ index,
102
+ switches['file'],
103
+ include_pdks=not switches['exclude_pdks'],
104
+ include_specific_pdks=switches['add_pdk'],
105
+ include_libraries=not switches['exclude_libraries'],
106
+ include_specific_libraries=switches['add_library'],
107
+ hash_files=switches['hash_files'])
108
+
109
+ return 0
110
+
111
+ if switches['run']:
112
+ if not switches['file']:
113
+ raise ValueError('-file must be provided')
114
+
115
+ test_dir = os.path.basename(switches['file']).split('.')[0]
116
+ with tarfile.open(switches['file'], 'r:gz') as f:
117
+ f.extractall(path='.')
118
+
119
+ chip.read_manifest(f'{test_dir}/orig_manifest.json')
120
+
121
+ with open(f'{test_dir}/issue.json', 'r') as f:
122
+ issue_info = json.load(f)
123
+
124
+ # Report major information
125
+ sc_version = issue_info['version']['sc']
126
+ if 'commit' in issue_info['version']['git']:
127
+ sc_source = issue_info['version']['git']['commit']
128
+ else:
129
+ sc_source = 'installed'
130
+
131
+ chip.logger.info(f"Design: {chip.design}")
132
+ chip.logger.info(f"SiliconCompiler version: {sc_version} / {sc_source}")
133
+ chip.logger.info(f"Schema version: {issue_info['version']['schema']}")
134
+ chip.logger.info(f"Python version: {issue_info['python']['version']}")
135
+
136
+ sc_machine = issue_info['machine']
137
+ sc_os = sc_machine['system']
138
+ if 'distro' in sc_machine:
139
+ sc_os += f" {sc_machine['distro']}"
140
+ sc_os += f" {sc_machine['osversion']} {sc_machine['arch']} {sc_machine['kernelversion']}"
141
+ chip.logger.info(f"Machine: {sc_os}")
142
+ chip.logger.info(f"Date: {issue_info['date']}")
143
+
144
+ step = issue_info['run']['step']
145
+ index = issue_info['run']['index']
146
+
147
+ chip.set('arg', 'step', step)
148
+ chip.set('arg', 'index', index)
149
+ tool, task = get_tool_task(chip, step, index)
150
+ chip.logger.info(f'Preparing run for {step}{index} - {tool}/{task}')
151
+
152
+ # Modify run environment to point to extracted files
153
+ builddir_key = ['option', 'builddir']
154
+ new_builddir = f"{test_dir}/{chip.get(*builddir_key)}"
155
+ chip.logger.info(f"Changing {builddir_key} to '{new_builddir}'")
156
+ chip.set(*builddir_key, new_builddir)
157
+
158
+ if switches['use']:
159
+ for use in switches['use']:
160
+ try:
161
+ module = importlib.import_module(use)
162
+ chip.logger.info(f"Loading '{use}' module")
163
+ chip.use(module)
164
+ except ModuleNotFoundError:
165
+ chip.logger.error(f"Unable to use '{use}' module")
166
+
167
+ # Run task
168
+ # Rerun setup task, assumed to be running in its own thread so
169
+ # multiprocess is not needed
170
+ flow = chip.get('option', 'flow')
171
+ _runtask(chip, flow, step, index, _executenode, replay=True)
172
+
173
+ return 0
174
+
175
+
176
+ #########################
177
+ if __name__ == "__main__":
178
+ sys.exit(main())