siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/builtin/maximum.py

@@ -0,0 +1,46 @@
+from siliconcompiler.tools.builtin import _common
+from siliconcompiler.tools.builtin import minimum
+from siliconcompiler.tools.builtin.builtin import set_io_files
+
+
+def setup(chip):
+    '''
+    Selects the task with the maximum metric score from a list of inputs.
+
+    Sequence of operation:
+
+    1. Check list of input tasks to see if all metrics meets goals
+    2. Check list of input tasks to find global min/max for each metric
+    3. Select MAX value if all metrics are met.
+    4. Normalize the min value as sel = (val - MIN) / (MAX - MIN)
+    5. Return normalized value and task name
+
+    Meeting metric goals takes precedence over compute metric scores.
+    Only goals with values set and metrics with weights set are considered
+    in the calculation.
+    '''
+
+    set_io_files(chip)
+
+
+def _select_inputs(chip, step, index):
+    inputs = _common._select_inputs(chip, step, index)
+
+    score, sel_inputs = _common._minmax(chip, *inputs, op='maximum')
+
+    if sel_inputs:
+        chip.logger.info(f"Selected '{sel_inputs[0]}{sel_inputs[1]}' with score {score:.3f}")
+
+    return sel_inputs
+
+
+def _gather_outputs(chip, step, index):
+    return minimum._gather_outputs(chip, step, index)
+
+
+def run(chip):
+    return _common.run(chip)
+
+
+def post_process(chip):
+    _common.post_process(chip)

siliconcompiler/tools/builtin/minimum.py

@@ -0,0 +1,57 @@
+from siliconcompiler.tools.builtin import _common
+from siliconcompiler import flowgraph
+from siliconcompiler.tools.builtin.builtin import set_io_files
+
+
+def setup(chip):
+    '''
+    Selects the task with the minimum metric score from a list of inputs.
+
+    Sequence of operation:
+
+    1. Check list of input tasks to see if all metrics meets goals
+    2. Check list of input tasks to find global min/max for each metric
+    3. Select MIN value if all metrics are met.
+    4. Normalize the min value as sel = (val - MIN) / (MAX - MIN)
+    5. Return normalized value and task name
+
+    Meeting metric goals takes precedence over compute metric scores.
+    Only goals with values set and metrics with weights set are considered
+    in the calculation.
+    '''
+
+    set_io_files(chip)
+
+
+def _select_inputs(chip, step, index):
+    inputs = _common._select_inputs(chip, step, index)
+
+    score, sel_inputs = _common._minmax(chip, *inputs, op='minimum')
+
+    if sel_inputs:
+        chip.logger.info(f"Selected '{sel_inputs[0]}{sel_inputs[1]}' with score {score:.3f}")
+
+    return sel_inputs
+
+
+def _gather_outputs(chip, step, index):
+    '''Return set of filenames that are guaranteed to be in outputs
+    directory after a successful run of step/index.'''
+
+    flow = chip.get('option', 'flow')
+
+    in_nodes = chip.get('flowgraph', flow, step, index, 'input')
+    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+
+    if len(in_task_outputs) > 0:
+        return in_task_outputs[0].intersection(*in_task_outputs[1:])
+
+    return []
+
+
+def run(chip):
+    return _common.run(chip)
+
+
+def post_process(chip):
+    _common.post_process(chip)

siliconcompiler/tools/builtin/mux.py

@@ -0,0 +1,70 @@
+from siliconcompiler.tools.builtin import _common
+import re
+from siliconcompiler.tools.builtin.builtin import set_io_files
+from siliconcompiler import flowgraph, SiliconCompilerError
+
+
+def setup(chip):
+    '''
+    Selects a task from a list of inputs.
+
+    The selector criteria provided is used to create a custom function
+    for selecting the best step/index pair from the inputs. Metrics and
+    weights are passed in and used to select the step/index based on
+    the minimum or maximum score depending on the 'op' argument from
+    ['flowgraph', flow, step, index, 'args'] in the form 'minimum(metric)' or
+    'maximum(metric)'.
+
+    The function can be used to bypass the flows weight functions for
+    the purpose of conditional flow execution and verification.
+    '''
+
+    set_io_files(chip)
+
+
+def _select_inputs(chip, step, index):
+    chip.logger.info("Running builtin task 'mux'")
+
+    flow = chip.get('option', 'flow')
+    inputs = chip.get('flowgraph', flow, step, index, 'input')
+    arguments = chip.get('flowgraph', flow, step, index, 'args')
+
+    operations = []
+    for criteria in arguments:
+        m = re.match(r'(minimum|maximum)\((\w+)\)', criteria)
+        if not m:
+            raise SiliconCompilerError(f"Illegal mux criteria: {criteria}", chip=chip)
+
+        op = m.group(1)
+        metric = m.group(2)
+        if metric not in chip.getkeys('metric'):
+            raise SiliconCompilerError(
+                f"Criteria must use legal metrics only: {criteria}", chip=chip)
+
+        operations.append((metric, op))
+    score, sel_inputs = _common._mux(chip, *inputs, operations=operations)
+
+    if sel_inputs:
+        chip.logger.info(f"Selected '{sel_inputs[0]}{sel_inputs[1]}' with score {score:.3f}")
+
+    return sel_inputs
+
+
+def _gather_outputs(chip, step, index):
+    flow = chip.get('option', 'flow')
+
+    in_nodes = chip.get('flowgraph', flow, step, index, 'input')
+    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+
+    if len(in_task_outputs) > 0:
+        return in_task_outputs[0].intersection(*in_task_outputs[1:])
+
+    return []
+
+
+def run(chip):
+    return _common.run(chip)
+
+
+def post_process(chip):
+    _common.post_process(chip)

siliconcompiler/tools/builtin/nop.py

@@ -0,0 +1,38 @@
+from siliconcompiler.tools.builtin import _common
+from siliconcompiler.tools.builtin.builtin import set_io_files
+from siliconcompiler import flowgraph
+
+
+def setup(chip):
+    '''
+    A no-operation that passes inputs to outputs.
+    '''
+
+    set_io_files(chip)
+
+
+def _select_inputs(chip, step, index):
+    return _common._select_inputs(chip, step, index)
+
+
+def _gather_outputs(chip, step, index):
+    '''Return set of filenames that are guaranteed to be in outputs
+    directory after a successful run of step/index.'''
+
+    flow = chip.get('option', 'flow')
+
+    in_nodes = chip.get('flowgraph', flow, step, index, 'input')
+    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+
+    if len(in_task_outputs) > 0:
+        return in_task_outputs[0].union(*in_task_outputs[1:])
+
+    return []
+
+
+def run(chip):
+    return _common.run(chip)
+
+
+def post_process(chip):
+    _common.post_process(chip)

siliconcompiler/tools/builtin/verify.py

@@ -0,0 +1,83 @@
+from siliconcompiler.tools.builtin import _common
+from siliconcompiler.schema import Schema
+from siliconcompiler.scheduler import _haltstep
+from siliconcompiler.tools.builtin.builtin import set_io_files
+from siliconcompiler import utils, flowgraph, SiliconCompilerError
+
+import re
+
+
+def setup(chip):
+    '''
+    Tests an assertion on an input task.
+
+    The input to this task is verified to ensure that all assertions
+    are True. If any of the assertions fail, False is returned.
+    Assertions are passed in using ['flowgraph', flow, step, index, 'args'] in the form
+    'metric==0.0'.
+    The allowed conditional operators are: >, <, >=, <=, ==
+    '''
+
+    set_io_files(chip, outputs=False)
+
+
+def _select_inputs(chip, step, index):
+    inputs = _common._select_inputs(chip, step, index)
+    if len(inputs) != 1:
+        raise SiliconCompilerError(
+            f'{step}{index} receives {len(inputs)} inputs, but only supports one', chip=chip)
+    inputs = inputs[0]
+    flow = chip.get('option', 'flow')
+    arguments = chip.get('flowgraph', flow, step, index, 'args')
+
+    if len(arguments) == 0:
+        raise SiliconCompilerError(f'{step}{index} requires arguments for verify', chip=chip)
+
+    passes = True
+    for criteria in arguments:
+        m = re.match(r'(\w+)([\>\=\<]+)(\w+)', criteria)
+        if not m:
+            raise SiliconCompilerError(f"Illegal verify criteria: {criteria}", chip=chip)
+
+        metric = m.group(1)
+        op = m.group(2)
+        goal = m.group(3)
+        if metric not in chip.getkeys('metric'):
+            raise SiliconCompilerError(
+                f"Criteria must use legal metrics only: {criteria}", chip=chip)
+
+        value = chip.get('metric', metric, step=inputs[0], index=inputs[1])
+
+        if value is None:
+            raise SiliconCompilerError(
+                f"Missing metric for {metric} in {inputs[0]}{inputs[1]}", chip=chip)
+
+        metric_type = chip.get('metric', metric, field='type')
+        goal = Schema._normalize_value(goal, metric_type, "", None)
+        if not utils.safecompare(chip, value, op, goal):
+            chip.error(f"{step}{index} fails '{metric}' metric: {value}{op}{goal}")
+
+    if not passes:
+        _haltstep(chip, flow, step, index)
+
+    return inputs
+
+
+def _gather_outputs(chip, step, index):
+    flow = chip.get('option', 'flow')
+
+    in_nodes = chip.get('flowgraph', flow, step, index, 'input')
+    in_task_outputs = [flowgraph._gather_outputs(chip, *node) for node in in_nodes]
+
+    if len(in_task_outputs) > 0:
+        return in_task_outputs[0].intersection(*in_task_outputs[1:])
+
+    return []
+
+
+def run(chip):
+    return _common.run(chip)
+
+
+def post_process(chip):
+    _common.post_process(chip)

siliconcompiler/tools/chisel/SCDriver.scala

@@ -0,0 +1,10 @@
+import chisel3.stage.ChiselStage
+
+import chisel3._
+
+object SCDriver extends App {
+  (new ChiselStage).execute(
+    Array("-E", "verilog", "--target-dir", "chisel_work") ++ args,
+    Seq()
+  )
+}

siliconcompiler/tools/chisel/build.sbt

@@ -0,0 +1,27 @@
+// Based on https://github.com/freechipsproject/chisel-template/blob/main/build.sbt
+
+ThisBuild / scalaVersion     := "2.12.13"
+
+Compile / scalaSource := baseDirectory.value / "inputs"
+
+lazy val root = (project in file("."))
+  .settings(
+    libraryDependencies ++= Seq(
+      "edu.berkeley.cs" %% "chisel3" % "3.4.3",
+      "edu.berkeley.cs" %% "chiseltest" % "0.3.3" % "test"
+    ),
+    scalacOptions ++= Seq(
+      "-Xsource:2.11",
+      "-language:reflectiveCalls",
+      "-deprecation",
+      "-feature",
+      "-Xcheckinit",
+      // Enables autoclonetype2 in 3.4.x (on by default in 3.5)
+      "-P:chiselplugin:useBundlePlugin"
+    ),
+    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.4.3" cross CrossVersion.full),
+    addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
+  )
+
+// Prevents exception on exit
+trapExit := false

siliconcompiler/tools/chisel/chisel.py

@@ -0,0 +1,37 @@
+'''
+Chisel is a hardware design language that facilitates advanced circuit
+generation and design reuse for both ASIC and FPGA digital logic designs.
+Chisel adds hardware construction primitives to the Scala programming
+language, providing designers with the power of a modern programming
+language to write complex, parameterizable circuit generators that produce
+synthesizable Verilog.
+
+Documentation: https://www.chisel-lang.org/docs
+
+Sources: https://github.com/chipsalliance/chisel
+
+Installation: The Chisel plugin relies on having the Scala Build Tool (sbt)
+installed. Instructions: https://www.scala-sbt.org/download.html.
+'''
+
+from siliconcompiler.tools.chisel import convert
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    convert.setup(chip)
+    return chip
+
+
+def parse_version(stdout):
+    # sbt version in this project: 1.5.5
+    # sbt script version: 1.5.5
+
+    for line in stdout.splitlines():
+        line = line.strip()
+        if 'sbt script version:' in line:
+            return line.split()[-1]
+
+    return None

siliconcompiler/tools/chisel/convert.py

@@ -0,0 +1,140 @@
+import os
+import shutil
+import glob
+from siliconcompiler.tools._common import add_frontend_requires, get_tool_task, has_input_files
+from siliconcompiler import sc_open, SiliconCompilerError
+
+
+def setup(chip):
+    '''
+    Performs high level synthesis to generate a verilog output
+    '''
+
+    if not has_input_files(chip, 'input', 'config', 'chisel') and \
+       not has_input_files(chip, 'input', 'hll', 'scala'):
+        return "no files in [input,hll,scala] or [input,config,chisel]"
+
+    tool = 'chisel'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    # Standard Setup
+    refdir = 'tools/' + tool
+    chip.set('tool', tool, 'exe', 'sbt')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=1.5.5', clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler', clobber=False)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'option', ['-batch',
+                                                    '--no-share',
+                                                    '--no-global'],
+             step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'application',
+             'Application name of the chisel program',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'argument',
+             'Arguments for the chisel build',
+             field='help')
+
+    # Input/Output requirements
+    if chip.valid('input', 'config', 'chisel') and \
+       chip.get('input', 'config', 'chisel', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require', 'input,config,chisel',
+                 step=step, index=index)
+        if len(chip.get('input', 'config', 'chisel', step=step, index=index)) != 1:
+            raise SiliconCompilerError('Only one build.sbt is supported.', chip=chip)
+
+    if chip.valid('input', 'hll', 'scala') and \
+       chip.get('input', 'hll', 'scala', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require', 'input,hll,scala',
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', chip.top() + '.v', step=step, index=index)
+
+    add_frontend_requires(chip, [])
+
+
+def pre_process(chip):
+    tool = 'chisel'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    refdir = chip.find_files('tool', tool, 'task', task, 'refdir', step=step, index=index)[0]
+
+    if chip.valid('input', 'config', 'chisel') and \
+       chip.get('input', 'config', 'chisel', step=step, index=index):
+        build_file = chip.find_files('input', 'config', 'chisel', step=step, index=index)[0]
+        work_dir = chip.getworkdir(step=step, index=index)
+        build_dir = os.path.dirname(build_file)
+        # Expect file tree from: https://www.scala-sbt.org/1.x/docs/Directories.html
+        # copy build.sbt
+        # copy src/
+        shutil.copyfile(build_file, os.path.join(work_dir, 'build.sbt'))
+        shutil.copytree(os.path.join(build_dir, 'src'),
+                        os.path.join(work_dir, 'src'))
+        if os.path.exists(os.path.join(build_dir, 'project')):
+            shutil.copytree(os.path.join(build_dir, 'project'),
+                            os.path.join(work_dir, 'project'))
+        return
+
+    for filename in ('build.sbt', 'SCDriver.scala'):
+        src = os.path.join(refdir, filename)
+        dst = filename
+        shutil.copyfile(src, dst)
+
+    # Chisel driver relies on Scala files being collected into '$CWD/inputs'
+    chip.set('input', 'hll', 'scala', True, field='copy')
+    chip.collect(directory=os.path.join(chip.getworkdir(step=step, index=index), 'inputs'))
+
+
+def runtime_options(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    runMain = ["runMain"]
+    if chip.valid('input', 'config', 'chisel') and \
+       chip.get('input', 'config', 'chisel', step=step, index=index):
+        app = design
+        if chip.valid('tool', tool, 'task', task, 'var', 'application') and \
+           chip.get('tool', tool, 'task', task, 'var', 'application', step=step, index=index):
+            app = chip.get('tool', tool, 'task', task, 'var', 'application',
+                           step=step, index=index)[0]
+
+        runMain.append(f"{app}")
+
+        if chip.valid('tool', tool, 'task', task, 'var', 'argument') and \
+           chip.get('tool', tool, 'task', task, 'var', 'argument', step=step, index=index):
+            runMain.extend(chip.get('tool', tool, 'task', task, 'var', 'argument',
+                                    step=step, index=index))
+        runMain.append("--")
+
+        runMain.append("--target-dir chisel-output")
+    else:
+        # Use built in driver
+        runMain.append("SCDriver")
+        runMain.append(f"--module {chip.top(step=step, index=index)}")
+
+        runMain.append(f"--output-file ../outputs/{design}.v")
+
+    return [f'"{" ".join(runMain)}"']
+
+
+def post_process(chip):
+    chisel_path = 'chisel-output'
+    if os.path.exists(chisel_path):
+        design = chip.top()
+        with open(f'outputs/{design}.v', 'w') as out:
+            for f in glob.glob(os.path.join(chisel_path, '*.v')):
+                with sc_open(f) as i_file:
+                    out.writelines(i_file.readlines())

siliconcompiler/tools/execute/exec_input.py

@@ -0,0 +1,41 @@
+import glob
+import os
+import stat
+from siliconcompiler.tools.execute.execute import setup as tool_setup
+from siliconcompiler.tools._common import input_provides, get_tool_task
+
+
+def setup(chip):
+    '''
+    Execute the output of the previous step directly.
+    This only works if the task receives a single file.
+    '''
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'input',
+             list(input_provides(chip, step, index).keys()),
+             step=step, index=index)
+
+
+def pre_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, _ = get_tool_task(chip, step, index)
+
+    exec = None
+    for fin in glob.glob('inputs/*'):
+        if fin.endswith('.pkg.json'):
+            continue
+        exec = os.path.abspath(fin)
+        break
+
+    if not exec:
+        chip.error(f'{step}{index} did not receive an executable file')
+
+    chip.set('tool', tool, 'exe', exec)
+
+    os.chmod(exec, stat.S_IRUSR | stat.S_IWUSR | stat.S_IXUSR)

siliconcompiler/tools/execute/execute.py

@@ -0,0 +1,17 @@
+'''
+This tool is used to execute the output of a previous step.
+For example, if the flow contains a compile step which generates the
+next executable needed in the flow.
+'''
+
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', ":exe:", clobber=False)
+    chip.set('tool', tool, 'task', task, 'option', [], step=step, index=index, clobber=False)

siliconcompiler/tools/genfasm/bitstream.py

@@ -0,0 +1,61 @@
+import os
+import shutil
+from siliconcompiler.tools.genfasm import genfasm
+from siliconcompiler.tools.vpr import vpr
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Generates a bitstream
+    '''
+    genfasm.setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', "^Warning",
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', "^Error",
+             step=step, index=index, clobber=False)
+
+    design = chip.top()
+
+    chip.set('tool', tool, 'task', task, 'input', design + '.route', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'input', design + '.blif', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'input', design + '.net', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'input', design + '.place', step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', design + '.fasm', step=step, index=index)
+
+
+def runtime_options(chip):
+    options = vpr.runtime_options(chip)
+
+    design = chip.top()
+
+    blif = f"inputs/{design}.blif"
+    options.append(blif)
+
+    options.append(f'--net_file inputs/{design}.net')
+    options.append(f'--place_file inputs/{design}.place')
+    options.append(f'--route_file inputs/{design}.route')
+
+    return options
+
+################################
+# Post_process (post executable)
+################################
+
+
+def post_process(chip):
+    ''' Tool specific function to run after step execution
+    '''
+    vpr.vpr_post_process(chip)
+
+    design = chip.top()
+    shutil.move(f'{design}.fasm', 'outputs')

siliconcompiler/tools/genfasm/genfasm.py

@@ -0,0 +1,40 @@
+from siliconcompiler.tools.vpr.vpr import parse_version as vpr_parse_version
+from siliconcompiler.tools.vpr.vpr import normalize_version as vpr_normalize_version
+
+'''
+Generate a `FSAM <https://github.com/chipsalliance/fasm>`_ file from the output of
+`VPR <https://github.com/verilog-to-routing/vtr-verilog-to-routing>`_
+
+Documentation: https://docs.verilogtorouting.org/en/latest/utils/fasm/
+
+Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/utils/fasm
+'''
+
+
+######################################################################
+# Make Docs
+######################################################################
+def make_docs(chip):
+    from siliconcompiler.tools.genfasm.bitstream import setup
+    setup(chip)
+    return chip
+
+
+def setup(chip):
+    chip.set('tool', 'genfasm', 'exe', 'genfasm', clobber=False)
+    chip.set('tool', 'genfasm', 'vswitch', '--version')
+    chip.set('tool', 'genfasm', 'version', '>=8.1.0', clobber=False)
+
+
+def parse_version(chip):
+    return vpr_parse_version(chip)
+
+
+def normalize_version(chip):
+    return vpr_normalize_version(chip)
+
+
+##################################################
+if __name__ == "__main__":
+    chip = make_docs()
+    chip.write_manifest("genfasm.json")