siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -0,0 +1,74 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_tool opensta
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+# Design
+set sc_design [sc_top]
+
+# APR Parameters
+set sc_targetlibs [sc_get_asic_libraries logic]
+set sc_delaymodel [sc_cfg_get asic delaymodel]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+
+###############################
+# Optional
+###############################
+
+# MACROS
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+###############################
+# Read Files
+###############################
+
+# Read Liberty
+puts "Defining timing corners: $sc_scenarios"
+define_corners {*}$sc_scenarios
+foreach lib "$sc_targetlibs $sc_macrolibs" {
+    #Liberty
+    foreach corner $sc_scenarios {
+        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
+                foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
+                    puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"
+                    read_liberty -corner $corner $lib_file
+                }
+                break
+            }
+        }
+    }
+}
+
+# Report cells
+foreach cell [get_lib_cells *] {
+    puts [get_full_name $cell]
+
+    set pins [get_lib_pins -quiet [get_full_name $cell]/*]
+    if { [llength $pins] == 0 } {
+        puts "  No pins"
+        continue
+    }
+    foreach pin $pins {
+        puts "  [get_full_name $pin] [get_property $pin direction]"
+        set cap [expr { [sta::capacitance_ui_sta [get_property $pin capacitance]] / 1e-15 }]
+        puts "    Capacitance:      [format %.3f $cap]fF"
+        set res [sta::resistance_ui_sta [get_property $pin drive_resistance]]
+        puts "    Drive resistance: [format %.3f $res]ohm"
+        set delay [expr { [sta::time_ui_sta [get_property $pin intrinsic_delay]] / 1e-12 }]
+        puts "    Intrinsic delay:  [format %.3f $delay]ps"
+    }
+}

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -0,0 +1,268 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_tool opensta
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+# Design
+set sc_design [sc_top]
+
+# APR Parameters
+set sc_targetlibs [sc_get_asic_libraries logic]
+set sc_mainlib [lindex $sc_targetlibs 0]
+set sc_delaymodel [sc_cfg_get asic delaymodel]
+set sc_timing_mode [lindex [sc_cfg_tool_task_get var timing_mode] 0]
+set sc_scenarios []
+foreach corner [dict keys [sc_cfg_get constraint timing]] {
+    if { [sc_cfg_get constraint timing $corner mode] == $sc_timing_mode } {
+        lappend sc_scenarios $corner
+    }
+}
+
+###############################
+# Optional
+###############################
+
+# MACROS
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+###############################
+# Read Files
+###############################
+
+# Read Liberty
+puts "Defining timing corners: $sc_scenarios"
+define_corners {*}$sc_scenarios
+foreach lib "$sc_targetlibs $sc_macrolibs" {
+    #Liberty
+    foreach corner $sc_scenarios {
+        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
+                foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
+                    puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"
+                    read_liberty -corner $corner $lib_file
+                }
+                break
+            }
+        }
+    }
+}
+
+# Read Verilog
+if { [file exists "inputs/${sc_design}.vg"] } {
+    puts "Reading netlist verilog: inputs/${sc_design}.vg"
+    read_verilog "inputs/${sc_design}.vg"
+} else {
+    foreach netlist [sc_cfg_get input netlist verilog] {
+        puts "Reading netlist verilog: ${netlist}"
+        read_verilog $netlist
+    }
+}
+link_design $sc_design
+
+# Read SDC (in order of priority)
+# TODO: add logic for reading from ['constraint', ...] once we support MCMM
+if { [file exists "inputs/${sc_design}.sdc"] } {
+    # get from previous step
+    puts "Reading SDC: inputs/${sc_design}.sdc"
+    read_sdc "inputs/${sc_design}.sdc"
+} elseif { [sc_cfg_exists input constraint sdc] } {
+    foreach sdc [sc_cfg_get input constraint sdc] {
+        # read step constraint if exists
+        puts "Reading SDC: ${sdc}"
+        read_sdc $sdc
+    }
+
+    set sdc_files []
+    foreach corner $sc_scenarios {
+        foreach sdc [sc_cfg_get constraint timing $corner file] {
+            if { [lsearch -exact $sdc_files $sdc] == -1 } {
+                # read step constraint if exists
+                puts "Reading mode (${sc_timing_mode}) SDC: ${sdc}"
+                lappend sdc_files $sdc
+                read_sdc $sdc
+            }
+        }
+    }
+} else {
+    # fall back on default auto generated constraints file
+    set sdc "[sc_cfg_tool_task_get file opensta_generic_sdc]"
+    puts "Reading SDC: ${sdc}"
+    puts "Warning: Defaulting back to default SDC"
+    read_sdc "${sdc}"
+}
+
+###############################
+
+foreach corner $sc_scenarios {
+    set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+
+    set spef_file "inputs/${sc_design}.${pex_corner}.spef"
+    if { [file exists $spef_file] } {
+        puts "Reading SPEF ($corner): $spef_file"
+        read_spef -corner $corner $spef_file
+    }
+}
+
+###############################
+# Source helper functions
+###############################
+
+source "$sc_refdir/sc_procs.tcl"
+
+###############################
+# Report Metrics
+###############################
+
+set opensta_top_n_paths [lindex [sc_cfg_tool_task_get var top_n_paths] 0]
+
+set fields "{capacitance slew input_pins nets fanout}"
+set PREFIX "SC_METRIC:"
+
+puts "$PREFIX timeunit"
+puts [sta::unit_scale_abbreviation time]
+
+puts "$PREFIX report_checks -path_delay max"
+report_checks -fields $fields -path_delay max -format full_clock_expanded \
+    > reports/setup.rpt
+sc_display_report reports/setup.rpt
+report_checks -path_delay max -group_count $opensta_top_n_paths \
+    > reports/setup.topN.rpt
+
+puts "$PREFIX setupslack"
+report_worst_slack -max > reports/worst_slack.setup.rpt
+sc_display_report reports/worst_slack.setup.rpt
+
+puts "$PREFIX setuppaths"
+puts [sta::endpoint_violation_count max]
+
+puts "$PREFIX setuptns"
+report_tns > reports/total_negative_slack.rpt
+sc_display_report reports/total_negative_slack.rpt
+
+puts "$PREFIX report_checks -path_delay min"
+report_checks -fields $fields -path_delay min -format full_clock_expanded \
+    > reports/hold.rpt
+sc_display_report reports/hold.rpt
+report_checks -path_delay min -group_count $opensta_top_n_paths \
+    > reports/hold.topN.rpt
+
+puts "$PREFIX holdslack"
+report_worst_slack -min > reports/worst_slack.hold.rpt
+sc_display_report reports/worst_slack.hold.rpt
+
+puts "$PREFIX holdpaths"
+puts [sta::endpoint_violation_count max]
+
+puts "$PREFIX holdtns"
+puts "tns [sta::time_sta_ui [sta::total_negative_slack_cmd min]]"
+
+report_checks -fields $fields -unconstrained -format full_clock_expanded \
+    > reports/unconstrained.rpt
+sc_display_report reports/unconstrained.rpt
+report_checks -unconstrained -group_count $opensta_top_n_paths \
+    > reports/unconstrained.topN.rpt
+
+if { [llength [all_clocks]] > 0 } {
+    puts "$PREFIX setupskew"
+    report_clock_skew -setup -digits 4 > reports/skew.setup.rpt
+    sc_display_report reports/skew.setup.rpt
+    puts "$PREFIX holdskew"
+    report_clock_skew -hold -digits 4 > reports/skew.hold.rpt
+    sc_display_report reports/skew.hold.rpt
+}
+
+puts "$PREFIX drvs"
+report_check_types -max_slew -max_capacitance -max_fanout -violators -no_line_splits \
+    > reports/drv_violators.rpt
+sc_display_report reports/drv_violators.rpt
+
+# Model on: https://github.com/The-OpenROAD-Project/OpenSTA/blob/f913c3ddbb3e7b4364ed4437c65ac78c4da9174b/tcl/Search.tcl#L1078
+set fmax_metric 0
+foreach clk [sta::sort_by_name [all_clocks]] {
+    puts "$PREFIX fmax"
+    set clk_name [get_name $clk]
+    set min_period [sta::find_clk_min_period $clk 1]
+    if { $min_period == 0.0 } {
+        continue
+    }
+    set fmax [expr { 1.0 / $min_period }]
+    puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
+    set fmax_metric [expr { max($fmax_metric, $fmax) }]
+}
+if { $fmax_metric > 0 } {
+    puts "fmax = [format %.2f [expr { $fmax_metric / 1e6 }]] MHz"
+}
+
+# get logic depth of design
+puts "$PREFIX logicdepth"
+puts [sc_count_logic_depth]
+
+puts "$PREFIX power"
+foreach corner [sta::corners] {
+    set corner_name [$corner name]
+    puts "Power for corner: $corner_name"
+    report_power -corner $corner_name > reports/power.${corner_name}.rpt
+    sc_display_report reports/power.${corner_name}.rpt
+}
+
+puts "$PREFIX cells"
+puts [llength [get_cells *]]
+
+puts "$PREFIX cellarea"
+puts [sc_design_area]
+
+# get number of nets in design
+puts "$PREFIX nets"
+puts [llength [get_nets *]]
+
+# get number of registers
+puts "$PREFIX registers"
+puts [llength [all_registers]]
+
+# get number of buffers
+set bufs 0
+set invs 0
+foreach inst [get_cells -hierarchical *] {
+    set cell [$inst cell]
+    if { $cell == "NULL" } {
+        continue
+    }
+    set liberty_cell [$cell liberty_cell]
+    if { $liberty_cell == "NULL" } {
+        continue
+    }
+    if { [$liberty_cell is_buffer] } {
+        incr bufs
+    } elseif { [$liberty_cell is_inverter] } {
+        incr invs
+    }
+}
+puts "$PREFIX buffers"
+puts $bufs
+puts "$PREFIX inverters"
+puts $invs
+
+puts "$PREFIX pins"
+puts [llength [get_ports *]]
+
+# get number of unconstrained endpoints
+with_output_to_variable endpoints {check_setup -unconstrained_endpoints}
+set unconstrained_endpoints [regexp -all -inline {[0-9]+} $endpoints]
+if { $unconstrained_endpoints == "" } {
+    set unconstrained_endpoints 0
+}
+puts "$PREFIX unconstrained"
+puts $unconstrained_endpoints

siliconcompiler/tools/opensta/timing.py

@@ -0,0 +1,214 @@
+import os
+import re
+from siliconcompiler import sc_open, SiliconCompilerError
+from siliconcompiler.tools.opensta import setup as tool_setup
+from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
+from siliconcompiler.tools._common import input_provides, add_common_file, \
+    get_tool_task, record_metric
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_timing_modes
+
+
+def setup(chip):
+    '''
+    Generate a static timing reports.
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    tool_setup(chip)
+
+    chip.set('tool', tool, 'task', task, 'script', 'sc_timing.tcl',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index)
+
+    design = chip.top()
+    if f'{design}.vg' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', f'{design}.vg',
+                 step=step, index=index)
+    else:
+        chip.set('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
+                 step=step, index=index)
+
+    if f'{design}.sdc' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', f'{design}.sdc',
+                 step=step, index=index)
+    elif chip.valid('input', 'constraint', 'sdc') and \
+            chip.get('input', 'constraint', 'sdc', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require', 'input,constraint,sdc',
+                 step=step, index=index)
+
+    set_tool_task_var(chip, param_key='top_n_paths',
+                      default_value='10',
+                      schelp='number of paths to report timing for')
+
+    modes = get_timing_modes(chip)
+
+    set_tool_task_var(chip, param_key='timing_mode',
+                      default_value=modes[0],
+                      schelp='timing mode to use')
+
+    timing_mode = chip.get('tool', tool, 'task', task, 'var', 'timing_mode',
+                           step=step, index=index)[0]
+    if timing_mode not in modes:
+        raise SiliconCompilerError(
+            f'{timing_mode} mode is not present in timing constraints', chip=chip)
+
+    for scenario in chip.getkeys('constraint', 'timing'):
+        if chip.get('constraint', 'timing', scenario, 'mode',
+                    step=step, index=index) != timing_mode:
+            continue
+        if chip.get('constraint', 'timing', scenario, 'file', step=step, index=index):
+            chip.add('tool', tool, 'task', task, 'require', f'constraint,timing,{scenario},file',
+                     step=step, index=index)
+
+    add_common_file(chip, 'opensta_generic_sdc', 'sdc/sc_constraints.sdc')
+
+
+def __report_map(chip, metric, basefile):
+    corners = chip.getkeys('constraint', 'timing')
+    mapping = {
+        "power": [f"reports/power.{corner}.rpt" for corner in corners],
+        "unconstrained": ["reports/unconstrained.rpt", "reports/unconstrained.topN.rpt"],
+        "setuppaths": ["reports/setup.rpt", "reports/setup.topN.rpt"],
+        "holdpaths": ["reports/hold.rpt", "reports/hold.topN.rpt"],
+        "holdslack": ["reports/hold.rpt", "reports/hold.topN.rpt"],
+        "setupslack": ["reports/setup.rpt", "reports/setup.topN.rpt"],
+        "setuptns": ["reports/setup.rpt", "reports/setup.topN.rpt"],
+        "holdtns": ["reports/hold.rpt", "reports/hold.topN.rpt"],
+        "setupskew": ["reports/skew.setup.rpt", "reports/setup.rpt", "reports/setup.topN.rpt"],
+        "holdskew": ["reports/skew.hold.rpt", "reports/hold.rpt", "reports/hold.topN.rpt"]
+    }
+
+    if metric in mapping:
+        paths = [basefile]
+        for path in mapping[metric]:
+            if os.path.exists(path):
+                paths.append(path)
+        return paths
+    return [basefile]
+
+
+################################
+# Post_process (post executable)
+################################
+def post_process(chip):
+    '''
+    Tool specific function to run after step execution
+    '''
+
+    # Check log file for errors and statistics
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    logfile = f"{step}.log"
+
+    peakpower = []
+    leakagepower = []
+    skews = {}
+    # parsing log file
+    with sc_open(logfile) as f:
+        timescale = "s"
+        metric = None
+        for line in f:
+            metricmatch = re.search(r'^SC_METRIC:\s+(\w+)', line)
+            value = re.search(r'(\d*\.?\d)*', line)
+            fmax = re.search(r'fmax = (\d*\.?\d*)', line)
+            tns = re.search(r'^tns (.*)', line)
+            slack = re.search(r'^worst slack (.*)', line)
+            skew = re.search(r'^\s*(.*)\s+(.*) skew', line)
+            power = re.search(r'^Total(.*)', line)
+            if metricmatch:
+                metric = metricmatch.group(1)
+                continue
+
+            if metric:
+                if metric == 'timeunit':
+                    timescale = f'{line.strip()}s'
+                    metric = None
+                if metric == 'fmax':
+                    if fmax:
+                        record_metric(chip, step, index, 'fmax', float(fmax.group(1)),
+                                      __report_map(chip, 'fmax', logfile),
+                                      source_unit='MHz')
+                        metric = None
+                elif metric == 'power':
+                    if power:
+                        powerlist = power.group(1).split()
+                        leakage = powerlist[2]
+                        total = powerlist[3]
+
+                        peakpower.append(float(total))
+                        leakagepower.append(float(leakage))
+
+                        metric = None
+                elif metric == 'cellarea':
+                    record_metric(chip, step, index, 'cellarea', float(value.group(0)),
+                                  __report_map(chip, 'cellarea', logfile),
+                                  source_unit='um^2')
+                    metric = None
+                elif metric in ('logicdepth',
+                                'cells',
+                                'nets',
+                                'buffers',
+                                'inverters',
+                                'registers',
+                                'unconstrained',
+                                'pins',
+                                'setuppaths',
+                                'holdpaths'):
+                    record_metric(chip, step, index, metric, int(value.group(0)),
+                                  __report_map(chip, metric, logfile))
+                    metric = None
+                elif metric in ('holdslack', 'setupslack'):
+                    if slack:
+                        record_metric(chip, step, index, metric, float(slack.group(1)),
+                                      __report_map(chip, metric, logfile),
+                                      source_unit=timescale)
+                        metric = None
+                elif metric in ('setuptns', 'holdtns'):
+                    if tns:
+                        record_metric(chip, step, index, metric, float(tns.group(1)),
+                                      __report_map(chip, metric, logfile),
+                                      source_unit=timescale)
+                        metric = None
+                elif metric in ('setupskew', 'holdskew'):
+                    if skew:
+                        skews.setdefault(skew.group(2), []).append(float(skew.group(1)))
+                else:
+                    metric = None
+
+    if peakpower:
+        record_metric(chip, step, index, 'peakpower', max(peakpower),
+                      __report_map(chip, 'peakpower', logfile),
+                      source_unit='W')
+    if leakagepower:
+        record_metric(chip, step, index, 'leakagepower', max(leakagepower),
+                      __report_map(chip, 'leakagepower', logfile),
+                      source_unit='W')
+    if skews:
+        for skewtype, values in skews.items():
+            skew = f'{skewtype}skew'
+            record_metric(chip, step, index, skew, max(values),
+                          __report_map(chip, skew, logfile),
+                          source_unit=timescale)
+
+    drv_report = "reports/drv_violators.rpt"
+    if os.path.exists(drv_report):
+        drv_count = 0
+        with sc_open(drv_report) as f:
+            for line in f:
+                if re.search(r'\(VIOLATED\)$', line):
+                    drv_count += 1
+
+        record_metric(chip, step, index, 'drvs', drv_count,
+                      [drv_report, logfile])
+
+
+################################
+# Runtime options
+################################
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/slang/__init__.py

@@ -0,0 +1,49 @@
+'''
+slang is a software library that provides various components for lexing, parsing, type checking,
+and elaborating SystemVerilog code. It comes with an executable tool that can compile and lint
+any SystemVerilog project, but it is also intended to be usable as a front end for synthesis
+tools, simulators, linters, code editors, and refactoring tools.
+
+Documentation: https://sv-lang.com/
+
+Sources: https://github.com/MikePopoloski/slang
+
+Installation: https://sv-lang.com/building.html
+'''
+import re
+from siliconcompiler import sc_open
+from siliconcompiler.tools._common import get_tool_task, record_metric
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    tool = 'slang'
+
+    # Standard Setup
+    chip.set('tool', tool, 'exe', 'slang')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=6.0', clobber=False)
+
+
+def parse_version(stdout):
+    # slang --version output looks like:
+    # slang version 6.0.121+c2c478cf
+
+    # grab version # by splitting on whitespace
+    return stdout.strip().split()[-1].split('+')[0]
+
+
+def post_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    log = f'{step}.log'
+    with sc_open(log) as f:
+        for line in f:
+            match = re.search(r'(\d+) errors, (\d+) warnings', line)
+            if match:
+                record_metric(chip, step, index, 'errors', match.group(1), log)
+                record_metric(chip, step, index, 'warnings', match.group(2), log)