siliconcompiler 0.26.5__py3-none-any.whl

siliconcompiler/sphinx_ext/schemagen.py

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+import os
+from docutils import nodes
+from sphinx.util.nodes import nested_parse_with_titles
+from docutils.statemachine import ViewList
+from sphinx.util.docutils import SphinxDirective
+
+import siliconcompiler
+from siliconcompiler.schema import Schema
+from siliconcompiler.sphinx_ext.utils import (
+    strong,
+    code,
+    para,
+    keypath,
+    build_table,
+    build_section_with_target,
+    build_list
+)
+from siliconcompiler.schema import utils
+
+
+# Main Sphinx plugin
+class SchemaGen(SphinxDirective):
+
+    def run(self):
+        cfg_path = os.path.dirname(siliconcompiler.__file__)
+        self.env.note_dependency(os.path.join(cfg_path, 'schema', 'schema_cfg.py'))
+        self.env.note_dependency(__file__)
+        self.env.note_dependency(utils.__file__)
+
+        schema = Schema().cfg
+
+        return self.process_schema(schema)
+
+    def process_schema(self, schema, parents=[]):
+        if 'help' in schema:
+            entries = [[strong('Description'), para(schema['shorthelp'])],
+                       [strong('Type'), para(schema['type'])]]
+
+            if schema['pernode'] != 'never':
+                entries.append([strong('Per step/index'), para(schema['pernode'])])
+
+            if 'enum' in schema['type']:
+                entries.append([strong('Allowed Values'),
+                                build_list([code(val) for val in schema['enum']])])
+
+            if 'unit' in schema:
+                entries.append([strong('Unit'), para(schema['unit'])])
+
+            defvalue = schema['node']['default']['default']['value']
+            switch_list = [code(switch) for switch in schema['switch']]
+            entries.extend([[strong('Default Value'), para(defvalue)],
+                            [strong('CLI Switch'), build_list(switch_list)]])
+
+            examples = {}
+            for example in schema['example']:
+                name, ex = example.split(':', 1)
+                examples.setdefault(name, []).append(ex)
+
+            for name, exs in examples.items():
+                examples = [code(ex.strip()) for ex in exs]
+                p = None
+                for ex in examples:
+                    if not p:
+                        p = para("")
+                    else:
+                        p += para("")
+                    p += ex
+                entries.append([strong(f'Example ({name.upper()})'), p])
+
+            table = build_table(entries, colwidths=[25, 75])
+            body = self.parse_rst(utils.trim(schema['help']))
+
+            return [table, body]
+        else:
+            sections = []
+            for key in schema.keys():
+                if key == 'default':
+                    for n in self.process_schema(schema['default'], parents=parents):
+                        sections.append(n)
+                elif key not in ('history', 'library'):
+                    section_key = 'param-' + '-'.join(parents + [key])
+                    section = build_section_with_target(key, section_key, self.state.document)
+                    for n in self.process_schema(schema[key], parents=parents + [key]):
+                        section += n
+                    sections.append(section)
+
+            # Sort all sections alphabetically by title. We may also have nodes
+            # in this list that aren't sections if  `schema` has a 'default'
+            # entry that's a leaf. In this case, we sort this as an empty string
+            # in order to put this node at the beginning of the list.
+            return sorted(sections, key=lambda s: s[0][0] if isinstance(s, nodes.section) else '')
+
+    def parse_rst(self, content):
+        rst = ViewList()
+        # use fake filename 'inline' for error # reporting
+        for i, line in enumerate(content.split('\n')):
+            rst.append(line, 'inline', i)
+        body = nodes.paragraph()
+        nested_parse_with_titles(self.state, rst, body)
+
+        return body
+
+
+class CategorySummary(SphinxDirective):
+
+    option_spec = {'category': str}
+
+    def run(self):
+        self.env.note_dependency(__file__)
+        category = self.options['category']
+
+        # List of documentation objects to return.
+        new_doc = []
+        section = nodes.section(ids=[nodes.make_id(f'{category}_summary')])
+
+        chip = siliconcompiler.Chip('<design>')
+
+        table = [[strong('parameter'), strong('description')]]
+
+        # Descend through defaults until we find the real items
+        prefix = [category]
+        while 'default' in chip.getdict(*prefix).keys():
+            prefix.append('default')
+
+        for item in chip.getkeys(*prefix):
+            key = para('')
+            key += keypath([*prefix, item], self.env.docname)
+            if 'shorthelp' in chip.getkeys(*prefix, item):
+                shorthelp = chip.get(*prefix, item, field='shorthelp')
+                table.append([key, para(shorthelp)])
+            else:
+                table.append([key, para("Contains sub-tree of parameters. See Schema.")])
+        section += build_table(table)
+        new_doc += section
+
+        return new_doc
+
+
+class CategoryGroupTable(SphinxDirective):
+
+    def count_keys(self, schema, *keypath):
+        cfgs = schema.getdict(*keypath)
+        count = 0
+        for key, cfg in cfgs.items():
+            if schema._is_leaf(cfg):
+                count += 1
+            else:
+                count += self.count_keys(schema, *keypath, key)
+
+        return count
+
+    def run(self):
+        self.env.note_dependency(__file__)
+
+        desc = {
+            "option": "Compilation options",
+            "tool": "Individual tool settings",
+            "flowgraph": "Execution flow definition",
+            "pdk": "PDK related settings",
+            "asic": "ASIC related settings",
+            "fpga": "FPGA related settings",
+            "checklist": "Checklist related settings",
+            "constraint": "Design constraint settings",
+            "metric": "Metric tracking",
+            "record": "Compilation history tracking",
+            "package": "Packaging manifest",
+            "datasheet": "Design interface specifications",
+
+            # Nothing to document
+            "library": "",
+            "history": "",
+            "input": "",
+            "output": "",
+            "schemaversion": "",
+            "design": "",
+            "arg": "",
+        }
+
+        schema = Schema()
+
+        # Check if all groups have desc
+        for group in schema.getkeys():
+            if group not in desc:
+                raise ValueError(f"{group} not found in group descriptions")
+
+        # Check if all groups have schema
+        for group in desc.keys():
+            if group not in schema.getkeys():
+                raise ValueError(f"{group} not found in schema")
+
+        table = [[strong('Group'), strong('Parameters'), strong('Description')]]
+
+        total = 0
+        for group in schema.getkeys():
+            text = desc[group]
+            if len(text) == 0:
+                continue
+
+            key = para('')
+            key += keypath([group], self.env.docname)
+
+            count = self.count_keys(schema, group)
+            total += count
+
+            table.append([key, para(f'{count}'), para(text)])
+
+        table.append([strong('Total'), para(f'{total}'), para('')])
+
+        return build_table(table)
+
+
+def setup(app):
+    app.add_directive('schemagen', SchemaGen)
+    app.add_directive('schema_category_summary', CategorySummary)
+    app.add_directive('schema_group_summary', CategoryGroupTable)
+
+    return {
+        'version': '0.1',
+        'parallel_read_safe': True,
+        'parallel_write_safe': True,
+    }

siliconcompiler/sphinx_ext/utils.py

@@ -0,0 +1,166 @@
+from docutils import nodes
+import sphinx.addnodes
+
+from siliconcompiler.schema import Schema
+
+
+# Docutils helpers
+def build_table(items, colwidths=None, colspec=None):
+    '''Create table node.
+
+    Args:
+        - items (list of list of nodes): nested list of table contents
+        - colwidths (list of nums): relative column widths (seems to affect HTML
+            builder only)
+        - colspec (str): LaTeX column spec for overriding Sphinx defaults
+
+    Returns list of nodes, since there may be an associated TabularColumn node
+    that hints at sizing in PDF output.
+    '''
+    if colwidths is None:
+        colwidths = [1] * len(items[0])  # default to equal spacing
+    else:
+        assert len(colwidths) == len(items[0])
+
+    return_nodes = []
+    if colspec is not None:
+        colspec_node = sphinx.addnodes.tabular_col_spec()
+        colspec_node['spec'] = colspec
+        return_nodes.append(colspec_node)
+
+    table = nodes.table()
+    table['classes'] = ['longtable']
+
+    group = nodes.tgroup(cols=len(items[0]))
+    table += group
+    for colwidth in colwidths:
+        group += nodes.colspec(colwidth=colwidth)
+
+    body = nodes.tbody()
+    group += body
+
+    for row in items:
+        row_node = nodes.row()
+        body += row_node
+        for col in row:
+            entry = nodes.entry()
+            row_node += entry
+            entry += col
+
+    return_nodes.append(table)
+
+    return return_nodes
+
+
+def build_section(text, key):
+    sec = nodes.section(ids=[get_ref_id(key)])
+    sec += nodes.title(text=text)
+    return sec
+
+
+def build_section_with_target(text, key, ctx):
+    id = get_ref_id(key)
+    target = nodes.target('', '', ids=[id], names=[id])
+    sec = nodes.section(ids=[id])
+    sec += nodes.title(text=text)
+
+    # We don't need to add target node to hierarchy, just need to call this
+    # function.
+    ctx.note_explicit_target(target)
+
+    return sec
+
+
+def get_ref_id(key):
+    return nodes.make_id(key + "-ref")
+
+
+def para(text):
+    return nodes.paragraph(text=text)
+
+
+def code(text):
+    return nodes.literal(text=text)
+
+
+def literalblock(text):
+    block = nodes.literal_block(text=text)
+    block['language'] = 'none'
+    return block
+
+
+def strong(text):
+    p = nodes.paragraph()
+    p += nodes.strong(text=text)
+    return p
+
+
+def image(src, center=False):
+    i = nodes.image()
+    i['uri'] = '/' + src
+    if center:
+        i['align'] = 'center'
+    return i
+
+
+def link(url, text=None):
+    if text is None:
+        text = url
+    return nodes.reference(internal=False, refuri=url, text=text)
+
+
+def build_list(items, enumerated=False):
+    if enumerated:
+        list = nodes.enumerated_list()
+    else:
+        list = nodes.bullet_list()
+
+    for item in items:
+        docutils_item = nodes.list_item()
+        docutils_item += item
+        list += docutils_item
+
+    return list
+
+
+def keypath(key_path, refdoc, key_text=None):
+    '''Helper function for displaying Schema keypaths.'''
+    text_parts = []
+    key_parts = []
+    cfg = Schema().cfg
+    for key in key_path:
+        if list(cfg.keys()) != ['default']:
+            text_parts.append(f"'{key}'")
+            key_parts.append(key)
+            try:
+                cfg = cfg[key]
+            except KeyError:
+                raise ValueError(f'Invalid keypath {key_path}')
+        else:
+            cfg = cfg['default']
+            if key.startswith('<') and key.endswith('>'):
+                # Placeholder
+                text_parts.append(key)
+            else:
+                # Fully-qualified
+                text_parts.append(f"'{key}'")
+
+    if 'help' not in cfg:
+        # Not leaf
+        text_parts.append('...')
+
+    if key_text:
+        text_parts = key_text
+    text = f"[{', '.join(text_parts)}]"
+    refid = get_ref_id('param-' + '-'.join(key_parts))
+
+    opt = {'refdoc': refdoc,
+           'refdomain': 'sc',
+           'reftype': 'ref',
+           'refexplicit': True,
+           'refwarn': True}
+    refnode = sphinx.addnodes.pending_xref('keypath', **opt)
+    refnode['reftarget'] = refid
+    refnode += code(text)
+
+    return refnode

siliconcompiler/targets/asap7_demo.py

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+import siliconcompiler
+from siliconcompiler.flows import asicflow, synflow
+
+from lambdapdk import asap7
+from lambdapdk.asap7.libs import asap7sc7p5t
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip, syn_np=1, floorplan_np=1, physyn_np=1, place_np=1, cts_np=1, route_np=1,
+          timing_np=1):
+    '''
+    ASAP7 Demo Target
+    '''
+
+    asic_flow_args = {
+        "syn_np": syn_np,
+        "floorplan_np": floorplan_np,
+        "physyn_np": physyn_np,
+        "place_np": place_np,
+        "cts_np": cts_np,
+        "route_np": route_np
+    }
+
+    # 1. Load PDK, flow, libs combo
+    chip.use(asap7)
+    chip.use(asap7sc7p5t)
+    chip.use(asicflow, **asic_flow_args)
+    chip.use(synflow, syn_np=syn_np, timing_np=timing_np)
+
+    # 2. Select default flow/PDK
+    chip.set('option', 'flow', 'asicflow', clobber=False)
+    chip.set('option', 'pdk', 'asap7', clobber=False)
+    chip.set('option', 'stackup', '10M', clobber=False)
+
+    # 3. Select libraries
+    chip.set('asic', 'logiclib', 'asap7sc7p5t_rvt', clobber=False)
+
+    # 4. Project specific design choices
+    chip.set('asic', 'delaymodel', 'nldm', clobber=False)
+    chip.set('constraint', 'density', 40, clobber=False)
+    chip.set('constraint', 'coremargin', 1, clobber=False)
+
+    # 5. Timing corners
+    pex_corner = 'typical'
+
+    chip.set('constraint', 'timing', 'slow', 'libcorner', 'slow', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'pexcorner', pex_corner, clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'fast', 'libcorner', 'fast', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'pexcorner', pex_corner, clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'typical', 'libcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'pexcorner', pex_corner, clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'check', ['power'], clobber=False)
+
+
+#########################
+if __name__ == "__main__":
+    target = siliconcompiler.Chip('<target>')
+    setup(target)
+    target.write_manifest('asap7_demo.json')

siliconcompiler/targets/asic_demo.py

@@ -0,0 +1,38 @@
+import os
+import siliconcompiler
+from siliconcompiler.targets import skywater130_demo
+
+
+def setup(chip):
+    '''
+    "Self-test" target which builds a small 8-bit counter design as an ASIC,
+    targeting the Skywater130 PDK.
+
+    This target is intended for testing purposes only,
+    to verify that SiliconCompiler is installed and configured correctly.
+    '''
+
+    # Set design name
+    design = 'heartbeat'
+    chip.set('design', design)
+
+    # Load the Sky130 PDK/standard cell library target.
+    chip.load_target(skywater130_demo)
+
+    # Set quiet flag
+    chip.set('option', 'quiet', True, clobber=False)
+
+    # Set die area and clock constraint.
+    chip.set('constraint', 'outline', [(0, 0), (50, 50)], clobber=False)
+    chip.set('constraint', 'corearea', [(5, 5), (45, 45)], clobber=False)
+    chip.clock('clk', period=10)
+
+    # Add source files.
+    chip.input(os.path.join('data', f'{design}.v'), package='siliconcompiler')
+
+
+#########################
+if __name__ == "__main__":
+    target = siliconcompiler.Chip('<target>')
+    setup(target)
+    target.write_manifest('asic_demo.json')

siliconcompiler/targets/fpgaflow_demo.py

@@ -0,0 +1,47 @@
+import siliconcompiler
+from siliconcompiler import SiliconCompilerError
+from siliconcompiler.fpgas import lattice_ice40
+from siliconcompiler.fpgas import vpr_example
+
+from siliconcompiler.flows import fpgaflow
+
+
+############################################################################
+# DOCS
+############################################################################
+def make_docs(chip):
+    chip.set('fpga', 'partname', 'ice40up5k-sg48')
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip):
+    '''
+    Demonstration target for running the open-source fpgaflow.
+    '''
+
+    # 1. Configure fpga part
+    part_name = chip.get('fpga', 'partname')
+    if not part_name:
+        raise SiliconCompilerError('FPGA partname has not been set.', chip=chip)
+
+    # 2.  Load all available FPGAs
+    chip.use(lattice_ice40)
+    chip.use(vpr_example)
+
+    if part_name not in chip.getkeys('fpga'):
+        raise SiliconCompilerError(f'{part_name} has not been loaded', chip=chip)
+
+    # 3. Load flow
+    chip.use(fpgaflow)
+
+    # 4. Select default flow
+    chip.set('option', 'flow', 'fpgaflow', clobber=False)
+
+
+#########################
+if __name__ == "__main__":
+    target = siliconcompiler.Chip('<target>')
+    setup(target)
+    target.write_manifest('fpgaflow_demo.json')

siliconcompiler/targets/freepdk45_demo.py

@@ -0,0 +1,59 @@
+import siliconcompiler
+from siliconcompiler.flows import lintflow, asicflow, asictopflow, synflow
+
+from lambdapdk import freepdk45
+from lambdapdk.freepdk45.libs import nangate45
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip, syn_np=1, floorplan_np=1, physyn_np=1, place_np=1, cts_np=1, route_np=1,
+          timing_np=1):
+    '''
+    FreePDK45 demo target
+    '''
+
+    asic_flow_args = {
+        "syn_np": syn_np,
+        "floorplan_np": floorplan_np,
+        "physyn_np": physyn_np,
+        "place_np": place_np,
+        "cts_np": cts_np,
+        "route_np": route_np
+    }
+
+    # 1. Load PDK, flow, libs combo
+    chip.use(freepdk45)
+    chip.use(nangate45)
+    chip.use(lintflow)
+    chip.use(asicflow, **asic_flow_args)
+    chip.use(synflow, syn_np=syn_np, timing_np=timing_np)
+    chip.use(asictopflow)
+
+    # 2. Set flow and pdk
+    chip.set('option', 'flow', 'asicflow', clobber=False)
+    chip.set('option', 'pdk', 'freepdk45', clobber=False)
+    chip.set('option', 'stackup', '10M', clobber=False)
+
+    # 3. Select libraries
+    chip.set('asic', 'logiclib', 'nangate45', clobber=False)
+
+    # 4. Set project specific design choices
+    chip.set('asic', 'delaymodel', 'nldm', clobber=False)
+    chip.set('constraint', 'density', 40, clobber=False)
+    chip.set('constraint', 'coremargin', 1, clobber=False)
+
+    # 5. Timing corners
+    corner = 'typical'
+    chip.set('constraint', 'timing', 'worst', 'libcorner', corner, clobber=False)
+    chip.set('constraint', 'timing', 'worst', 'pexcorner', corner, clobber=False)
+    chip.set('constraint', 'timing', 'worst', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'worst', 'check', ['setup', 'hold'], clobber=False)
+
+
+#########################
+if __name__ == "__main__":
+    target = siliconcompiler.Chip('<target>')
+    setup(target)
+    target.write_manifest('freepdk45_demo.json')

siliconcompiler/targets/gf180_demo.py

@@ -0,0 +1,77 @@
+import siliconcompiler
+from siliconcompiler.flows import asicflow, asictopflow, signoffflow, synflow
+from siliconcompiler.checklists import oh_tapeout
+from siliconcompiler.tools.openroad import openroad
+from siliconcompiler.tools._common import get_tool_tasks
+
+from lambdapdk import gf180
+from lambdapdk.gf180.libs import gf180mcu
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip, syn_np=1, floorplan_np=1, physyn_np=1, place_np=1, cts_np=1, route_np=1,
+          timing_np=1):
+    '''
+    Global foundries 180 Demo Target
+    '''
+
+    asic_flow_args = {
+        "syn_np": syn_np,
+        "floorplan_np": floorplan_np,
+        "physyn_np": physyn_np,
+        "place_np": place_np,
+        "cts_np": cts_np,
+        "route_np": route_np
+    }
+
+    # 1. Load PDK, flow, libs
+    chip.use(gf180)
+    chip.use(gf180mcu)
+    chip.use(asicflow, **asic_flow_args)
+    chip.use(synflow, syn_np=syn_np, timing_np=timing_np)
+    chip.use(asictopflow)
+    chip.use(signoffflow)
+    chip.use(oh_tapeout)
+
+    # 2. Set default targets
+    chip.set('option', 'flow', 'asicflow', clobber=False)
+    chip.set('option', 'pdk', 'gf180', clobber=False)
+    chip.set('option', 'stackup', '5LM_1TM_9K', clobber=False)
+
+    # 3. Set project specific design choices
+    chip.set('asic', 'logiclib', 'gf180mcu_fd_sc_mcu9t5v0', clobber=False)
+
+    # 4. get project specific design choices
+    chip.set('asic', 'delaymodel', 'nldm', clobber=False)
+    chip.set('constraint', 'density', 40, clobber=False)
+    chip.set('constraint', 'coremargin', 1, clobber=False)
+
+    # 5. Timing corners
+    chip.set('constraint', 'timing', 'slow', 'libcorner', 'slow', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'pexcorner', 'wst', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'fast', 'libcorner', 'fast', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'pexcorner', 'bst', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'typical', 'libcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'pexcorner', 'typ', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'check', ['power'], clobber=False)
+
+    # PSM gets stuck in a loop, must be disabled for now on gf180
+    for task in get_tool_tasks(chip, openroad):
+        chip.set('tool', 'openroad', 'task', task, 'var', 'psm_enable', 'false')
+    chip.set('tool', 'openroad', 'task', 'route', 'var', 'ant_check', 'false')
+
+
+#########################
+if __name__ == "__main__":
+    target = siliconcompiler.Chip('<target>')
+    setup(target)
+    target.write_manifest('gf180_demo.json')